JP2749889B2 - Multipoint synchronous optical writer - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multipoint synchronous optical writing device used for a high-quality laser printer or the like.

2. Description of the Related Art In general, in an optical writing apparatus such as a laser printer, a laser light source is modulated according to image information, and is scanned by a deflector such as a polygon mirror to perform optical writing on a photosensitive member or the like. At this time, it is difficult to rotate the polygon mirror or the like at a constant speed, and in practice, speed unevenness or the like occurs, causing a shift in the writing dot position. Therefore, in order to perform good optical writing in which the writing dot interval is constant, a multipoint synchronous optical writing device using a linear encoder having a large number of slits is disclosed in, for example, US Pat.
It is known from the specification of 2,389,403.

Japanese Patent Laid-Open Publication No. Sho 54-97050 discloses an example in which improvements such as facilitation of manufacturing a linear encoder are given. This is such that a video clock (pixel clock) is obtained by multiplying a photoelectric pulse signal obtained from a linear encoder by n. Specifically, the photoelectric pulse obtained by the linear encoder is compared with the reference pulse by the phase comparator of the PLL circuit, the voltage-controlled oscillator is feedback-controlled so that the two coincide, and the PLL circuit synchronizes with the photoelectric pulse, Further, the clock signal multiplied by n is output as a pixel clock which is a synchronization signal for modulating the semiconductor laser.

By the way, since the PLL circuit has a substantially constant response delay due to the circuit configuration and the like, even when a photoelectric pulse is generated, the phase of the photoelectric pulse does not immediately become the same as the phase of the reference pulse. Therefore, in the above publication, the time required for the phase of the photoelectric pulse and the phase of the reference pulse (lock-up time) elapses, and after the phase is aligned, the gate is opened and a write start signal is output. Thus, the pixel clock is used. When the semiconductor laser is modulated in synchronization with such a pixel clock, recording can be performed at a correct position where the starting point of the effective scanning line (that is, the first dot position) is aligned in the vertical direction.
Here, the shorter the lock-up time, the longer the effective scanning line, which is convenient for obtaining high resolution. In this regard, in the above publication, the frequency divider is reset by the first photoelectric pulse of the scanning line, and the phase of the photoelectric pulse and the reference pulse are forcibly adjusted to reduce the amount of phase correction, thereby achieving lock-up. I try to shorten the time.

Problems to be Solved by the Invention However, it is at a certain temperature that dots can always be recorded at a correct position by the above-mentioned publication system. In general, PL
If the L circuit changes the ambient temperature, even when locked,
The phase error between the input reference pulse and the clock obtained by dividing the PLL oscillation output as the feedback signal also changes. Therefore, even if the phase difference between the write start signal and the write clock (pixel clock) is adjusted at room temperature, a phase shift occurs due to the temperature change, and in the worst case, the position shift of the recording dot on the image is caused. appear. That is, conventionally, no measure has been taken against a change in phase error due to a temperature change.

Means for Solving the Problems Using a synchronization beam in addition to the writing beam, a PLL circuit generates a pixel clock that is phase-synchronized with a reference pulse signal generated over the entire area in the main scanning direction based on the synchronization beam. In a multi-point synchronous optical writer that modulates a laser light source for a write beam with a clock-synchronized image information to perform optical writing, a voltage corresponding to a phase difference between a write start signal in the main scanning direction and a pixel clock is generated. And a adder for adding the voltage generated by the voltage generation circuit to the input of the voltage controlled oscillator in the PLL circuit.

Further, an integrating circuit having a time constant longer than the blanking time without a write start signal and integrating the voltage generated by the voltage generating circuit and outputting the integrated voltage to the adder is provided.

Function Phase error between write start signal and pixel clock is also PLL
Since the compensation control is always performed in the voltage-controlled oscillator of the circuit, the phase error does not fluctuate even if the environmental temperature changes, and an image with good positional accuracy can be obtained.

In particular, when a voltage corresponding to the phase difference is input to the voltage controlled oscillator via the integration circuit, the voltage gradually changes and is very small compared to the original control voltage of the PLL circuit. There is no need to remove.
Further, since the time constant of this integration circuit is longer than the blanking time, the detected and generated voltage corresponding to the phase difference can be maintained until the rise of the next write start signal and used for control for phase difference change compensation. it can.

Embodiment An embodiment of the present invention will be described with reference to the drawings.

First, an outline of a laser printer to which the present invention is applied will be described with reference to FIG. This is described, for example, in JP-A-60-109667.
As shown in Japanese Patent Application Laid-Open Publication No. H10-207, a multi-point synchronization system in which a pixel clock is generated using a grating (also referred to as a slit, a grid, or a scale). A semiconductor laser (laser light source) 1 for writing which emits a modulated write beam P ₁ by the image information is provided.
The write beam P ₁ is deflected by one surface of the rotating polygon mirror 2, passes through the fθ lens 3, is reflected by the mirror 4, forms an image on the photoreceptor 5, and performs recording scanning as indicated by a scanning line 6. Is performed. On the other hand, a semiconductor laser 7 for generating a pixel clock is provided separately from the semiconductor laser 1 for writing. Synchronous beam P ₂ emitted from the semiconductor laser 7 (in the main scanning direction same position) writing position away some distance to beam P ₂ on the same reflecting surface of the polygon mirror 2 is incident on, similarly to the writing beam P ₁ Enters the fθ lens 3. After passing through the fθ lens 3, the vertical position is different, so that the synchronization beam P ₂ passes over the mirror 4 and scans the grating 8 positioned at a position optically equivalent to the photoconductor 5. This synchronization beam P ₂ passing through the transparent portion of the grating 8 are sequentially condensing imaging plurality, for example four light-receiving elements 10 a to 10 d by the lens array 9, from these light-receiving elements 10 a to 10 d, PLL circuit 11 , A reference pulse signal Sr is generated. More specifically, the light receiving element
The light-receiving signals received and photoelectrically converted by 10 are respectively amplified and then added by an adding circuit. This allows
It becomes a pulse train signal over the entire scanning length in the main scanning direction according to the light and dark arrangement of the grating 8, and after being shaped as necessary, the PLL circuit 11 generates and outputs a pixel clock W _CLK obtained by multiplying the reference pulse signal Sr by n. You.

Here, the PLL circuit 11 has a phase comparator (P
D) 12, a low-pass filter (LPF) 13, a voltage controlled oscillator (VCO) 14, and a 1 / N divider 15 are connected in a loop. That is, the comparator 12 outputs a pulse corresponding to the phase difference between the reference pulse signal Sr and the feedback pulse signal Sb which is obtained by multiplying the feedback output of the voltage controlled oscillator 14 by N from the 1 / N frequency divider 15 and fed back. and, after smoothing the pulse as the control voltage upsilon ₀ by the low-pass filter 13, a control voltage υin of the voltage controlled oscillator 14. The voltage controlled oscillator 14 controls the feedback pulse signal Sb obtained by dividing the output by N so that the phase is synchronized with the reference pulse signal Sr, and outputs the pixel clock _WCLK to the drive circuit of the semiconductor laser 1.

In this embodiment, a phase error change compensation circuit is added to such a PLL circuit 11. This circuit includes a write start signal L Gate in the main scanning direction synchronized with the reference pulse signal Sr.
First, the write start signal L Ga
There is provided a counter 16 that is cleared when te falls. Also, the pixel clock W _CLK from the voltage controlled oscillator 14
Is provided at a clock terminal and a write start signal L Gate is input at a D terminal. The output of this D flip-flop 17 is a write start signal L Ga
te and the write start signal LG
for a period of time corresponding to the phase difference between the rising edge of ate and pixel clock W _CLK is to the counter 16 in the enabled state. The counter 16 counts and holds the number of oscillation pulses input from the oscillator 19 during the enable state. The output side of the counter 16 is connected to a D / A converter 20 that converts the count value into an analog value. D
Analog value to the output side of the / A converter 20, i.e., the write start signal L Gate and the current produced as a control voltage υp a voltage corresponding to the phase difference between the rising edge of the pixel clock W _CLK - voltage converting circuit (IV) 21 is It is connected. The counter 16, the D / A converter 20, and the current-voltage conversion circuit 21 constitute a voltage generation circuit 22 corresponding to a phase difference. Further, the control voltage of the current-voltage conversion circuit 21 is provided on the output side.
integrating circuit 23 for smoothing the control voltage upsilon ₁ to p are connected. The integrating circuit 23 is one having a time constant longer than the blanking time T ₁ corresponding to between the output time T ₀ of the write start signal L Gate. Then, the adder 24 to the control voltage upsilon ₁ by adding the control voltage upsilon ₀ from the low-pass filter 13 is input to the voltage controlled oscillator 14 is provided.

In such a configuration, first, at room temperature (normal temperature) and when the PLL circuit 11 is locked, the write start signal L
So that the phase difference between the rise of Gate and pixel clock W _CLK is 180 °, the gain of the PLL circuit 11 and compensation circuit is adjusted.

Then, in an actual write operation, a write start signal
The counter 16 cleared by the fall of the L Gate is enabled by the rise of the write start signal L Gate, and counts the number of oscillation pulses of the oscillator 19. This counting operation is stopped at the rising _edge of the pixel clock _{WCLK, and} the counted value is held until the write start signal LGate falls. Therefore, the count value in such counter 16 is equivalent to a phase difference between the rising edge of the write start signal L Gate and the pixel clock W _CLK, after being converted into an analog value by the D / A converter 20, current - The control voltage Δp is generated by the voltage conversion circuit 21. The control voltage υp is input to the adder 24 becomes the smoothed control voltage upsilon ₁ by the integration circuit 23, the normal control voltage upsilon ₀ and summed with the voltage controlled oscillator resulting from the low pass filter 13 in the PLL circuit 11 Entered in 14.

In such an operation, the phase difference between the write start signal L Gate and the rising edge of the pixel clock W _CLK becomes larger than that at normal temperature (180 °) due to a change in environmental temperature, and as shown in FIG. When the phase difference) becomes W ₀ , the count value of the counter 16 increases, and the generated control voltage Δp also becomes larger than at room temperature. This control voltage υp
When the write start signal L Gate falls, it is cleared to 0 as shown in FIG. 2, but the write start signal L Gate is written by the integrating circuit 23 having a time constant longer than the blanking time T ₁ of the write start signal L Gate. It is maintained until the next rising of the signal L Gate. Thus, by using the control voltage upsilon _1, the phase difference W ₀ controls the voltage controlled oscillator 14 so that the phase difference at the normal temperature.

On the other hand, when the phase difference between the write start signal L Gate and the rise of the pixel clock W _CLK becomes smaller than that at normal temperature, and the enable period (phase difference) becomes W ₁ as shown in FIG. In this case, the count value of the counter 16 becomes smaller, and the generated control voltage Δp becomes smaller than that at normal temperature. Thus, by using the control voltage upsilon ₁ obtained by integrating this phase difference W ₀ controls the voltage controlled oscillator 14 so that the phase difference at the normal temperature.

Such control voltage upsilon ₁ is for gradually varying in accordance with the time constant of the integrating circuit 23, and be very small compared the variation width to the original control voltage upsilon ₀ from the low-pass filter 13 side, The PLL circuit 11 does not come out of the locked state.

As described above, the present invention provides a voltage generation circuit that generates a voltage corresponding to a phase difference between a write start signal in the main scanning direction and a pixel clock for modulating a laser light source, and a voltage corresponding to the phase difference. Is added to the input of the voltage controlled oscillator in the PLL circuit by the adder, so that the phase error between the write start signal and the pixel clock is always compensated and controlled in the voltage controlled oscillator of the PLL circuit. Even if the temperature changes, the phase error can be prevented from fluctuating, and an image having good positional accuracy can be obtained. In particular, by gradually inputting the voltage corresponding to the phase difference to the voltage-controlled oscillator through the integration circuit, The voltage fluctuates very much in comparison with the original control voltage of the PLL circuit, and the above-described control can be performed by preventing the unlocking of the PLL circuit. Since the time constant of the integrating circuit is longer than the blanking time, the detected and generated voltage corresponding to the phase difference can be maintained until the next rise of the write start signal, and can be used for control for phase difference change compensation. is there.

[Brief description of the drawings]

The drawings show an embodiment of the present invention. FIG. 1 is a block diagram, FIG. 2 is a timing chart, and FIG. 3 is a perspective view showing an example of a laser printer. 1: laser light source, 11: PLL circuit, 14: voltage controlled oscillator, 2
2… Voltage generation circuit, 23… Integration circuit, 24… Adder, P ₁ … Write beam, P ₂ … Sync beam, Sr… Reference pulse signal, L
Gate: Write start signal, W _CLK : Pixel clock, T ₁ : Blanking time

Claims (2)

(57) [Claims] 1. A synchronizing beam is used in addition to a writing beam, and a PLL circuit generates a pixel clock phase-synchronized with a reference pulse signal generated over the entire area in the main scanning direction based on the synchronizing beam. In a multi-point synchronous optical writing device that performs optical writing by modulating a laser light source for a writing beam with synchronized image information, a voltage corresponding to a phase difference between a writing start signal in the main scanning direction and the pixel clock is generated. A multipoint synchronous optical writing device comprising a voltage generating circuit, and an adder for adding a voltage generated by the voltage generating circuit to an input of a voltage controlled oscillator in the PLL circuit. 2. An integration circuit having a time constant longer than a blanking time without a write start signal and integrating a voltage generated by a voltage generation circuit and outputting the integrated voltage to an adder. The multipoint synchronous optical writing device according to the above.