JP2745940B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device provided with an insulating layer having a wiring pattern on a conductive substrate.

[0002]

2. Description of the Related Art As semiconductor devices become more highly integrated, the package on which the semiconductor device is mounted has been reduced in thermal resistance.
As shown in FIG. 5, a package in which a semiconductor element mounting portion of an insulating substrate having a wiring pattern is formed of a metal plate 12 having good thermal conductivity (for example, Japanese Patent Application No. 59-15642).
6, Japanese Patent Application No. 59-47506) to form a semiconductor device. In this conventional semiconductor device, the metal plate 12
After the semiconductor element is mounted on the semiconductor device 8, the power supply, GND and signal wiring patterns 3, 6 formed on the insulating layer 2 and the semiconductor element 8 are electrically connected by the thin metal wires 9, and then sealed with the sealing resin 10. A semiconductor device has been formed. In this conventional semiconductor device, heat generated from the semiconductor element 8 is radiated to the outside through the metal plate 12, so that the semiconductor element can be used for a highly integrated semiconductor element with large power consumption.

As shown in FIG. 6, when further lowering the heat resistance is required, a heat sink 11 made of aluminum or the like is fixed to a metal plate 12 to achieve a lower heat lowering effect.

[0004]

In this conventional semiconductor device, it is possible to cope with a semiconductor element with high power consumption by utilizing a heat radiation effect from a metal plate. However, wiring formed on an insulating substrate is possible. Due to power supply noise caused by inductance components of patterns, especially power supply and GND wiring patterns, there is a problem that malfunction occurs when a high-speed and multi-bit semiconductor element (for example, 64 bit microcomputer, ECLG / A, etc.) is mounted, There were restrictions on the use of semiconductor devices.

[0005]

SUMMARY OF THE INVENTION The semiconductor device of the present invention has a conductor substrate at the center of the semiconductor device in order to enable high-power consumption, high-speed and multi-bit semiconductor elements to be mounted. The conductor substrate is electrically connected to an external lead serving as a sub-potential of the semiconductor element. With this structure, the wiring shape of the sub-potential becomes a perfect plate shape,
The inductance component of the wiring can be reduced to 1/3 or less of that of the related art, and high-speed operation can be performed.

[0006] In the power supply wiring, an inductance component can be reduced by forming a plate wiring on a conductive substrate via a dielectric thin film layer. Further, in this structure, since a thin-film bypass capacitor is formed between the power supply and GND, the effect of reducing power supply noise can be increased.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a sectional view of one embodiment of the present invention. Also,
FIG. 2 is an enlarged sectional view of FIG. 1A. A signal wiring pattern 3 is formed on the lower surface of the conductor substrate 1 via an insulating layer 2, and the lower surface is covered with a solder resist 4. A power supply plate pattern 6 is formed on the upper surface of the conductor substrate via a dielectric layer 5, and is covered with a solder resist 4. External lead 1
3 is electrically connected to an arbitrary signal wiring pattern 3,
The conductor substrate 1 and the power supply plate pattern 6 are electrically insulated by an insulator 7. In addition, external lead 1
Reference numeral 4 denotes an external lead for supplying a sub-potential of the semiconductor element 8, which is press-fitted into a hole provided in the conductive substrate and fixed with solder or screwed into a conductive gas screw hole and fixed with the conductive substrate 1. Electrically connected to the signal wiring pattern 3
The power supply plate pattern 6 is electrically insulated from the power supply plate pattern 6 by an insulator 7. The external lead 15 is a power supply external lead, is electrically connected to the power supply plate pattern 6, and is electrically insulated from the other wiring patterns 3 by the insulator 7.

The semiconductor element 8 is mounted at the center of the conductor substrate, and is electrically connected to the signal wiring pattern 3, a part of the power supply plate pattern 6 and a part of the sub-potential conductor substrate 1 by a thin metal wire 9, Thereafter, the semiconductor device is sealed with the sealing resin 10 to form a semiconductor device.

In this embodiment, the heat generated by the semiconductor element 8 is dissipated through the conductive substrate 1 and the power supply to the semiconductor element 8 is performed by a low-inductance plate-structured wiring. Less occurrence, high speed and multi-bit support are possible.

FIG. 3 is a partially enlarged sectional view showing a second embodiment of the present invention. In this embodiment, a dielectric layer 5 and a power supply plate pattern 6 are provided on both sides of a conductive substrate 1, and an insulating layer 2, a signal wiring pattern 3, and a solder resist 4 are sequentially laminated on one of the power supply plate patterns. And The other points such as the connection of the external leads 13, 14, 15 are the same as those of the first embodiment.

This structure has the advantage that the capacity of the bypass capacitor formed between the power supply GND can be increased. As an example, in the case where a semiconductor device is a 208-pin pinglit array, the dielectric layer is formed of Al ₂ using a sputtering method.
When O _{3 is} formed to have a thickness of 10 μm, it is possible to make a bypass capacitor of about 30 nF. If a larger value is required for the capacity of the bypass capacitor, SrTiO ₂ having a high dielectric constant is used as the dielectric layer.
By using such a method and reducing the thickness, a bypass capacitor of about 1 μF can be formed.

FIG. 4 is a partially enlarged sectional view of a third embodiment of the present invention. This embodiment has a structure in which one external lead 16 for power supply is added to the structure of the second embodiment. That is, similarly to the second embodiment, the dielectric layer 5 and the power supply plate pattern 6 are formed on both surfaces of the conductive substrate 1, and different power supply potentials are applied to the power supply plate pattern 6 by the external power supply leads 15 and 16. I am giving. With this structure, Bi ・ C
There is an advantage that a semiconductor element requiring multiple power supplies such as MOS + ECL can be mounted.

[0013]

As described above, the sub-potential of the semiconductor element is supplied by the conductor substrate, and the power supply potential is supplied by the plate pattern formed on the conductor substrate via the dielectric, thereby achieving high power consumption. There is an effect that a semiconductor device corresponding to power and high speed can be realized.

[Brief description of the drawings]

FIG. 1 is a sectional view of a first embodiment of the present invention.

FIG. 2 is an enlarged sectional view of FIG. 1A part.

FIG. 3 is a sectional view of an external lead portion according to a second embodiment of the present invention.

FIG. 4 is a sectional view of an external lead portion showing a third embodiment of the present invention.

FIG. 5 is a sectional view of a conventional low heat resistance type.

FIG. 6 is a cross-sectional view when a heat sink is mounted on the semiconductor device of FIG. 5;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Conductive substrate 2 Insulating layer 3 Signal wiring pattern 4 Solder resist 5 Dielectric layer 6 Power supply plate pattern 7 Insulator 8 Semiconductor element 9 Thin metal wire 10 Sealing resin 11 Heat sink 12 Metal plate 13 External lead for signal 14 For sub-potential External lead 15, 16 External lead for power supply

Claims (6)

(57) [Claims] An insulating layer having a wiring pattern is provided on at least one surface of a conductor substrate, a semiconductor element is mounted on the conductor substrate, and the wiring pattern and an electrode on the semiconductor element are formed by a thin metal wire. A semiconductor device sealed with a resin after being electrically connected, wherein the conductive substrate is electrically connected to an external lead of a sub-potential of a semiconductor element. 2. The semiconductor device according to claim 1, wherein a power supply pattern is formed on at least one surface of the conductive substrate via a dielectric layer. 3. The semiconductor device according to claim 1, wherein said conductive substrate is made of a copper alloy or an iron-nickel alloy. 4. The semiconductor device according to claim 2, wherein the dielectric layer formed on the semiconductor substrate is made of Al ₂ O ₃ , SiO _2
2, wherein a is an inorganic dielectric layer of SrTiO _2, and the like. 5. The semiconductor device according to claim 1, wherein the external leads electrically connected to the conductor substrate are connected by solder after being pressed into holes provided in the conductor substrate. A semiconductor device characterized by the above-mentioned. 6. The semiconductor device according to claim 1, wherein external leads electrically connected to the conductor substrate are fixed to screw holes provided in the conductor substrate.