JP2745645B2 - Method for manufacturing semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Purpose] Outline Industrial field of application Conventional technology Problems to be solved by the invention Means for solving the problem Operation Example Process plan view of one embodiment (FIG. 1) FIG. 2 is a sectional view taken along the line AA of one embodiment (FIG. 2). FIG. 3 is a sectional view taken along the line BB of the embodiment (FIG. 3). Completed view of the memory cell (FIG. 4). The present invention relates to a method for manufacturing a semiconductor memory device, and more particularly, to a method for forming a substrate contact of a charge storage electrode having a two-layer conductive layer structure in a one-transfer transistor / one storage capacitor cell. The purpose is to form the contact window between the storage electrode and the semiconductor substrate with high accuracy and reliability. When forming the storage electrode of the storage capacitor, one direction is defined by the gate electrode and the other three directions are defined by the field insulating film. Impurities Forming a lower insulating film extending from the impurity diffusion region on the gate electrode and the field insulating film on the diffusion region; and displaying the lower insulating film on the impurity diffusion region on the lower insulating film. Forming a first conductive layer having a first opening that emerges, a second conductive layer on the first conductive layer crossing the first opening in a direction parallel to the gate electrode;
Forming an etching-resistant layer having an opening by etching the lower insulating film exposed in the second opening by using the etching-resistant layer and the first conductive layer as a mask; Selectively exposing the surface of the impurity diffusion region in the hole, removing the etching-resistant layer, and then forming the first opening and the second opening on the first conductive layer. Forming a second conductive layer in contact with the impurity diffusion region in the common portion of the above, and patterning the second conductive layer and the first conductive layer in a peripheral portion of the first opening by using the same mask. To be configured.

[Industrial applications]

The present invention relates to a method for manufacturing a semiconductor memory device, and more particularly to a two-layer conductive layer which is constituted by one transfer transistor and one storage capacitor (one transistor and one capacitor) and in which storage electrodes of the storage capacitor are directly stacked. The present invention relates to a method for forming a connecting portion between a storage electrode and a substrate in a semiconductor memory device having a volatile memory cell constituted by the above.

2. Description of the Related Art In recent years, a volatile semiconductor memory device in which a memory cell is constituted by one transistor and one capacitor has responded to a demand for large-scale and high-integration, and reference dimensions of respective parts have been remarkably miniaturized. In order to compensate for the decrease in the storage capacity when a storage cell is provided, a memory cell having a storage electrode having a two-layer conductive layer structure in which two conductive layers are directly stacked to increase the level difference contributing to the storage capacity has been provided. Due to the increase in steps on the upper surface of the substrate, it is becoming difficult to perform lithography, especially exposure techniques, when forming various connection regions.

[Conventional technology]

FIG. 5 is a schematic side sectional view of a conventional memory cell having a one-transistor / one-capacitor structure. In the figure, 1 is p
Type silicon (Si) substrate, 2 is a field oxide film, 3 is a gate oxide film, 4 is a gate electrode, 5 is an n ⁺ type source region, 6
Is an n ⁺ type drain region (bit line), 7 is a lower insulating film, 8 is a contact window, 9 is a storage electrode made of polycrystalline Si or the like, 10 is a dielectric film, 11 is a counter electrode made of polycrystalline Si or the like,
12 is a covering insulating film, 44 is a word line formed by extending the gate electrode of an adjacent transistor, TT is a transfer transistor, SC
Indicates a storage capacity.

As shown in this figure, in a memory cell having a conventional storage capacitor SC in which the storage electrode 9 is formed of a single conductive layer 9A, a contact window 8 for connecting the storage electrode 9 to the source region 6 is formed.
Are the process plan views of FIGS. 6 (a) to 6 (d) and their AA
It was formed by the following method which will be described with reference to the process sectional views of FIGS.

That is, as shown in FIGS. 6A and 7A, the gate electrode 4 is formed on the element region 13 defined by the field oxide film 2 via the gate oxide film 3 as usual (field oxidation). A word line 44, which is an extension of the gate electrode of the adjacent cell, is formed on the film 2), and the source region 5 and the drain region 6 are formed by ion implantation using the gate electrode 4 as a mask.
After the lower insulating film 7 is deposited on the substrate, a resist layer 14 is formed on the lower insulating film 7 as shown in FIGS. 6 (b) and 7 (b). A pattern having a size and shape corresponding to the contact window is exposed on the resist layer 14 above the region 5, and normal development is performed to form an etching opening 15 having a size and shape corresponding to the contact window 8 in the resist layer 14. Then, as shown in FIGS. 6 (c) and 7 (c), the lower insulating film exposed in the opening 15 by anisotropic etching through the opening 15 for etching the resist layer 14. In this method, a contact window 8 is formed by selectively removing the contact window 7.

6 (d) and 7 (d) show the contact window 8
After the formation, the resist layer 14 is removed, and a polycrystalline film which is in contact with the source region 6 at the contact window 8 is formed on the lower insulating film 7.
The state where the storage electrode 9 made of the first conductive layer 9A of Si or the like is completed is shown.

As described above, in the conventional structure using the storage electrode 9 composed of one conductive layer 9A, the step formed around the contact window forming region is about 3000 ° corresponding to about 1/2 of the field oxide film 2. Since the total thickness is about 7000 mm or less including about 4000 mm corresponding to the gate electrode 4, the thickness t ₁ (see FIG. 7B) of the resist film 14 in the portion where the contact window 8 is formed also corresponds to the step. Not too big,
Therefore, even if a pattern having a dimension corresponding to the contact window is exposed as is generally performed, deformation due to insufficient exposure does not occur so much at the bottom of the etching hole pattern after resist development, and It was also possible to form a contact window of a very small size close to the limit with high precision.

On the other hand, in a highly integrated semiconductor memory device, recently, as shown in the schematic cross-sectional view of FIG. 8, the storage electrode 9 is directly connected to the frame-shaped first conductive layer 9A and the source region 5. Second
(Second layer) and a conductive layer 9B, and the height h
Has been proposed to increase the area of the side surface of the storage electrode by increasing the height of the storage electrode, thereby increasing the storage capacity. (The reference numerals in the figure are the same as those in FIG. 5.) When a conventional contact window forming method is applied to this structure, it will be described with reference to the process sectional views of FIGS. 9 (a) to 9 (d). Process. (The reference numerals in the figure are the same as those in FIG. 8.) That is, prior to forming the contact window, as shown in FIG. 9A, a region corresponding to the upper part of the source region 5 on the lower insulating film 7 is formed. After forming the first (first layer) conductive layer 9A having the opening 16 to be exposed, a resist layer 14 is applied and formed on the substrate as shown in FIG. As shown in FIG. 9C, an opening 115 for etching is formed in the resist layer 14 by exposing and developing a pattern having the dimensions and shapes of the contact windows. Then, as shown in FIG. The lower insulating film 7 is etched through the opening 115 to form a contact window 108.

[Problems to be solved by the invention]

However, in the case of the storage electrode having the above-described two-layer conductive layer structure, according to the conventional method for forming a contact window, as shown in FIG. Since a step having a height of about 3000 to 4000 mm corresponding to the thickness of the conductive layer 9A is formed, the thickness (t ₂ ) of the resist layer 14 on the contact window formation region is significantly larger than that of the single-layer conductive layer structure. It gets thicker. For this reason, in a situation where the cell is highly integrated and the outer dimensions of the contact window are reduced to near the limit of exposure, exposure of a pattern having a size and shape corresponding to the size and shape of the contact window is performed as in the conventional method. Due to the small amount of light, the bottom of the resist layer 14 was underexposed, and the shape of the opening 115 for etching of the developed resist layer 14 was reduced and deformed as shown in FIG. 9 (c). It will have an abnormal shape. For this purpose, the opening 11 for etching the resist layer 14 is formed.
As shown in FIG. 9D, the contact window 108 formed by the anisotropic etching means via 5 has a problem that it is extremely reduced or not penetrated.

Accordingly, the present invention provides a semiconductor memory device that can reliably and accurately form a contact window between a storage electrode and a semiconductor substrate, which has a surface step increased by stacking two conductive layers to increase storage capacitance. The purpose of the present invention is to provide a manufacturing method.

[Means for solving the problem]

The object of the present invention is to provide a method of manufacturing a semiconductor memory device having a storage cell including one transfer transistor and one storage capacitor, wherein a storage electrode of the storage capacitor includes two conductive layers. In forming the storage electrode of the storage capacitor, one direction is formed on the impurity diffusion region defined by the gate electrode and the other three directions by the field insulating film.
Forming a lower insulating film extending on the gate electrode and the field insulating film from the impurity diffusion region; and exposing the lower insulating film on the impurity diffusion region on the lower insulating film. Forming a first conductive layer having openings,
Forming, on the first conductive layer, an etching-resistant layer having a second opening crossing over the first opening in a direction parallel to the gate electrode, the etching-resistant layer and the first conductive layer; Etching the lower insulating film exposed in the second opening by using the layer as a mask to selectively expose the surface of the impurity diffusion region in the first opening; Forming a second conductive layer on the first conductive layer in contact with the impurity diffusion region on the first conductive layer at a common portion of the first opening and the second opening, The problem is solved by a method of manufacturing a semiconductor memory device according to the present invention, which comprises a step of patterning a second conductive layer and a first conductive layer in the periphery of the first opening with the same mask.

(Operation)

That is, in the method of the present invention, when forming a contact window for connecting a storage electrode formed by laminating two conductive layers to a substrate, two opposing sides on one side of the contact window are the first side. Two sides in one direction of the first opening formed in the conductive layer and exposing the lower insulating film are formed in a self-aligned manner, and only two opposing sides in the other direction are the first side of the conductive layer.
Are formed in a self-aligned manner on two opposing sides of a second opening formed in the resist layer across the opening.

Therefore, the width of one side of the second opening formed in the resist layer can be relaxed and expanded irrespective of the opening width of the contact window, and when the contact window size is reduced to near the critical dimension of exposure, In addition, since the exposure area can be widened to the one width side, a sufficient exposure light amount can be obtained so that the resist bottom can be surely exposed, and the dimensional accuracy of the aperture pattern after development is reduced. Improved and stable, pattern failure,
Reproduction rate etc. decrease.

〔Example〕

 Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.

1 (a) to 1 (e) are process plan views of an embodiment of the method of the present invention, and FIGS. 2 (a) to 2 (e) are process cross sectional views showing cross sections taken along line AA of the embodiment. 3 (a) to 3 (e) are process sectional views showing a cross section taken along line BB of the embodiment, and FIG. 4 is a completed view of a volatile memory cell according to the method of the present invention. FIG. 3B is a cross-sectional view taken along the line AA, and FIG. 3C is a cross-sectional view taken along the line BB.

 The same objects are denoted by the same reference symbols throughout the drawings.

FIGS. 1 (a), 2 (a), and 3 (a). A two-layered conductive film having a one-transistor / one-capacitor structure and having storage electrodes of storage capacitors directly stacked according to the method of the present invention. When forming a volatile memory cell composed of layers, for example, a field oxide film 2 having a thickness of, for example, about 6000 mm which defines an element region 13 is formed on a p-type Si substrate 1 by a usual method. A gate electrode 4 made of polycrystalline Si or the like is formed across the region via a gate oxide film 3 (at this time, the gate electrode 4 of the adjacent transistor forms a word line 44 and extends over the field oxide film 1). After forming an n ⁺ -type source region 5 and an n ⁺ -type drain region (bit line) 6 in the element region 13 by ion implantation using the gate electrode 4 as a mask, chemical vapor deposition (CVD) is performed on the substrate. ) Method, etc. O ₂ ) is formed on the lower insulating film 7 having a thickness of about 1000 to 2000 °.

1 (b), 2 (b) and 3 (b). Next, a thickness of 3000 is formed on the lower insulating film 7 by the CVD method.
A first polycrystalline Si layer 9A of about Å is formed. Note that the first
Since the height of the polycrystalline Si layer 9A contributes to the capacitance, the thickness thereof is changed according to the requirement.

Next, the lower insulating film 7 is formed on the first polycrystalline Si layer 9A along the source region 5 by ordinary photolithography.
The first opening 16 having a narrow width of about 1 μm, for example, in the vicinity of the exposure limit, is formed.

1 (c), 2 (c) and 3 (c) Next, a resist layer 14 having a thickness of about 1 μm on a flat portion is formed on the surface on which the first polycrystalline Si layer 9A is formed. Is formed on the resist layer 14, for example, in the vicinity of an exposure limit which crosses the upper part of the first opening 16 in parallel with the gate electrode 4.
A pattern having a width of about 1 μm is exposed and subjected to normal development to form a first opening having a width of about 1 μm on the resist layer 14.
A second opening 17 having a width of about 1 .mu.m, which crosses at right angles to 16, is formed. Here, the length of the exposure region is designed to be larger than the width, for example, about twice. Thus, even if the width of the exposure pattern is close to the critical dimension, the length direction is designed to be significantly larger than the critical dimension.
Since the amount of exposure light is sufficiently ensured up to the bottom of the substrate 14, the bottom of the second opening 17 formed by development does not undergo a reduction deformation due to insufficient exposure.

Next, using the resist layer 14 and the first polycrystalline Si layer 9A exposed in the resist layer 14 as a mask, the resist layer
14 and the first opening 16 of the first polycrystalline Si layer 9A.
Is removed by anisotropic dry etching means, and two opposing sides of the lower insulating film 7 in the direction parallel to the gate electrode 4 are in the same direction. The self-aligned two sides of the first opening 16 of the polycrystalline Si layer 9A are aligned with the two sides of the resist layer 14 in the direction perpendicular to the gate electrode 4 in the same direction. A contact window 8 which is self-aligned with two opposing sides of 17 and whose width in each direction is aligned with the width of the first opening 16 and the second opening 17 and has a minute width close to the exposure limit of about 1 μm. To form

1 (d), 2 (d), and 3 (d). Next, the resist layer 14 is removed, and then,
A second polycrystalline Si layer 9B having a thickness of about 1000 mm is formed by a CVD method, and the first and second polycrystalline Si layers are formed by a usual method.
9B is given an n ⁺ -type conductivity.

1 (e), 2 (e) and 3 (e). Next, the second polycrystalline Si layer 9B and the first polycrystalline silicon are matched with one mask by ordinary photolithography. Si
The layer 9A is patterned around the first opening 16 to complete the storage electrode 9 having a two-layered conductive layer structure according to the method of the present invention.

Note that, in this structure, the end face of the first polycrystalline Si layer 9A contributes as a capacitance forming surface, and the level difference of the storage electrode 9 formed on the contact window 8 side is larger than that of the conductive layer single layer structure. In addition, the storage capacity can be increased. Therefore, it goes without saying that the storage capacitance increases as the thickness of the first polycrystalline Si layer 9A increases.

Thereafter FIG. 4 (a), (b), as shown in completion drawing of the volatile memory cell according to the method of the present invention (c), the surface to a thickness 100Å approximately nitride Si of storage electrode 9 (Si ₃ N ₄₎ of film or the like dielectric film 10 is formed, a counter electrode 11 having a thickness of about 2000Å of polycrystalline Si layer or the like having conductivity on the substrate to form, about 5000~6000Å thereon The volatile memory cell according to the method of the present invention is completed by forming a coating insulating film 12 having a thickness.

As is apparent from the above embodiment, according to the method of the present invention, two opposing sides on one side of the contact window for connecting the storage electrode formed by laminating two conductive layers to the substrate are formed by the accumulation. Two sides on one side of a first opening exposing a lower insulating film formed on a first conductive layer used for an electrode are formed in a self-aligned manner, and only two opposing sides on the other side are formed. And a second opening formed in the resist layer across the first opening of the conductive layer and formed on two opposite sides of the resist layer in a self-aligned manner.

Therefore, the width of the second opening formed in the resist layer in one direction can be reduced irrespective of the opening width of the contact window, and when the contact window dimension is reduced to near the critical dimension of exposure. In addition, since the exposure area can be widened in the above-described one direction, a sufficient amount of exposure light can be obtained so that the bottom of the resist can be surely exposed. The hole pattern can be formed with high accuracy and without deformation. Therefore, by performing etching using the resist layer and the first conductive layer as a mask, a fine contact window having four sides close to the exposure limit at the intersection of the first opening and the second opening. Can be formed with high precision and without variation.

〔The invention's effect〕

As described above, according to the present invention, a connection between a storage electrode and a substrate in a volatile memory cell having a storage electrode having a structure in which two conductive layers are stacked is formed in a minute region through a fine contact window. It can be done reliably,
The integration and the yield and the reliability of the volatile semiconductor memory device having the one-transistor / one-capacitor structure can be improved.

[Brief description of the drawings]

1 (a) to 1 (e) are process plan views of an embodiment of the method of the present invention, FIGS. 2 (a) to 2 (e) are cross-sectional views of the embodiment taken along the line AA, FIG. 4 (a) to 4 (e) are cross-sectional views taken along the line BB of the embodiment, FIG. 4 is a completed view of a volatile memory cell according to the method of the present invention, FIG. 4 (a) is a plan view, and FIG. AA arrow sectional drawing, (c)
Is a cross-sectional view taken along the line BB, FIG. 5 is a schematic side cross-sectional view of a conventional memory cell having a single-layered storage electrode, and FIGS. FIGS. 7A to 7D are process cross-sectional views of a method of forming a storage electrode having the same one-layer structure, FIG. 8 is a schematic cross-sectional view of a storage electrode having the two-layer structure, and FIGS. 9 (a) to 9 (d) are process sectional views of a conventional method for forming a storage electrode having a two-layer structure. In the figure, 1 is a p-type Si substrate, 2 is a field oxide film, 3 is a gate oxide film, 4 is a gate electrode, 5 is an n ⁺ -type source region, 6 is an n ⁺ -type drain region (bit line), and 7 is a lower insulating layer. 8, 108 are contact windows, 9 is a storage electrode, 9A is a first polycrystalline Si layer (first conductive layer), 9B is a second polycrystalline Si layer (second conductive layer), 10 is Dielectric film, 11 is a counter electrode, 12 is a covering insulating film, 13 is an element region, 14 is a resist layer, 15, 115 are etching openings for contact windows, 16 is a first opening, and 17 is a second opening. Opening, 44 indicates a word line, TT indicates a transfer transistor, and SC indicates a storage capacitor.

Claims (1)

(57) [Claims] 1. A method of manufacturing a semiconductor memory device, comprising: a storage cell formed by one transfer transistor and one storage capacitor, wherein a storage electrode of the storage capacitor is formed by two conductive layers. In forming the storage electrode of the storage capacitor, one direction is on the impurity diffusion region defined by the gate electrode and the other three directions are defined by the field insulating film, and from the impurity diffusion region on the gate electrode and the field insulating film. Forming a first conductive layer having a first opening exposing the lower insulating film above the impurity diffusion region, on the lower insulating film; Forming, on the first conductive layer, an etching-resistant layer having a second opening crossing the first opening in a direction parallel to the gate electrode; and forming the etching-resistant layer and the first conductive layer. Using the layer as a mask Removing the lower insulating film exposed in the second opening by etching to selectively expose the impurity diffusion region surface in the first opening; removing the etching-resistant layer; On the conductive layer of
Forming a second conductive layer in contact with the impurity diffusion region at a portion common to the first opening and the second opening, wherein the second conductive layer and the first conductive layer are the same. A method for manufacturing a semiconductor memory device, comprising a step of patterning a peripheral portion of the first opening with a mask.