JP2737495B2 - I / O control unit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output control device controlled by a processor, and more particularly to an input / output control device capable of preventing important trace data from disappearing among trace data indicating a process executed by the processor. To an input / output control device.

A disk device is used as an external storage device of a computer system. This disk device is controlled by a disk control device and transfers data to and from a channel.

When the data transfer between the disk device and the channel is stopped due to a failure or the like, the processing efficiency of the computer system is reduced. Therefore, the disk control device stores history information indicating the processing executed by the processor, , A trace memory for storing trace data,
When a failure occurs, the cause of the failure is pursued based on the trace data read from the trace memory, and the failure is promptly eliminated.

[0004] Therefore, it is necessary that the trace data at the time of occurrence of a fault be stored.

[0005]

2. Description of the Related Art FIG. 8 is a block diagram for explaining an example of the prior art. Channels 1 to 4 are connected to the interface circuit 8 of the disk control device 5, and disk devices 6 to 7 are connected to the interface circuit 10. Then, the processor 11 of the disk control device 5
When a program stored in the control memory 12 is read and operated, and the data writing is instructed via the interface circuit 8, for example, by specifying the disk device 6 from the channel 1, the disk device is transmitted via the interface circuit 10. The head No. 6 is positioned at the designated address.

When data can be written to the disk device 6, the channel 1 is transmitted via the interface circuit 8.
, And instructs the data transfer control circuit 9 to transfer the data transmitted by the channel 1 to the disk device 6 via the interface circuit 10 and write the data to the disk device 6.

When the processor 11 designates the disk device 7 from the channel 2 via the interface circuit 8 and instructs data reading, the processor 11 designates the head of the disk device 7 via the interface circuit 10 at the designated address. And instructs the data transfer control circuit 9 to read the data read by the disk device 7, and transfers the data to the channel 2 via the interface circuit 8.

The same applies to access from channel 3 or channel 4. Thus, the processor 11
Receives a command from the channel and, upon executing the received command, returns an end status to the channel. During this command processing, a command is issued to the disk device, and the end status is received.

Also, for example, an error detection circuit provided in the data transfer control circuit 9 has an error in the data being transferred,
If such an error has been detected and reported, error information is created and the corresponding channel is notified of the abnormal termination of the command.

[0010] When there is a retry request from the channel in response to the abnormal end notification, the processor 11 executes a retry process. Then, the processor 11
The trace data created based on these operations is sent to the trace memory 13 and stored.

That is, the processor 11 receives the command from the channel, issues the command to the disk device, receives the end status from the disk device,
Issuance of an end status to the channel is stored as trace data, and during retry processing, each time retry is repeated, trace data indicating the history of the processing is sequentially written to the trace memory 13.

[0012]

As described above, when the retry processing is conventionally performed, the amount of trace data stored in the trace memory 13 increases, but the trace data is recorded up to the last address of the trace memory 13. Then, the next trace data is sequentially written again from the head address of the trace memory 13.

Therefore, the already stored trace data is erased and lost sequentially from the head address. As a result, there is a problem that important trace data before and after the occurrence of an error may be lost depending on the frequency of access to the disk device or the frequency of retry occurrence.

In view of such a problem, the present invention provides a register for storing the contents specifying the trace data to be extracted from the trace data stored in the trace memory 13, and a storage means for storing the extracted trace data. Is provided so that only necessary trace data can be left among the trace data stored in the trace memory 13.

[0015]

FIG. 1 is a block diagram for explaining the principle of the present invention. The input / output controller is shown in Fig. 1 (A)
As shown in (1), there is provided a trace memory 13 for storing trace data indicating the processing executed by the processor 11.

A first storage means 14 for storing information for extracting necessary trace data from the trace data stored in the trace memory 13, based on the information stored in the first storage means 14. A second storage unit for storing the extracted trace data; and a trace extracted from the trace data stored in the trace memory based on information stored in the first storage unit. The data is stored in the second storage unit 15.

Further, as shown in FIG. 1B, the input / output control device includes a trace memory 13 for storing trace data indicating the processing steps executed by the processor 11.
The first storage unit 14 stores information for extracting necessary trace data from the trace data stored in the trace memory 13, and the first storage unit 14 extracts information based on the information stored in the first storage unit 14. A pair of a second storage unit 15 for storing trace data and a first storage unit 16 for storing information for extracting necessary trace data from the trace data stored in the trace memory 13; This first storage means 1
6 and a second storage means 17 for storing the trace data extracted based on the information stored by the information storage unit 6. Further, from among the trace data stored in the trace memory 13,
A first storage unit 18 for storing information for extracting necessary trace data, and a second storage unit 19 for storing trace data extracted based on information stored in the first storage unit 18 are paired. Are provided as plural pairs.

The trace data extracted from the trace data stored in the trace memory 13 based on the information stored in the first storage means 14 is stored in the second storage means 15 as a pair. The trace data extracted based on the information stored in the first storage unit 18 is stored in the paired second storage unit 17 with the trace data extracted based on the information stored in the first storage unit 18. In the second storage means 19 to be stored separately.

[0019]

With the above arrangement, important trace data can be extracted from the trace memory 13 and stored in the second storage means 15, 17, 19.
The data is not erased by writing the trace data to the trace memory 13.

Therefore, only the necessary trace data can be left among the trace data stored in the trace memory 13.

[0021]

FIG. 2 is a block diagram of a circuit showing an embodiment of the present invention, and FIGS. 3 to 5 are diagrams for explaining the operation of FIG.

In FIG. 2, the same reference numerals as those in FIG. The processor 11 operates by reading the program stored in the control storage 21 and sequentially stores the trace data in the trace memory 13 as described with reference to FIG.

The trace data is composed of, for example, 4-byte data as shown in the trace memory 13 of FIG.
000 is 110A hexadecimal in the second address area
1011 is the hexadecimal number 120C0 in the third address.
001 is the hexadecimal 130A in the fourth address area
0100 is the hexadecimal number 140D1 at the fifth address
110 has been written.

The addresses of the channels 1 to 4 are stored in the second byte of the trace data. That is, the address of channel 1 is hexadecimal 0A, the address of channel 2 is hexadecimal 0B, the address of channel 3 is hexadecimal 0C, and the address of channel 4 is hexadecimal 0D.

When no error occurs, the initial value hexadecimal number FF is stored in the register 22 and the extended trace memory 23 in the initial state as shown in the register 22 and the extended trace memory 23 of FIG. Have been.

The processor 11 reads the data of the register 22 every time the trace data is written to the trace memory 13. If the register 22 is in the initial state, the processor 11 writes the trace data to the extended trace memory 23. Absent.

Here, for example, if an error occurs when data is being transferred between the channel 1 and the disk device 6, the processor 11, which has been notified of the occurrence of the error by the data transfer control circuit 9, Due to the occurrence of an error during access from the channel 1, the address 0A of the channel 1 is written into the register 22 as shown in the register 22 of FIG.

As described above, each time the trace data is written to the trace memory 13, the processor 11
When the address 0A of channel 1 is stored in the register 22 and the trace data whose second byte address is 0A is extracted from the trace data stored in the trace memory 13, The extracted trace data is written into the extended trace memory 23.

That is, as shown in the extended trace memory 23 of FIG. 4, the trace data 110A1011 and 130A0100 stored in the second address area and the fourth address area of the trace memory 13 are written in the extended trace memory 23. Put in.

The processor 11 has an extended trace memory 23
When the writing of the trace data to is completed, an error is reported to the channel 1, and the initial value FF is stored in the register 22 to return to the initial state as shown in the register 22 of FIG.

The channel 1 that has reported the error reports an error to the central processing unit. When the central processing unit instructs the retry of the command, the channel 1 sends a command to the processor 11 again and requests a retry.

The processor 11 executes the requested retry, and writes the trace data to the trace memory 13 each time as described with reference to FIG. The processor 11 operates by access from the channel 2 or 3 or 4, and
The trace data is sequentially written into the trace memory 13. When the trace data is written to the last address of the trace memory 13, the trace data is written from the start address.

Therefore, as shown in the trace memory 13 of FIG. 5, the head address area of the trace memory 13 is rewritten, for example, as 220B1001, and the second address area is rewritten as 230C1100. Therefore, the trace data of channel 1 at the time of occurrence of the error, 110A10
11 disappears, but as shown in the extended trace memory 23 of FIG.
3 is left.

FIG. 6 is a flowchart for explaining the operation of FIG. The processor 11 creates trace data in step (1), and writes the trace data created in step (2) into the trace memory 13.

Then, the processor 11 proceeds to step (3)
In step (4), it is checked whether an error has occurred. If no error has occurred, the process proceeds to step (4), and the register 22 is checked whether it is an initial value.

If the register 22 has the initial value, the step
Returning to the processing of (1), if the register 22 is not the initial value,
In step (5), the initial value is stored in the register 22, and the process returns to step (1).

If an error has occurred in step (3), the processor 11 checks in step (6) whether the register 22 has an initial value.
Write the address of the channel being accessed to
In (8), when the trace data corresponding to the channel indicated by the address of the register 22 is extracted from the trace memory 13 and written in the extended trace memory 23, the process returns to the step (1).

If the register 22 is not the initial value in step (6), the processor 11 proceeds to the processing in step (9), and stores the trace data corresponding to the channel indicated by the address of the register 22 in the extended trace memory 23. Is extracted from the trace memory 13 and written, the process returns to the step (1).

FIG. 7 is a block diagram of a circuit showing another embodiment of the present invention. FIG. 7 shows a plurality of registers 22 and 24.
And a plurality of extended trace memories 23 and 25. For example, by storing the address of channel 1 in the register 22 and the address of channel 3 in the register 24, The trace data related to channel 1 can be extracted and written, and the trace data related to channel 3 can be extracted and written to the extended trace memory 25.

In this way, a plurality of types of important trace data can be stored in correspondence with the number of pairs of registers and extended trace memories.

[0041]

As described above, according to the present invention, since important trace data can be extracted from the trace memory and saved in the extended trace memory, the trace data can be written beyond the capacity of the trace memory. Will not be erased by being overwritten.

Accordingly, necessary trace data can be left among the trace data stored in the trace memory.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram of a circuit showing an embodiment of the present invention.

FIG. 3 is a view for explaining the operation of FIG. 2 (part 1)

FIG. 4 is a view for explaining the operation of FIG. 2 (part 2);

FIG. 5 is a view for explaining the operation of FIG. 2 (part 3);

FIG. 6 is a flowchart for explaining the operation of FIG. 2;

FIG. 7 is a block diagram of a circuit showing another embodiment of the present invention.

FIG. 8 is a block diagram illustrating an example of a conventional technique.

[Explanation of symbols]

 1 to 4 channels 5, 20 disk control device 6, 7 disk device 8, 10 interface circuit 9 data transfer control circuit 11 processor 12, 21 control storage 13 trace memory 14, 16, 18 first storage means 15, 17, 19 Second storage means 22, 24 Register 23, 25 Extended trace memory

Claims (2)

(57) [Claims] 1. An input / output control device comprising a trace memory (13) for storing trace data indicating a process executed by a processor (11), wherein the trace data stored in the trace memory (13) is A first storage means (14) for storing information for extracting necessary trace data, and a second storage means for storing the trace data extracted based on the information stored in the first storage means (14). Storage means (15), and trace data extracted from the trace data stored in the trace memory (13) based on the information stored in the first storage means (14). An input / output control device, wherein the input / output control device is stored in a second storage means (15). 2. An input / output control device provided with a trace memory (13) for storing trace data indicating a process executed by a processor (11), wherein the trace data stored in the trace memory (13) is included. The first storage means (14), (16), (18) for storing information for extracting necessary trace data, and the information stored in the first storage means (14), (16), (18). Second storage means for storing the trace data extracted based on the data
(15) (17) (19), and a plurality of pairs are provided as pairs, respectively, and the trace memory (13)
Out of the trace data stored in the first storage means (14), (16), and (18) based on different information stored in the first storage means (14), (16), and
(15) An input / output control device characterized in that the input / output control device is configured to store the information separately in (17) and (19).