JP2734148B2 - Tone control parameter supply device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial applications]

The present invention relates to a musical tone control parameter supply device provided before a musical tone signal forming means such as an electronic musical instrument and supplying desired control parameters to a plurality of operation channels in the musical tone signal forming means.

[Prior art]

Conventionally, this type of apparatus has a parameter storage means comprising a plurality of storage channels corresponding to a plurality of operation channels of the tone signal forming means, and forms a tone signal input in response to an operation of an operator such as a keyboard or a tone. Is stored in a designated storage channel among a plurality of storage channels of the parameter storage means, and the stored control parameters are supplied to an operation channel corresponding to the storage channel.

[Problems to be solved by the invention]

However, in the above-mentioned conventional apparatus, the control parameters used in each operation channel of the tone signal forming means are stored in each storage channel of the parameter storage means corresponding to each operation channel. Each had to be written. On the other hand, the control parameters used in each operation channel of the musical tone signal forming means may be different, but the same control parameters are often used in different operation channels. For example, when the tone signal forming means synthesizes a tone signal by a tone synthesis method using modulation such as FM modulation, a frequency number FN as a control parameter for pitch control of a carrier and a pitch number for pitch control of a modulator are used. Frequency number as control parameter
In many cases, the same value as FN is used, and this control parameter often needs to be changed over time for one musical tone. In such a case, according to the conventional device,
It is necessary to write control parameters of the same value to a plurality of storage channels of the parameter storage means, and it is necessary to perform the writing repeatedly for one sound as time passes. It takes a long time, and delays in the process of generating tone signals for the operation of controls such as keyboards and tones.
There is a problem that the processing speed of the entire system is delayed due to the delay of this processing due to other processing. The present invention has been made to address the above problems,
It is an object of the present invention to provide a musical tone control parameter supply apparatus that simplifies writing of control parameters into parameter storage means, thereby increasing the processing speed of the entire system including musical tone signal generation processing.

[Means for Solving the Problems]

In order to achieve the above object, the structural feature of the invention according to claim 1 enables one musical tone signal to be formed using a plurality of operation channels and a plurality of musical tone signals to be simultaneously formed. A musical tone control parameter supply device for supplying a musical signal forming means with control parameters used for computation in each computation channel, comprising a plurality of storage channels respectively corresponding to each computation channel of the musical tone signal forming means. A parameter storage unit capable of storing the control parameter in each storage channel, and a plurality of flags set for each tone signal formed by the tone signal forming unit, wherein one flag is generated. One of a plurality of storage channels respectively corresponding to a plurality of operation channels used for performing The stored control parameters are used in common for the same plurality of operation channels, or each control stored in a plurality of storage channels respectively corresponding to the plurality of operation channels used to generate one musical tone signal. A flag storage means capable of storing a flag indicating whether the parameter is independently used in each of the plurality of operation channels, and a tone signal,
Writing the control parameters into the storage channels of the parameter storage means and writing the flags into the flag storage means in response to the writing of the control parameters; When the flag corresponding to one musical tone signal indicates the common use of the control parameter, any one of the plurality of storage channels respectively corresponding to the plurality of arithmetic channels used to generate the same musical tone signal. The control parameter stored in the one storage channel is output to each of the plurality of operation channels, and the flag corresponding to one tone signal generated and stored in the flag storage means is output to each of the plurality of operation channels. When expressing the independent use of control parameters, Each control parameters stored in the plurality of storage channels corresponding to the plurality of operation channels used to generate a signal, in that an output means for outputting each of the plurality of operation channels. In the invention according to claim 2, the parameter storage means is constituted by a plurality of stages of first circulating shift registers operating in synchronization with an operation channel of the tone signal forming means,
The flag storage means is composed of a plurality of second cyclic shift registers operating in synchronization with the first cyclic shift register, and the output means is provided from a plurality of different stages of the first cyclic shift register. The present invention is configured by a selector which selectively outputs a control parameter according to a flag from the second cyclic shift register.

Actions and effects of the present invention

In the invention according to claim 1 (or claim 2) configured as described above, the writing means controls the storage channel of the parameter storage means (or the first cyclic shift register) to generate a tone signal. When the parameter is written and the flag is written in the flag storage means (or the second cyclic shift register) in response to the writing of the control parameter, the output means (or the selector) responds to the flag stored in the flag storage means. Then, the control parameters stored in the storage channel of the parameter storage means are output to the tone signal forming means. In this case, the flag stored in the flag storage means and corresponding to each tone signal indicates that one control parameter is commonly used for a plurality of calculation channels for generating one tone signal. For example, the control parameters stored in any one of the plurality of storage channels corresponding to the plurality of operation channels,
Output to each of the plurality of operation channels. On the other hand, if the flag indicates that a plurality of control parameters are used independently for a plurality of operation channels for generating one tone signal, a plurality of storages respectively corresponding to the plurality of operation channels are provided. Each control parameter stored in each channel is output to each of the plurality of operation channels. Therefore, as for the control parameters commonly used in a plurality of calculation channels used to generate one musical tone signal, only one write operation to the parameter storage means is performed, and the control parameters are stored in the plurality of calculation channels. Since the signals are supplied to the channels, the process of writing the control parameters commonly used by a plurality of calculation channels for generating one tone signal is simplified. The flag is simple data indicating whether the control parameter is used in common by a plurality of operation channels for generating one tone signal or used independently. Since the processing can be performed simultaneously on the parameters and the processing is not complicated, according to the inventions according to the first and second aspects, the processing for writing the control parameters is simplified, and the system including the processing for generating the tone signal is also included. The overall processing speed is increased. Further, depending on the setting of the flag, the control parameters can be independently used for a plurality of calculation channels for generating one tone signal. As a result, in this case, since the calculations performed on a plurality of calculation channels for forming one musical tone signal are performed using the child control parameters, one musical tone signal uses many control parameters. Formed. Further, since the setting of the flag can be performed for each tone signal, the control parameters for a certain tone signal can be used in common for a plurality of calculation channels for generating one tone signal, or for other tone signals. For, the control parameters can be independently used for a plurality of calculation channels for generating one tone signal. As a result, the control parameters can be used appropriately and effectively for each tone signal generated for each key press.

【Example】

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 shows a musical tone control parameter supply device according to the embodiment.
An applied electronic musical instrument is shown in a block diagram. This electronic musical instrument has a keyboard 10 consisting of multiple keys and tone selection.
An operator group 11 including various operators such as operators is provided.
The keyboard 10 and the operator group 11 are a microcomputer (hereinafter, referred to as a microcomputer).
Connected to 12)
12 detects the operation state of the keyboard 10 and the operator group 11, and performs the detection.
Various data necessary for the tone signal and the
Address signal and chip for controlling the capture to the destination
Control signals such as select signals and write command signals.
Output to interface 13, register unit 14 and control unit 15
I do. Each of these circuits 13 to 15 is a control parameter of the present invention.
It corresponds to the supply device, and the supply device
Control parameters necessary for forming the tone signal
The meter is supplied to the tone signal forming unit 16. A plurality of musical tone signal forming units 16 capable of simultaneous sound generation (for example,
In this embodiment, 14) sound channels are provided.
Each channel operates in a time-sharing manner and responds to the control parameters.
A modified tone signal is formed and output. In this embodiment,
Means that each of the sounding channels operates in a time-division manner.
Consists of two operation channels, and these two operation channels
The channel is the carrier and modulator in the FM synthesis method.
This is to execute the calculation for. This tone signal formation
The output of the unit 16 is connected to the D / A converter 17 and the converter 1
7 converts the input digital tone signal to an analog tone signal
The signal is converted and supplied to the sound system 18. Sound system
The system 18 comprises an amplifier, a speaker, etc.
The log tone signal is converted to an acoustic signal and emitted. In addition,
At least the register unit 14, the control unit 15, and the tone signal formation
The unit 16 is supplied with a system clock φ, and each circuit
The units 14 to 16 operate synchronously. FIG. 2 shows the interface 13, the register unit 14 and
This shows the specific configuration of the control unit 15, and
13 has a capture control circuit 21 which constitutes a part thereof.
I have. The capture control circuit 21 writes the chip select signal.
Pulse signal of short width
Output a sound source write signal WTG consisting of
Supplied at the same time as or slightly behind the signal, and
Address that is supplied for a slightly longer time than the
Signal A ₀ ~ A _Three And data signal D ₀ ~ D ₇ Is output as is.
The sound source write signal WTG is supplied to the latch signal generator 22.
You. The latch signal generator 22 is an OR circuit OR1 and switches the input signal.
Delay time for outputting by delaying 2 bits of stem clock φ
Path DL1, the inverter circuit INV1, and the AND circuit AND1.
Pulse-like sound source write signal WTG at least
Extending the pulse width to 2 bits of system clock φ
First, the same two bits are delayed, and AND
It is supplied to one input of each of the circuits AND2 to AND4. Address signal A ₀ ~ A _Three Is supplied to the decoder 23,
The decoder 23 receives the address signal A ₀ ~ A _Three The decoder
And AND circuit AND2 as latch select signals LS0-LS2.
To the other input of AND4. Data signal
D ₀ ~ D ₇ Is a latch circuit 24 for control parameters, channels
Latch circuit 25 for specifying and latch circuit for specifying the register
26, and each latch 24-26 is connected to an AND circuit AND2.
~ Data is received by the arrival of each high-level signal “1” from AND4
Signal D ₀ ~ D ₇ Are respectively latched. In this example,
Only a part of the register unit 14 and the control unit 15 is shown.
Therefore, in FIG.
Signals LS3, LS4 ... and AND circuit A corresponding to these signals
ND4 and other AND circuits similar to latch circuit 26
And a latch circuit are omitted. These latch signal generator 22, decoder 23 and latch
The circuits 24-26 constitute the control unit 15 (see FIG. 1).
Therefore, the control unit 15 further compares the channel counter 27,
Unit 28, register write signal generator 31 and decoder 32
Have. The details of the channel counter 27 are shown in FIG.
That is, the counters 27a and 27b are provided. Counter 27a is
3-bit counter driven by stem clock φ
And its output end has a channel count value CH
Outputs lower three bits CHC0 to CHC2 of C0 to CHC5.
Therefore, a high-level signal “1” is applied to the carry input end Ti.
It is always supplied and its reset input terminal is
The signal from the gate circuit AND5 is supplied. AND circuit AN
D5 outputs the channel count value CHC0 to the inverter circuit INV2.
From the value inverted and the channel count value CHC1 and CHC2
And outputs the logical product of the three signals. Counter 27
b is a 2-bit clock driven by the system clock φ.
And a channel counter at its output.
Output the upper 2 bits CHC3 and CHC4 of the default values CHC0 to CHC5
The carry input terminal Ti has an AND circuit AND5
Is supplied. This allows the channel cow
The count values CHC0 to CHC4 correspond to the 28 arithmetic channels of the tone signal forming unit.
"0" to "6", "8" to "14",
Changes repeatedly from "16" to "22" and "24" to "30"
I do. Note that the count values “7”, “15”, “23”, “3”
The reason for excluding `` 1 '' is because of the convenience of the circuit configuration.
It is a title. Also, from this channel counter 27, the channel
The count value CHC3 is output as the timing signal TM7
Exclusive OR circuit EXOR1
The exclusive OR output of channel count values CHC3 and CHC4 is
It is output as an imaging signal TM7 *. This allows
The imaging signal TM7 has the channel count value “0”.
~ "6", low level at "16"-"22" timing
"0" and the channel count value "8" to
High level "1" at the timing of "14", "24" to "30"
Becomes The timing signal TM7 * is
At the timing of the event values "0" to "6" and "24" to "30"
Low level “0” and the channel count value
High level at the timing of “8” to “14” and “16” to “22”
The bell becomes "1". The comparator 28 is connected to the latch circuit 25 and the channel counter 27.
Connected, the memory contents of the latch circuit 25 and the channel counter
At the time of coincidence with the data values CHC0 to CHC4, a match signal EQ is output. The details of the register write signal generator 31 are shown in FIG.
As shown in FIG.
Roads NOR1 and NOR2 are provided. One input of NOR circuit NOR1
(Corresponding to the set terminal S of the flip-flop circuit)
The output of the AND circuit AND6 is connected.
D6 is the latch signal WL from the latch signal generator 22 and the decoder
Input the latch select signal LS0 from 23 and both signals WL,
Outputs the logical product of LS0. Output of NOR circuit NOR1 (flicker)
Is equivalent to the inverted output terminal of the flip-flop circuit)
Supplied to one input of AND circuit AND7 via circuit INV3.
The match signal EQ is supplied to the other input of the same circuit AND7
And the logical product is used as the register write signal WR.
Output. Further, the register write signal WR is
Delay input signal by 2 bits of system clock φ
Via the extension circuit DL2, one input (free) of the NOR circuit NOR2
(Equivalent to the reset terminal R of the flip-flop circuit)
You. The decoder 32 is connected to the output of the latch circuit 26,
Decoder data for register specification stored in 26
And AND circuit AND8, AND9, AND10 ...
Supply. Each of these AND circuits AND8, AND9, AND10…
The other input is supplied with the register write signal WR.
AND8, AND9, AND10 ... is the logical product of both inputs.
Output each. Further, the control unit 15 controls the 14 tone patterns of the tone signal forming unit 16.
Cycling 14 channel flags corresponding to the generated channel
Shift registers 33 and 34 for storing are provided. This tea
The channel flag is key-on data as a control parameter
Consists of 2 bits corresponding to KON and frequency number FN
Each bit is set to a low level “0”, and each control parameter is set.
Data using only one calculation channel of the tone signal forming unit 16
Use, respectively, and according to the high level “1”.
Indicates that it is used in multiple computation channels.
You. In the present embodiment, the control parameter
Is commonly used in a plurality of operation channels, 0-
8,1-9 ... 6-14,6-24,17-25 ... 22-30
Each of these computation channels is restricted to a computation channel pair.
Channel pairs form 14 musical tone forming channels
ing. These shift registers 33 and 34 are both system clocks.
2-bit 7-stage cash register shifted by φ
The input / output terminals of the registers 33 and 34 have selectors.
Are connected. The selector 35 is a latch circuit
Data line D, the output of 24 ₆ , D ₇ Channel from
Lag CHF1 and CHF2 and the seventh stage of shift register 34 (most
Channel flags CHF1 and CHF2 from the last stage)
Input from the AND circuit AND11 to the control input terminal.
When the select control signal is high level “1”, the data line
D ₆ , D ₇ Input to the first stage of shift register 33
When the selection control signal is low level “0”
The input from the shift register 34 is
Supply to one stage. AND circuit AND11 has both inputs
Inverts the output of AND circuit AND8 and timing signal TM7 *
The signal inverted by the data circuit INV4 is supplied.
The AND circuit AND11 outputs a logical product of the two inputs. The selector 36 is connected to the data line D ₆ , D ₇ Channel from
7 of CHF1 and CHF2 and shift register 33
Channel flags CHF1 and CHF2 from (final stage)
Is supplied to the control input terminal from the AND circuit AND12.
When the selection control signal is high level “1”, the data
D ₆ , D ₇ The first stage of shift register 34
And when the selection control signal is at low level “0”
The input from the shift register 33 is
Supply to the first stage. For both inputs of AND circuit AND12
Is supplied with AND circuit AND8 output and timing signal TM7 *
The AND circuit AND11 calculates the logical product of the two inputs.
Is output. Selector 37 is the seventh stage of each of shift registers 33 and 34
Each channel flag CHF1, CHF2 from (final stage)
And the selection control signal supplied to its control input
When the timing signal TM7 * is high level “1”.
Output from the shift register 33, and
The signal from the shift register 34 when the signal is low level “0”.
Output the input. Register unit 14 shift-controlled by system clock φ
The shift registers 41 to 45 are provided. The shift registers 41 and 42 are connected in series and
The shift data 41 is stored cyclically in the shift register 41.
Is composed of a 1-bit 21-stage register group.
The shift register 42 is a 1-bit 7-stage register
Each register is provided in the tone signal forming unit 16.
It corresponds to each of the 28 computation channels. shift
The input end of the register 41 and the output end of the shift register 42
Selectors 46 and 47 are connected respectively. Selector 46
Is the data line D which is the output of the latch circuit 24. ₀ Key from
ON data KON and the seventh stage of shift register 42
Enter the key-on data KON from the last stage)
Control signal supplied from the AND circuit AND8 to the control input terminal
Is high level “1” when the data line D ₀ Input from
Is supplied to the first stage of the shift register 41 and selected.
When the select control signal is low level “0”, the shift register
Input from 42 is supplied to the first stage of shift register 41
I do. Selector 27 is the 21st stage of shift register 41 (final
Stage) and the seventh stage of the shift register 42 (final)
Enter each key-on data KON from the stage) and
Control signal supplied to the control input terminal from the gate circuit AND13
Is high level “1”.
Output and the selection control signal is low level “0”.
The input from the shift register 42 is output. and
The channel inputs from the selector 37 are connected to both inputs of the circuit AND13.
The lag CHF1 and the timing signal TM7 are output from the inverter circuit INV5.
The inverted signal is supplied to the AND circuit AND13.
Outputs the logical product of both inputs. Shift registers 43 and 44 are connected in series and
The upper 8 bits of the number FN are stored in a circular manner.
Register 43 is composed of an 8-bit 21-stage register group.
And the shift register 44 has 7 stages of 8 bits
Each register is a tone signal.
It corresponds to each of the 28 calculation channels of the forming unit 16.
You. The input terminals of these shift registers 43 and the shift registers
Selectors 48 and 51 are connected to the output terminal of the star 44, respectively.
ing. The selector 48 outputs the data which is the output of the line circuit 24.
Line D ₀ ~ D ₇ Frequency number from FN and shift register 44
Frequency number FN from the 7th stage (final stage)
Is supplied to the control input terminal from the AND circuit AND9.
When the selection control signal is high level “1”, the data
D ₀ ~ D ₇ The first stage of shift register 43
And when the selection control signal is at low level “0”
The input from the shift register 44 is
Supply to the first stage. The selector 51 selects the 21st stage of the shift register 43 (final
Stage) and the seventh stage of shift register 44 (final)
Enter each frequency number FN from the stage) and AND times
The selection control signal supplied to the control input terminal from the
When the level is “1”, the input from the shift register 43 is
Output when the selection control signal is low level “0”
The input from the shift register 44 is output. AND circuit
Channel flag C from selector 37 is applied to both inputs of AND14
HF2 and timing signal TM7 are inverted by inverter circuit INV6.
And the AND circuit AND14
Outputs the logical product of both inputs. Also, AND circuit AND14
The output is from the shift registers 43 and 44 and the selectors 48 and 51.
Lower than the frequency number FNO configured in the same way
It is supplied to a bit circuit. The shift register 45 controls, for example, an envelope.
The parameters are stored in a circular manner.
8 bits and 28 bits corresponding to each of the 28 computation channels
It consists of a group of registers. Register 45
A selector 52 is connected to the input end, and the selector 52
Is the data line D which is the output of the line circuit 24 ₀ ~ D ₇ from
28th stage of the control parameter and shift register 45
(Control parameters from the last stage)
Control signal supplied to the control input terminal from the
When the signal is high level "1", the data line D ₀ ~ D ₇ From
Is supplied to the first stage of the shift register 45,
When the selection control signal is low level “0”, the shift
Input from the register 45 to the first stage of the shift register 45
To supply. In this embodiment, the control parameter system is used.
Only three types of shift registers are shown, but a tone signal is formed.
The control parameters for the
Even control parameters related to attack level
Data and rate data, level data for decay and
And rate data, as well as other volume level data.
There are also control parameters such as data and data for adding effects.
Regarding shift registers for these control parameters
Are omitted in FIG. In such cases, multiple
Control parameters commonly used in computation channels
Shift registers 41, 42, 43, 4
It is divided into 2 groups as shown in 4 and other
For registers related to the control parameters of
It has a single configuration like the register 45. Next, the operation of the embodiment configured as described above will be described. When the keyboard 10 and the operator group 11 are operated, the microcomputer 12
Control parameters necessary for forming a tone signal in accordance with the above operation
Control that represents the calculation channel of the tone signal formation unit 16
Register unit 14 via interface 13 together with data
And to the control unit 15. Thereby, the register unit 14
Capture and store control parameters in the computation channel
The acquired control parameter is used for the calculation channel.
Supplied to the tone signal forming section 16 in synchronization with the
You. In the tone signal forming section 16, the control parameter
Are two sets of operation channels for the carrier and modulator.
The calculation results of the two sets of calculation channels
The tone signal formation operation is executed by the FM synthesis method used.
It is. The digital tone signal obtained in this way is D / A converted.
Output to an analog tone signal.
It is converted and supplied to the sound system 18, which
It is pronounced as a musical tone from 18. For these series of operations, frequency number FN and key
-ON data KON and two operation channels of the tone signal forming unit 16
A detailed example is given with a specific example of common use in channels.
More specifically, the microcomputer 12 is operated by pressing a key on the keyboard 10.
Of the program started from step ST0 in FIG.
In step ST1, the key code representing the pressed key is
Data KCD, and set a table in step ST2.
The frequency according to the data KCD is referred to
Deriving the number FN. Next, the microcomputer 12 performs step ST
At 3, the 14 tone signal forming channels of the tone signal forming section 16
Assigned channel ASCH of the pressed key from the channel
Is determined, and in steps ST4 and ST5, the assigned channel ASCH
Write by executing the following operations (1) to (3) based on
Calculate the channel WCH. a = INT (ASCH / 7) ... (1) b = MOD (ASCH / 7) ... (2) WCH = 16.a + b ... (3) In such an operation, the operator INT is the integer value in parentheses.
Extract a few parts, and the operator MOD
Indicates the remainder of division. As a result, "0" to "13"
The assigned channel ASCH to be represented is “0” to
Write channel WC consisting of "6", "16" to "22"
Converted to H. Next, in step ST6, the microcomputer 12
, The first control parameter is transmitted.
Data to the write channel WCH. Write the data representing the write channel WCH to the data bus.
Output to the interface 13 through the interface. At the same time,
Address indicating the latch select signal LS1 via the control line
Data A ₀ ~ A _Three , Chip select signal and write command signal
Output to the interface 13. The data representing register 45 is interfaced via the data bus.
Output to the interface 13. At the same time, via the control line
Address data A representing the latch select signal LS2 ₀ ~
A _Three , Chip select signal and write command signal
Output to the face 13. The first control parameter is transferred via the data bus.
Output to face 13. At the same time, via the control line
Address data A representing the latch select signal LS0. ₀ ~ A
_Three , Chip select signal and write command signal
Output to the face 13. This allows the capture control circuit in the interface 13
Path 21, latch signal generator 22, decoder 23 and AND circuit
AND2 to AND4 are activated, and the latch circuits 24-26
Displays the first control parameter and the write channel WCH
Control data representing the register 45
Written. On the other hand, the channel counter 27 always
The count value has been increased, and the same count value and write
Each time the channel WCH matches, the match signal EQ is compared
Output from the device 28 to the register write signal generator 31.
Swell. In the register write signal generator 31,
The output of the latch signal WL and the latch selector signal LS0
The flip-flop consisting of NOR circuits NOR1 and NOR2 at the time of power
Since the signal is set, generation of the coincidence signal EQ after the setting
Sometimes, a register write signal WR is output. Also this
At this time, the decoder 32 is turned off based on the output of the latch circuit 26.
Outputs high-level "1" signal to one input of gate circuit AND10
And the AND circuit AND10 operates when the coincidence signal EQ is generated.
Supplies a high-level "1" signal to the control input terminal of the selector 52
The first control stored in the latch circuit 24.
Parameters are input to the shift register 45 via the selector 52.
Is forced. Thereafter, in the register write signal generator 31,
The register write signal WR via the delay circuit DL2
A flip-flop consisting of circuits NOR1 and NOR2 is reset
Is done. As a result, the AND circuit AND10 is always at a low level.
Output a “0” signal, and the selector 52 shifts
Output of the 28th stage (final stage) of register 45 is
Since it will be supplied to the first stage of the register 45,
The first control parameter is set to the write channel WCH
The data is cyclically stored in the corresponding time division channel. And
This first control parameter is used by the tone signal forming section 16
In synchronization with the computation channel corresponding to channel WCH,
It is output every 28 cycles of the system clock φ. Returning to the explanation of the program again, the microcomputer 12
In step ST7, write the second control parameter.
The data is transmitted to the channel WCH + 8 according to the above procedures. Take
In this case, the second control parameter is provided in the latch circuits 24-26.
Data and data representing the write channel WCH + 8,
The control data representing the register 45 is written respectively.
Therefore, the second control parameter is stored in the shift register 45.
Is a time division channel corresponding to the write channel WCH + 8
It is stored cyclically in the flannel. Then, the second control parameter
The meter is connected to the channel WCH + 8 of the tone signal forming section 16.
The system clock is synchronized with the computation channel corresponding to
It is output every 28 cycles of φ. Next, the microcomputer 12 described above in step ST8.
By performing data transmission in the same manner as
Output frequency number FN to write channel WCH + 8
You. However, in such a case, the microcomputer 12
Number number FN, data representing write channel WCH + 8
And data representing registers 43 and 44 are output.
Each of the above data is written in the switch circuits 24-26.
You. This frequency number FN is
27, comparator 28, register write signal generator 31,
By the action of the loader 32, the AND circuit AND9 and the selector 48,
Corresponding to the channel WCH + 8 of the shift registers 43 and 44
Written to the time-shared channel
It is circulated and stored in 3,44. After the processing in step ST8, the microcomputer 12 proceeds to step ST9.
In the same way, the data transmission
By doing, key-on data KON and simultaneous frequency
Channel for writing flag and simultaneous key-on flag
Output to WCH + 8, and a series of program
The program processing ends. However, in such a case,
From bit 12, bit 0 (least significant bit) as shown in FIG.
Eye) D ₀ Key-on data KON, 6th bit D ₆ To
The simultaneous frequency number flag and the seventh bit (the most significant bit).
G) D ₇ 8-bit data with simultaneous key-on flag
Data, data representing the write channel WCH + 8,
The data representing the masters 41 and 42 is output, and the latch circuit 24
Each of the above data is written in. Soshi
As for the key-on data KON,
Counter 27, comparator 28, register write signal generator 31,
The operation of the decoder 32, the AND circuit AND8, and the selector 46
As described above, the channels of the shift registers 41 and 42 are
Write to time division channel corresponding to channel WCH + 8
Then, the data is circularly stored in the shift registers 41 and 42. On the other hand, the simultaneous frequency number flag and simultaneous key-on
Flags circulate in shift registers 33 and 34 as follows
It is memorized. As described in step ST5 above,
Assigned channel ASCH representing "0" to "13" (14 music channels)
(Corresponding to the sound signal formation channel) in this order from “0” to
Write channel WC consisting of "6", "16" to "22"
Since it is converted to H, the write channel WCH + 8
Represent any of “8” to “14” and “24” to “30”
Channel counter 27, comparator 28, register writing
Operation of only signal generator 31, decoder 32 and AND circuit AND8
Thus, one input of each of the AND circuits AND11 and AND12 is
Channel ties of “8” to “14” and “24” to “30”
High level signal “1” is supplied only during
You. The other input of the AND circuit AND11 has a time
Signal TM7 * is inverted by the interface circuit INV4
Channel timing of "0" to "6", "24" to "30"
The signal which becomes high level “1” is supplied,
The other input of the AND circuit AND12 includes “8” to “14”,
High level with "16" to "22" channel timing
A signal that becomes “1” is supplied. This allows writing
If only the channel WCH + 8 is “8” to “14”,
The simultaneous frequency number flag and simultaneous key-on flag
During the seven system clock φ transitions from the state shown in
To the shift register 34 via the
Write as "R flag" to "6-14 channel flag"
7C in the state of channel timing 16.
And during the next 7 system clock φ
Thus, each channel flag in the shift register 34 is
The data is fed back to the shift register 33 via the collector 35. Ma
Also, the write channel WCH + 8 is “24” to “30”.
The simultaneous frequency number flag and simultaneous key on
The lag is equivalent to 7 system clocks φ from the state shown in Fig. 7D.
During the period, "16-2
4 channel flag ”to“ 22-30 channel flag ”
In the channel timing 0 state.
7A and the next system clock φ
Each channel in the shift register 33 between seven
Flag is output to system register 34 via selector 36
Is done. Then, a new simultaneous frequency number is
Unless the flag and simultaneous key-on flag are supplied,
The data in the shift registers 33 and 34 is the system clock φ.
Is stored in synchronization with the
Each channel flag is stored in shift registers 41 and 42 and shift
"0-8", "1-9" in registers 43 and 44 ... "6-1
4 ”,“ 16-24 ”,“ 17-25 ”… a pair of“ 22-30 ”
Channel timings
You. Thus, each channel is stored in the shift registers 33 and 34.
The channel flag is stored cyclically, but the control input of the selector 37 is
At the end, "0" to "6", "24" to "30" channels
It becomes low level “0” at the timing and “8” to “1”.
4 ”,“ 16 ”to“ 22 ”
The timing signal TM7 * that becomes the bell "1" is supplied.
Therefore, as shown in FIGS. 7A and 7B, “0” to
In the channel timing of "6", "8" to "14"
"0-8 channel flag"-"6-14 channel flag"
Is output redundantly, and "16" to "22", "24"
~ With the channel timing of “30”, “16-24 channels”
Flag to 22-30 channel flag overlap
Is forced. In such a case, the output channel flag is
The simultaneous key-on flag and the simultaneous frequency number flag
Both flags are channel flags CHF1 and CHF2, respectively.
Then, it is supplied to one input of each of AND circuits AND13 and AND14. The other inputs of AND circuits AND13 and 14 are connected to the timing signal.
"0"-which is obtained by inverting signal TM7 with inverter circuits INV5,6
Only at channel timing of "6", "16" to "22"
Since a high level “1” signal is supplied,
Keys 47 and 51 are key-on data K in shift registers 41 to 44.
Selectively output ON and frequency number FN as follows.
You. For channel timings "0" to "6", see FIG.
As shown in the figure, the channel flags CHF1 and CHF2 are high.
If the level is “1”, the calculation channels of “8” to “14”
When the data KON and FN are output respectively,
In addition, the channel flags CHF1 and CHF2 are low level.
If it is “0”, the calculation channels for “0” to “6” are
The data KON and FN are output, respectively. For channel timings “8” to “11”, see FIG.
As shown in the figure, the channel flags CHF1 and CHF2 are not
In relation to the above, regarding the calculation channels of “8” to “14”,
Each data KON, FN is output respectively. For channel timings "16" to "22", see Figure 8C
As shown in the figure, the channel flags CHF1 and CHF2 are high.
If the level is “1”, the calculation channels of “24” to “30”
When the data KON and FN are output respectively,
In addition, the channel flags CHF1 and CHF2 are low level.
If “0”, the calculation channels for “16” to “22” are
The data KON and FN are output, respectively. For channel timings “24” to “30”, see Figure 8D
As shown in the figure, the channel flags CHF1 and CHF2 are not
In relation to the above, regarding the computation channels of “24” to “30”,
Each data KON, FN is output respectively. And the key-on data KO output in this way
N and the frequency number FN are the same as those of the shift register 45 described above.
Along with the first and second control parameters,
Example of forming a tone signal on a predetermined calculation channel of the forming unit 16
For example, calculation of carrier and modulator in FM synthesis method
Used for As can be understood from the above operation description,
According to the simultaneous key-on flag and the simultaneous frequency number flag,
By outputting the data and storing it in registers 33 and 34,
Key-on data, K0N and frequency number FN only once
Just send and write to shift registers 41-44,
Each written data KON, FN is used by two operation channels.
The same control parameter is used for multiple operation channels.
Transmission of control parameters when using
The writing process is simplified. Especially for one tone,
Change the control parameter (frequency number FN) over time
Channel flag (simultaneous frequency number)
Flag) to registers 33 and 34 only once.
In such a case, the above process is extremely simplified.
It is. In the above description of the operation, the channel flags CHF1, CHF
The case where both 2 are high level “1” was explained
Set one of these flags to high level “1”, and
To set the other flag to low level “0”
The key-on data KON or the frequency number FN
Only one or the other is used in common by the two calculation channels
I can do it. In particular, although omitted in FIG.
The shift stores the control parameters that can be used simultaneously.
A pair of other shift registers, such as registers 43 and 44
Are provided in the shift registers 33 and 34.
For each bit of the channel flag
The control parameter in the shift register of
Channel only or only two computation channels
Can control whether to use the channel flag.
Writing time can be reduced. In the above embodiment, one tone signal is formed.
To use these two computation channels to
Use common control parameters between computation channels.
Has been described as an example, but different tone signal formation
Control parameters in common between calculation channels for
Can also be used. Also, of course,
The embodiment is applied to an electronic musical instrument that forms a tone signal by an FM synthesis method.
Although the present invention has been applied, the present invention applies other types of modulation operations.
Method used, waveform memory readout method, harmonic synthesis method
It can also be applied to electronic musical instruments with different tone synthesis methods such as
You. Further, in the above embodiment, the same control parameters are used.
Is an example in which only two computation channels can be used in common.
Has been explained, but the same
Enable common use of control parameters
Can also. In such a case, the selectors 47 and 51 in FIG.
Input data from other stages of shift registers 41-44
In this way, the selector 47,51
Is controlled by timing signals corresponding to the other stages.
What should I do?

[Brief description of the drawings]

FIG. 1 is an overall block diagram of an electronic musical instrument to which a musical tone control parameter supply device according to one embodiment of the present invention is applied, FIG. 2 is a detailed block diagram of an interface, a register unit, and a control unit of FIG. 1, and FIG. FIG. 4 is a detailed circuit diagram of the channel counter of FIG. 2, FIG. 4 is a detailed circuit diagram of the register write signal generator of FIG. 2, FIG. 5 is a flowchart showing an example of a program executed by the microcomputer of FIG. FIG. 6 is a format diagram of channel flag data, FIGS.
7D is an operation state diagram for explaining the operation of the shift register and the selector for the channel flag of FIG. 2, and FIGS. 8A to 8D explain the operation of the shift register and the selector for the control parameter of FIG. And FIG. Explanation of reference numerals 10 ... keyboard, 11 ... operator group, 12 ... microcomputer, 13 ...
Interface, 14 register unit, 15 control unit
16 ... tone signal forming unit, 21 ... capture control circuit, 22 ...
… Latch signal generator, 23, 32 …… Decoder, 24-26 ……
Latch circuit, 27 channel counter, 28 comparator, 31 register write signal generator, 33, 34, 41-45
... shift registers, 35 to 37, 46 to 48, 51, 52 ... selectors.

Claims (2)

(57) [Claims] 1. A tone signal forming means for forming one tone signal using a plurality of operation channels and simultaneously forming a plurality of tone signals is used for an operation in each operation channel. A musical tone control parameter supply device for supplying control parameters, comprising: a plurality of storage channels respectively corresponding to the respective calculation channels of the musical tone signal forming means; and a parameter storage means capable of storing the control parameters in the respective storage channels. A plurality of flags respectively set for each tone signal formed by the tone signal forming means, and a plurality of flags of a plurality of storage channels respectively corresponding to a plurality of arithmetic channels used for generating one tone signal. The control parameters stored in any one of them are assigned to the same Or control parameters stored in a plurality of storage channels respectively corresponding to a plurality of calculation channels used for generating one musical tone signal are independently used in the same plurality of calculation channels. Flag storage means capable of storing a flag indicating whether or not the control parameter is to be written, and the control parameters are respectively written in a storage channel of the parameter storage means for generating a tone signal, and the flag storage is performed in accordance with the writing of the control parameter. Writing means for writing the flags into the means respectively; and when the flag corresponding to one generated tone signal stored in the flag storage means indicates a common use of the control parameter, the same tone signal is generated. Corresponding to the multiple computation channels used to generate A control parameter stored in any one of the plurality of storage channels is output to each of the plurality of operation channels, and one musical tone generated and stored in the flag storage means is output. When the flag corresponding to the signal indicates the independent use of each control parameter, each control stored in a plurality of storage channels respectively corresponding to a plurality of operation channels used to generate the same tone signal. Output means for outputting parameters to the plurality of operation channels, respectively. 2. The apparatus according to claim 1, wherein said parameter storage means comprises a plurality of stages of first circulating shift registers operating in synchronization with an operation channel of said tone signal forming means, and said flag storage means comprises said first circulating type shift register. A plurality of stages of second cyclic shift registers operating in synchronization with a shift register, and wherein the output means outputs control parameters from different stages of the first cyclic shift register to the second cyclic shift register. The musical tone control parameter supply device according to claim 1, wherein the selector is configured to selectively output the signal in accordance with a flag from the control unit.