JP2730474B2 - FET amplifier - Google Patents
FET amplifierInfo
- Publication number
- JP2730474B2 JP2730474B2 JP5351490A JP35149093A JP2730474B2 JP 2730474 B2 JP2730474 B2 JP 2730474B2 JP 5351490 A JP5351490 A JP 5351490A JP 35149093 A JP35149093 A JP 35149093A JP 2730474 B2 JP2730474 B2 JP 2730474B2
- Authority
- JP
- Japan
- Prior art keywords
- fet
- reference voltage
- distortion
- variable reference
- amplifier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Tone Control, Compression And Expansion, Limiting Amplitude (AREA)
- Amplifiers (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明はＦＥＴ増幅器に関し、特
に、多周波のアナログ信号を増幅するＦＥＴ増幅器に関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an FET amplifier, and more particularly to an FET amplifier for amplifying a multi-frequency analog signal.
【従来の技術】従来のＦＥＴ増幅器は、図２に示す様
に、ＦＥＴ８と規準電圧発生器９から構成され、初期調
整時にＦＥＴ８の歪特性が最適となる様に規準電圧発生
器９を調整している。2. Description of the Related Art As shown in FIG. 2, a conventional FET amplifier comprises an FET 8 and a reference voltage generator 9, and adjusts the reference voltage generator 9 so that the distortion characteristic of the FET 8 becomes optimal during initial adjustment. ing.
【発明が解決しようとする課題】しかしながら、従来の
ＦＥＴ増幅器では歪特性の最適化を初期調整で行ってい
るため、温度変化や、経時変化により、ＦＥＴの特性が
変化した場合、歪特性の最適点から外れるという問題点
がある。本発明の目的は上述の欠点を除したＦＥＴ増幅
器を提供することにある。However, in the conventional FET amplifier, since the distortion characteristic is optimized by initial adjustment, when the characteristic of the FET changes due to a temperature change or a temporal change, the distortion characteristic is optimized. There is a problem of deviating from the point. SUMMARY OF THE INVENTION It is an object of the present invention to provide a FET amplifier which eliminates the above-mentioned disadvantages.
【課題を解決するための手段】上述した目的を達成する
ため、本発明のＦＥＴ増幅器は互いにゲートが接続さ
れ、このゲートに入力信号を受ける同一素子上に構成さ
れた第１のＦＥＴおよび第２のＦＥＴを有する増幅部
と、前記ゲート可変基準電圧を供給する可変基準電圧発
生回路と、前記第２のＦＥＴの出力から歪成分を抽出す
る歪検出手段と、前記歪成分から生成した制御信号を前
記可変基準電圧発生器に出力する手段を備えている。In order to achieve the above object, the FET amplifiers of the present invention have their gates connected to each other , and are configured on the same element receiving an input signal at the gates.
An amplifier unit having a first FET and a second FET that is, a variable reference voltage generating circuit for supplying the gate variable reference voltage, a distortion detecting means for extracting a distortion component from the output of said second FET, Means for outputting a control signal generated from the distortion component to the variable reference voltage generator.
【実施例】次に本発明について図面を参照して説明す
る。図１は本発明の一実施例を示すブロック図である。
同一素子上に構成された複数のＦＥＴは、同一特性を示
すということを利用して、同一素子上にＦＥＴ２及び３
が形成されている。ＦＥＴ２と３のゲートは互いに接続
され、このゲートに入力端子と可変規準電圧発生器７の
出力が接続されている。可変規準電圧発生器７によって
ＦＥＴ２と３のゲート電圧が与えられ、ドレイン電流が
制御される。ＦＥＴ２のドレイン端子はそのまま出力端
子に接続されているが、ＦＥＴ３のドレイン端子はバン
ドパスフィルタ４に接続されている。バンドパスフィル
タ４は入力端子から入力される信号において歪が発生す
る周波数を通す周波数特性を有している。バンドパスフ
ィルタ４にて検出された歪成分をピーク検出器５に入力
し、歪量の絶対値を検出する。ピーク検出器５は検出し
た歪量を電圧比較増幅器６に入力する。電圧比較増幅器
６のもう一方の入力端子には規準電圧Ｖｒｅｆが供給さ
れ、Ｖｒｅｆの値は、本発明のＦＥＴ増幅器に許される
歪量に設定されている。電圧比較増幅器６はピーク検出
器５からの信号がＶｒｅｆよりも大きくなるときに、可
変規準電圧発生器７が出力電圧を可変する様に制御信号
を送る。電圧比較増幅器６はピーク検出器５からの信号
がＶｒｅｆよりも小さいときは、動作せず、従って可変
規準電圧発生器７は現状を保持する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention.
Utilizing the fact that a plurality of FETs configured on the same element show the same characteristics, FETs 2 and 3
Are formed. The gates of the FETs 2 and 3 are connected to each other, and the input terminal and the output of the variable reference voltage generator 7 are connected to this gate. The gate voltages of the FETs 2 and 3 are given by the variable reference voltage generator 7, and the drain current is controlled. The drain terminal of FET2 is connected to the output terminal as it is, while the drain terminal of FET3 is connected to bandpass filter 4. The bandpass filter 4 has a frequency characteristic of passing a frequency at which distortion occurs in a signal input from the input terminal. The distortion component detected by the bandpass filter 4 is input to the peak detector 5, and the absolute value of the distortion amount is detected. The peak detector 5 inputs the detected amount of distortion to the voltage comparison amplifier 6. A reference voltage Vref is supplied to the other input terminal of the voltage comparison amplifier 6, and the value of Vref is set to a distortion amount allowed for the FET amplifier of the present invention. The voltage comparison amplifier 6 sends a control signal so that the variable reference voltage generator 7 changes the output voltage when the signal from the peak detector 5 becomes larger than Vref. The voltage comparison amplifier 6 does not operate when the signal from the peak detector 5 is smaller than Vref, so that the variable reference voltage generator 7 keeps the current state.
【発明の効果】以上説明したように本発明は同一素子上
に作られた複数のＦＥＴが同じ特性をもつことを利用し
て、同一素子上の２つのＦＥＴのうちの一方のＦＥＴの
歪特性が最適になる様にドレイン電流を制御することに
より、等価的にもう一方の実際に信号増幅を行っている
ＦＥＴの歪特性の最適化を行っている。従って、温度変
動、経時変化等で変化するＦＥＴの歪特性を常に最適に
保つことができる。As described above, the present invention makes use of the fact that a plurality of FETs formed on the same element have the same characteristic, and utilizes the distortion characteristic of one of the two FETs on the same element. By controlling the drain current to optimize the distortion characteristic, the distortion characteristic of the other FET that is actually performing signal amplification is equivalently optimized. Therefore, it is possible to always keep the distortion characteristic of the FET that changes due to temperature fluctuation, aging, etc., optimally.
【図１】本発明の一実施例を示すブロック図。FIG. 1 is a block diagram showing one embodiment of the present invention.
【図２】従来のＦＥＴ増幅器のブロック図。FIG. 2 is a block diagram of a conventional FET amplifier.
１ 同一素子上に構成された複合ＦＥＴ ２ １に含まれる内の第１のＦＥＴ ３ １に含まれる内の第２のＦＥＴ ４ バンドパスフィルタ ５ ピーク検出器 ６ 電圧比較増幅器 ７ 可変規準電圧発生器 ８ ＦＥＴ ９ 規準電圧発生器 DESCRIPTION OF SYMBOLS 1 1st FET included in compound FET 21 comprised on the same element 2nd FET included in 1st FET 4 4 bandpass filter 5 peak detector 6 voltage comparison amplifier 7 variable reference voltage generator 8 FET 9 Reference voltage generator
Claims (1)
入力信号を受ける同一素子上に構成された第１のＦＥＴ
および第２のＦＥＴを有する増幅部と、前記ゲートに可
変基準電圧を供給する可変基準電圧発生回路と、前記第
２のＦＥＴの出力から歪成分を抽出する歪検出手段と、
前記歪成分から生成した制御信号を前記可変基準電圧発
生器に出力する手段とから構成されたことを特徴と す
るＦＥＴ増幅器。1. A first FET having a gate connected to each other and configured on the same element for receiving an input signal at the gate.
A and amplification section having a second FET, and a variable reference voltage generating circuit for supplying a variable reference voltage to said gate, said first
Distortion detecting means for extracting a distortion component from the output of the second FET ;
Means for outputting a control signal generated from the distortion component to the variable reference voltage generator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5351490A JP2730474B2 (en) | 1993-12-29 | 1993-12-29 | FET amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5351490A JP2730474B2 (en) | 1993-12-29 | 1993-12-29 | FET amplifier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07202580A JPH07202580A (en) | 1995-08-04 |
| JP2730474B2 true JP2730474B2 (en) | 1998-03-25 |
Family
ID=18417653
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5351490A Expired - Lifetime JP2730474B2 (en) | 1993-12-29 | 1993-12-29 | FET amplifier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2730474B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2720851B2 (en) * | 1995-10-25 | 1998-03-04 | 日本電気株式会社 | Amplifier bias current control circuit |
| JP4565693B2 (en) * | 2000-03-13 | 2010-10-20 | 株式会社日立国際電気 | MOS-FET amplifier circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61102805A (en) * | 1984-10-25 | 1986-05-21 | Fujitsu Ltd | Linear amplification method |
-
1993
- 1993-12-29 JP JP5351490A patent/JP2730474B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07202580A (en) | 1995-08-04 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19971118 |