JP2729001B2 - Reference voltage generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reference voltage generating circuit suitable for use in supplying a reference voltage as a bias voltage to a transistor forming a constant current source of an ECL circuit.

[0002]

2. Description of the Related Art FIG. 8 is a circuit diagram showing an input circuit of a BiCMOS memory, which is an example of an ECL circuit configured to supply a reference voltage as a bias voltage to a transistor forming a constant current source.

In FIG. 1, reference numeral 1 denotes an input terminal to which an input signal IN is input, reference numerals 2 and 3 denote NPN transistors forming a differential pair, and reference numeral 4 denotes a reference voltage input terminal to which a reference voltage Vr for determining a threshold voltage is input. .

[0004] 5 is a positive supply voltage V _P supply for supplying line, 6, 7 NPN transistors 2 and 3 forming a differential pair
Reference numeral 8 denotes a positive-phase output terminal from which a positive-phase output signal OUT is output, 9 denotes a negative-phase output terminal from which a negative-phase output signal OUT is output, and 10 denotes an nMOS transistor serving as a constant current source.

Reference numeral 11 denotes a control signal input terminal to which a control signal S _C is input, 12 denotes a reference voltage input terminal to which a reference voltage Vref to be applied to the gate of the nMOS transistor 10 is input, 13 denotes a pMOS transistor, and 14 denotes nMO
It is an S transistor.

In such an ECL circuit, the control signal S
_{When C} = L level, pMOS transistor 13 = O
N, nMOS transistor 14 = OFF, nMO
The reference voltage Vref is applied to the gate of the S transistor 10, the nMOS transistor 10 is turned on, and the NPN transistors 2 and 3 are activated.

On the other hand, when the control signal S _C = H level, p
The MOS transistor 13 = OFF, the nMOS transistor 14 = ON, and the gate of the nMOS transistor 10 is grounded via the nMOS transistor 14, so that the nMOS transistor 10 = OFF and NPN
Transistors 2 and 3 are made inactive.

Here, conventionally, a circuit as shown in FIG. 9 has been used as a reference voltage generating circuit for generating a reference voltage Vref. In the figure, 15 is a constant current source circuit,
16 is a clamp circuit, 17 is a diode-connected NPN transistor, and 18 is a diode-connected n
It is a MOS transistor.

Reference numeral 19 denotes a power supply line for supplying a power supply voltage V _P , reference numeral 20 denotes an NPN transistor constituting an emitter follower circuit, reference numeral 21 denotes a constant current source, and reference numeral 22 denotes a reference voltage Vre.
f is a reference voltage output terminal to be output.

In this reference voltage generating circuit, the voltage at the node 23 = the voltage between the base and the emitter of the NPN transistor 17 + the voltage at the node 24. Since the voltage is between the emitters, the reference voltage Vref is equal to the voltage of the node 24.

Here, the constant current source circuit 15 is configured, for example, as shown in the circuit diagram of FIG. In the figure, 25
Power supply line supplying a power supply voltage V _P, 26 to 28 are NPN
Transistors, 29 to 32 are resistors, and 33 and 34 are pMOS transistors forming a current mirror circuit.

[0012] In such a constant current source circuit 15, as is the base-emitter voltage of the voltage = NPN transistor 26 of the node 35, the base-emitter voltage of the NPN transistor 26, the power supply voltage V _P fluctuates Also, since the constant value is maintained, the current flowing through the resistor 31 is a constant current. That is, the current flowing through the resistors 30 and 31 is
Regardless of variations in the power supply voltage V _P, a constant current.

As a result, the voltage at the node 36 becomes a constant voltage, and the current flowing through the resistor 32 becomes a constant current. That is, pM
The current flowing between the source and the drain of the OS transistor 33 is a constant current.

Here, the pMOS transistors 33, 34
Constitutes a current mirror circuit.
A pMOS is provided between the source and the drain of the transistor 34.
A current having the same value as the current flowing between the source and the drain of the transistor 33 flows. Thus, in the constant current source circuit 15, a constant current Iconst can be obtained.

[0015]

However, in this constant current source circuit 15, when the temperature rises, the base-emitter voltage of the NPN transistor 26 decreases.
The current flowing through the resistors 30 and 31 decreases,
As a result, the current flowing through the resistor 32 decreases, and the current Iconst flowing through the pMOS transistor 34 decreases.
Is also smaller.

As described above, when the current Iconst output from the constant current source circuit 15 decreases, in the reference voltage generating circuit shown in FIG. 9, the voltage at the node 23 decreases, and the reference voltage Vref decreases.

SUMMARY OF THE INVENTION In view of the foregoing, it is an object of the present invention to provide a reference voltage generating circuit capable of reducing a temperature dependency and obtaining a reference voltage whose voltage change is as small as possible with respect to a temperature change. I do.

[0018]

According to the present invention, in a reference voltage generating circuit according to the first aspect of the present invention, a clamp circuit is connected to a downstream side of a constant current source circuit having a characteristic that a current value decreases in response to a temperature rise. And improving a reference voltage generating circuit configured to obtain a reference voltage at a connection point between the constant current source circuit and the clamp circuit, wherein the clamp circuit includes a MOS transistor in a current path thereof. It is configured by connecting resistance elements in series.

In the present invention, the reference voltage generating circuit according to the second aspect of the present invention includes a clamp circuit connected to a downstream side of a constant current source circuit having a characteristic that a current value decreases in response to a rise in temperature. A reference voltage generating circuit in which a connection point between a constant current source circuit and the clamp circuit is connected to a base of an NPN transistor constituting an emitter follower circuit, and a reference voltage is obtained at an emitter of the NPN transistor. Wherein the clamp circuit comprises:
The current path is configured by connecting a resistance element composed of a MOS transistor in series.

In the present invention, the reference voltage generation circuit according to the third invention also includes a clamp circuit connected to a downstream side of a constant current source circuit having a characteristic that a current value decreases in response to a temperature rise. A reference voltage generating circuit in which a connection point between a constant current source circuit and the clamp circuit is connected to a base of an NPN transistor constituting an emitter follower circuit, and a reference voltage is obtained at an emitter of the NPN transistor. Wherein the emitter follower circuit includes a first nMOS transistor provided on an emitter side of the NPN transistor, and the clamp circuit has a gate connected to a drain of the first nMOS transistor, And a second nMOS transistor forming a current mirror circuit together with the nMOS transistor It is intended to refer.

[0021]

According to the first aspect of the present invention, when the temperature rises, the on-resistance value of the MOS transistor forming the resistance element increases. Therefore, even when the current of the constant current source circuit decreases due to the temperature rise, the voltage at the connection point between the constant current source circuit and the clamp circuit, that is, the change in the reference voltage can be minimized.

Also in the second invention, when the temperature rises, the on-resistance value of the MOS transistor forming the resistance element increases. Therefore, even when the current of the constant current source circuit becomes small due to the temperature rise, the voltage change at the connection point between the constant current source circuit and the clamp circuit can be suppressed as small as possible, and the change in the reference voltage can be made as small as possible. it can.

In the third aspect, when the temperature rises, the on-resistance value of the second nMOS transistor increases. Therefore, even when the current of the constant current source circuit becomes small due to the temperature rise, the voltage change at the connection point between the constant current source circuit and the clamp circuit is suppressed as small as possible.
The change in the reference voltage can be minimized.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The first to seventh embodiments of the present invention will be described below with reference to FIGS. 1 to 7
In FIG. 9, the portions corresponding to those in FIG. 9 are denoted by the same reference numerals, and the description thereof will not be repeated.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention. In the first embodiment, a constant current source circuit 15, nMOS transistors 18 and 37, a reference The nMOS transistors 18 and 37 constitute a clamp circuit.

Here, the output terminal 15A of the constant current source circuit 15 is connected to the reference voltage output terminal 22 and the drain of the nMOS transistor 37, and the gate of the nMOS transistor 37 is connected to the power supply line 38. Its source is connected to the drain of the nMOS transistor 18.

That is, in the first embodiment, the nMO
The S transistor 37 is used as a resistance element using the ON resistance. The nMOS transistor 18 is diode-connected, the drain is connected to the gate, and the source is grounded, as in the conventional example.

In the first embodiment, when the temperature rises, the on-resistance value of the nMOS transistor 37 increases, so that the constant current output from the constant current source circuit 15 decreases due to the temperature rise. Also, the reference voltage Vre
The voltage change of f can be minimized. Thus, according to the first embodiment, the temperature dependency is reduced,
The reference voltage Vref whose voltage change is as small as possible with respect to temperature change
Can be obtained.

Second Embodiment FIG. 2 is a circuit diagram showing a second embodiment of the present invention. In the second embodiment, a pMOS transistor 39 is used instead of the nMOS transistor 37 in the first embodiment. And the pMOS transistor 39 is used as a resistance element. In this example, the gate of the pMOS transistor 39 is grounded.

Also in the second embodiment, the same operation and effect as in the first embodiment can be obtained by the pMOS transistor 39 serving as a resistance element.

Third Embodiment FIG. 3 FIG. 3 is a circuit diagram showing a third embodiment of the present invention. In the third embodiment, a pMOS transistor 39 whose gate is grounded is connected in parallel to an nMOS transistor 37, and the other configuration is the same as that of the first embodiment.

According to the third embodiment, more accurate temperature compensation can be performed by utilizing the difference between the temperature characteristic of the ON resistance of the nMOS transistor 37 and the temperature characteristic of the ON resistance of the pMOS transistor 39. it can.

Fourth Embodiment FIG. 4 FIG. 4 is a circuit diagram showing a fourth embodiment of the present invention. The fourth embodiment is different from the first embodiment in that an NPN
In this embodiment, an emitter follower circuit 40 including a transistor 20 and a constant current source 21 is connected. As a result, the conventional example shown in FIG. 9 is improved, and an nMOS transistor 37 serving as a resistance element is connected in place of the NPN transistor 17 serving as a diode shown in FIG.

According to the fourth embodiment, the nMOS transistor 37 serving as a resistance element reduces the temperature dependency similarly to the first embodiment, and obtains a reference voltage whose voltage change is as small as possible with respect to a temperature change. Since the emitter follower circuit 40 is provided and the reference voltage generation circuit is connected to the ECL circuit shown in FIG. 8, even when a through current flows through the pMOS transistor 13 and the nMOS transistor 14, Since there is no need to supply this through current from the constant current source circuit 15, fluctuations in the reference voltage Vref can be reduced.

Fifth Embodiment FIG. 5 FIG. 5 is a circuit diagram showing a fifth embodiment of the present invention. In the fifth embodiment, the NPN transistor 17 is diode-connected between the node 23 and the drain of the nMOS transistor 37, and the other configuration is the same as that of the fourth embodiment.

According to the fifth embodiment, the reference voltage Vref
In addition to the voltage of the node 41, the same operation and effect as those of the fourth embodiment can be obtained.

Sixth Embodiment FIG. 6 FIG. 6 is a circuit diagram showing a sixth embodiment of the present invention. The sixth embodiment is different from the sixth embodiment in that n
The MOS transistors 42 and 43 are connected, and the nMOS transistor 42 is used as a resistance element and the nMOS transistor 43 is used as a constant current source element.

Here, the nMOS transistor 42 has its drain connected to the emitter of the NPN transistor 20, its gate connected to the power supply line 38, and its source connected to the drain of the nMOS transistor 43.

The nMOS transistor 43 has its gate connected to the gate of the nMOS 18 and its source grounded. That is, the nMOS transistor 4
Reference numeral 3 forms a current mirror circuit together with the nMOS transistor 18.

In the sixth embodiment, the same operation and effect as in the fifth embodiment can be obtained.

Seventh Embodiment FIG. 7 FIG. 7 is a circuit diagram showing a seventh embodiment of the present invention. The seventh embodiment eliminates the NPN transistor 17 and the nMOS transistor 37 in the sixth embodiment shown in FIG.
The gate of the nMOS transistor 18 is connected to the drain of the nMOS transistor 43.

In the seventh embodiment, even when the temperature rises and the current of the constant current source circuit 15 decreases, the on-resistance value of the nMOS transistor 18 increases, so that the voltage change at the node 23 Is minimized, and the voltage change of the reference voltage Vref can be minimized.

In the above-described fourth to sixth embodiments, the description has been given of the case where the resistance element for performing the temperature compensation is constituted by the nMOS transistor 37. Instead, however, the pMOS transistor or the pMOS transistor is used. It can also be constituted by a parallel circuit with an nMOS transistor or a series circuit of these.

[0044]

According to the first aspect of the present invention, when the temperature rises, the on-resistance value of the MOS transistor forming the resistance element increases when the temperature rises. Even when the current of the constant current source circuit decreases due to the rise, the voltage at the connection point between the constant current source circuit and the clamp circuit, that is, the change in the reference voltage can be minimized.

Also, according to the second invention (the reference voltage generating circuit according to claim 2), when the temperature rises, the on-resistance value of the MOS transistor forming the resistance element increases. Even when the current of the circuit becomes small, the voltage change at the connection point between the constant current source circuit and the clamp circuit can be suppressed as small as possible, and the change in the reference voltage can be made as small as possible.

According to the third invention (the reference voltage generating circuit according to claim 3), when the temperature rises, the second n
Since the ON resistance value of the MOS transistor increases, even when the current of the constant current source circuit decreases due to a rise in temperature, the voltage change at the connection point between the constant current source circuit and the clamp circuit is minimized, The change in the reference voltage can be minimized.

That is, according to the first invention, the second invention or the third invention, it is possible to reduce the temperature dependency and obtain a reference voltage whose voltage change is as small as possible with respect to the temperature change. .

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a third embodiment of the present invention.

FIG. 4 is a circuit diagram showing a fourth embodiment of the present invention.

FIG. 5 is a circuit diagram showing a fifth embodiment of the present invention.

FIG. 6 is a circuit diagram showing a sixth embodiment of the present invention.

FIG. 7 is a circuit diagram showing a seventh embodiment of the present invention.

FIG. 8 is a circuit diagram showing an example of a circuit using a reference voltage.

FIG. 9 is a circuit diagram showing an example of a conventional reference voltage generation circuit.

FIG. 10 is a circuit diagram showing a constant current source circuit.

[Description of Signs] 15 Constant current source circuit 22 Reference voltage output terminal

Claims (3)

(57) [Claims] A clamp circuit is connected downstream of a constant current source circuit having a characteristic that a current value decreases in response to a temperature rise, and a reference voltage is applied to a connection point between the constant current source circuit and the clamp circuit. In the reference voltage generation circuit configured to obtain the reference voltage generation circuit, the clamp circuit is configured by connecting a resistance element including a MOS transistor in a current path thereof in series. 2. A clamp circuit is connected downstream of a constant current source circuit having a characteristic that a current value decreases in response to a rise in temperature, and a connection point between the constant current source circuit and the clamp circuit is connected to an emitter follower. In a reference voltage generating circuit configured to be connected to a base of an NPN transistor constituting a circuit and to obtain a reference voltage at an emitter of the NPN transistor, the clamp circuit includes, in a current path thereof, a resistance element formed of a MOS transistor in series. A reference voltage generation circuit, wherein the reference voltage generation circuit is connected to 3. A clamp circuit is connected downstream of a constant current source circuit having a characteristic that a current value decreases in response to a rise in temperature, and a connection point between the constant current source circuit and the clamp circuit is connected to an emitter follower. In a reference voltage generating circuit connected to a base of an NPN transistor constituting a circuit and configured to obtain a reference voltage at an emitter of the NPN transistor, the emitter follower circuit includes a first nMOS connected to an emitter of the NPN transistor. A transistor is provided, and the clamp circuit connects the gate to the first nM
Connected to the drain of the OS transistor, the first nM
The second that forms a current mirror circuit with the OS transistor
A reference voltage generating circuit comprising: an nMOS transistor.