JP2728458B2 - Manufacturing method of mixed semiconductor device - Google Patents

Description

The present invention relates to a large-scale integrated circuit (LSI) with high speed and low power consumption.
In particular, an NPN bipolar transistor having a self-aligned emitter electrode and a base electrode, and a complementary MIS
The present invention relates to a technology that is effective when applied to a method of manufacturing a mixed semiconductor device in which an FET (CMOS) is formed on the same substrate.

(Prior art)

Various methods have been proposed as a mixed-type semiconductor device (hereinafter, referred to as Bi-CMOS) in which a bipolar transistor and an MISFET in which an emitter electrode and a base electrode are formed in a self-aligned structure are formed on the same substrate, and a manufacturing method thereof. .

As one of the manufacturing methods, there is a method in which a base extraction electrode and a MOS gate electrode are formed in the same step.

FIGS. 3A, 3B, 3C and 3D show the case where polycrystalline silicon is used as a base extraction electrode of a bipolar transistor and a MOS.
FIG. 4 is a diagram for explaining a method used for the gate electrode of FIG.

First, as shown in FIG. 3A, a selective oxide film 1 for element isolation and a gate oxide film 2 are formed on a substrate 100. On top of this, an N-type polycrystalline silicon layer 3 and a P-type polycrystalline silicon layer 4
Is formed. The polycrystalline silicon layer 4 serving as the base of the bipolar transistor is in direct contact with the substrate 100 and is doped P-type. The polycrystalline silicon layer 3 is a portion serving as a gate of the MOS, and is connected to the substrate 100 at a buried contact portion (direct contact portion) 6. Normally, it is desirable that the polycrystalline silicon layer 3 is doped into N-type from the relation of the work function of the gate of the NMOS.

In addition, highly integrated SRAM using NMOS (Static Randam Ac
cess memory), the embedded contact 6
A part connecting the N-type gate to the substrate 100 as described above is indispensable. An oxide film (insulating film) 5 is deposited thereon by a CVD (Chemical Vapor Deposition) method.

Next, as shown in FIG. 3B, the polycrystalline silicon layer 4 is processed to form a base extraction electrode 4A of the bipolar transistor, and the polycrystalline silicon layer 3 is processed to form a MOS gate electrode 3A. The external base layer 8 of the mold is diffused into the substrate 100.

Next, as shown in FIG.
After forming the source / drain 11, an oxide film is deposited by the CVD method, anisotropic etching is performed, and a sidewall spacer 10 made of an oxide film is formed on the side surface of the base extraction electrode 4A of the bipolar transistor and the gate electrode 3A of the MOS. It is formed.

Next, as shown in FIG. 3D, after an internal base layer 12 of the bipolar transistor is formed, a polysilicon layer 13 serving as an emitter electrode is formed, and an emitter region 14 is formed. Further, the source / drain 11 of the NMOS is formed.

[Problems to be solved by the invention]

However, as a result of studying the above-mentioned manufacturing method, the present inventor has found that in the above-mentioned manufacturing method, a bipolar transistor having a self-aligned structure and a CMOS (here, only an NMOS is shown) can be formed at the same time. Since no electrodes are used, the inventors have found that the gate resistance is large (several tens of ohms / square) and is not suitable for semiconductor devices such as LSIs operating at high speed.

That is, since no polycide or metal electrode is used as a CMOS gate, the resistance of the gate electrode is large (several tens of ohms / port), which is not suitable for a high-speed operation LSI. When the gate size becomes submicron, the delay due to the resistance of the gate is a great constraint on increasing the speed. Further, the number of steps for dividing the polycrystalline silicon layer into N-type and P-type is increased.

A method of performing silicidation after electrode formation using only P-type polycrystalline silicon in a manner similar to FIGS. 3A to 3D has been proposed (IEEE electron devices letter).
s Vol edl-8 No11 pp509-511)
The problem of the threshold voltage Vth lowering due to the short channel effect on the NMOS for the NMOS type gate and the use of a method of reducing the memory cell size (buried contact) in forming a high resistance load type NMOS memory cell There were problems such as not being able to do.

In the method of FIGS. 3A to 3D, instead of polycrystalline silicon,
Problems in the case of using a polycide layer will be described with reference to FIGS. 4A to 4C (the steps are the same as those in FIGS. 3 to 3D).

The structure is such that a silicide layer 15 is overlaid on the N-type polycrystalline silicon layer 3 and the P-type polycrystalline silicon layer 4. When such a structure is used, the diffusion coefficient of impurities in silicide is several orders of magnitude larger than that in single crystal or polycrystalline silicon, and the mutual Diffusion occurs, and as shown in FIG. 4A, a phenomenon occurs in which the P-type polycrystalline surface is inverted to N-type and the N-type inversion layer 16 is formed. The electrode processing shown in FIG. 4B and the formation of the bipolar transistor and the NMOS shown in FIG. 4C are the same as those shown in FIGS. 3A to 3D, except that the Bi-CMOS shown in FIG.
In this case, there is a problem that the presence of the N-type inversion layer 16 causes rectification between the silicide 15 and the P-type polycrystalline layer 3 and abnormally increases the base resistance of the bipolar transistor.

In addition, a method has been proposed in which the base extraction electrode 4A and the MOS gate electrode 3A are separately formed of a polycrystalline silicon layer, and the sidewall spacers are separately formed (Japanese Patent Application Laid-Open Nos. Sho 62-155553 and 62-155553). (See JP-A-62-155554)
However, these manufacturing methods increase the number of manufacturing steps, and
There is a problem that it is difficult to speed up the CMOS.

An object of the present invention is to provide a method of manufacturing a Bi-CMOS in which a bipolar transistor and a MISFET having a self-aligned structure are formed on the same substrate, wherein the Bi-CMOS has a small gate resistance and operates at high speed. Is to provide.

The above and other objects and novel features of the present invention are as follows.
It will become apparent from the description of the present specification and the accompanying drawings.

[Means for solving the problem]

The outline of a typical invention disclosed in the present application is briefly described as follows.

That is, a side wall spacer is formed on the side wall of the base extraction electrode, and a bipolar transistor that forms an emitter electrode in self-alignment with the side wall spacer, and a side wall spacer is formed on the side wall of a gate electrode mainly composed of a transition metal. And a MISFET, wherein the base extraction electrode of the bipolar transistor and the gate electrode of the MISFET are formed in different steps, and then the sidewall spacers formed on the side walls of the two electrodes are formed in the same step. This is a method for manufacturing a mixed-type semiconductor device formed by:

[Action]

According to the above-described means, first, a base extraction electrode of a bipolar transistor is formed using P-type polycrystalline silicon or polycide having the same.

Next, a CMOS gate electrode made of a material mainly composed of a transition metal such as polycide or silicide is formed. As a result, it is possible to avoid deterioration in performance due to forming both electrodes in the same process. Next, by forming sidewall spacers on both electrodes in the same process, the formation of an LDD (Lightly Doped Drain) CMOS and the self-alignment separation of the emitter and base electrodes of the bipolar transistor can be performed without increasing the manufacturing process. It can be performed.

Thus, a Bi-CMOS with a small gate resistance and high-speed operation can be manufactured.

Hereinafter, an embodiment of the present invention will be specifically described with reference to the drawings.

In all the drawings, components having the same function are denoted by the same reference numerals, and repeated description thereof will be omitted.

[Example I of the invention]

FIGS. 1A, 1B, 1C, and 1D show Embodiment I applied to a method of manufacturing a mixed semiconductor device having Bi-CMOS according to the present invention.
Explanation will be made with reference to FIG. 1, FIG. 1E and FIG. 1F.

First, as shown in FIG. 1A, after a selective oxide film 1 (700 nm) for device isolation and a gate oxide film 2 (20 nm) are formed on the main surface of a silicon substrate 100, the gate oxide in a bipolar transistor formation region is formed. After the film 2 is removed, P-type polycrystalline silicon layers 3 and 4 having a thickness of 200 nm are formed by a CVD method,
An oxide film (insulating film) 5 (300 nm) is formed thereon.

Next, as shown in FIG. 1B, the two-layered film of the P-type polycrystalline silicon film 4 and the oxide film 5 is processed by using a photo-etching technique to form a base extraction electrode 4A. Next, an external base layer (P-type semiconductor region) 8 of the bipolar transistor is formed on the silicon substrate 100 from the P-type polycrystalline silicon film 4. This P-type semiconductor region 8 becomes an external base region.

Next, as shown in FIG. 1C, in order to prevent diffusion of N-type impurities into the bipolar transistor portion, a thin oxide film 17 is formed.
(20 nm) is formed in advance. After a window is formed in the oxide film of the buried contact portion 6 connecting the gate and the substrate 100, a 20 nm N-type polysilicon 18 and a 20 nm tungsten silicide 19 are formed to form a gate electrode 18A having a polycide structure. Deposit the overlay film.

Next, as shown in FIG. 1D, the gate electrode 18A is processed to form an N-type low concentration diffusion layer 7 for forming a low concentration drain.

Next, as shown in FIG. 1E, after depositing a CVD oxide film of about 400 nm, the MOS gate electrode 18A is anisotropically etched.
Side and base extraction electrode 4A of bipolar transistor
Is formed on the side surface of the substrate.

Next, as shown in FIG. 1F, after this, an internal base layer 12 and an emitter diffusion layer 14 formed beforehand under the emitter are formed, and the NMOS source / drain 11 and N-type polycrystalline silicon (200 nm) are formed. The emitter electrode 13 is formed according to (1), and thereafter, the normal processing is performed to complete the mixed semiconductor device having Bi-CMOS.

Although the above is an example in which polycrystalline silicon is used for the base extraction electrode and polycide is used for the gate electrode of the MOS, other combinations of materials are also possible.

(Example II of the invention)

FIGS. 2A, 2B, 2C and 2D show the results of the embodiment I.
FIG. 9 is a cross-sectional view of each part in the manufacturing process of Example II for the purpose of reducing the base resistance by using a polycide layer also for the base extraction electrode 4A.

The manufacturing process of Example II is similar to FIGS. 1A to 1F,
2A, a 200 nm P-type polycrystalline silicon 4 and a tungsten silicide (200 n
m) Twenty stacked films are formed. The processing of the base extraction electrode 4 in FIG. 2B, the formation of the gate electrode 18A in FIG. 2C, the formation of the buried contact, and the formation of the NMOS and bipolar transistors in FIG. 2D are completely the same as the steps respectively corresponding to FIGS. 1A to 1F. The same is true.

Note that a metal, for example, a transition metal such as tungsten can be used as the material of the gate electrode 18A.

As described above, according to the embodiments I and II, the formation of the base electrode 4A of the bipolar transistor and the formation of the gate electrode 18A of the MOS are performed in separate steps, so that the silicide or transition required for increasing the speed of the MOS is performed. A material mainly composed of metal is used for the gate electrode 18A, and the base extraction electrode 4A is formed in a state in which there is no problem in the process, and thereafter, the sidewall spacer 10 on the electrode side surface can be formed in the same process, thereby simplifying the process. In a simple process, self-assembly separation between the MOS having the LDD structure and the emitter and base electrodes can be simultaneously formed.

Compared with the prior art shown in FIG. 3, the number of polycrystalline silicon or polycide forming steps increases, but the number of photoetching steps does not increase.

Note that a typical LSI using the present invention is a high-speed SRA
There is M (Static Ramdom Access Memory). The memory cell is usually an NMOS memory cell with a high resistance (several tens of GΩ) load. In order to reduce the cell area, a buried contact 6 for connecting the gate and the substrate is used. In this case, the gate needs to be N-type and can be realized by using the present invention.

Further, in Examples I and II, the example in which the MOS gate electrode 18A is formed after the base extraction electrode 4A of the bipolar transistor is formed has been described, but the process order is changed, and the MOS gate electrode 18A is formed first. And then the base extraction electrode 4A
After that, the side wall spacer is used.
There is also a method of forming 10 at the same time. In this case, a similar result is obtained.

As mentioned above, although the present invention was explained concretely based on an example, the present invention is not limited to the above-mentioned example.
It goes without saying that various changes can be made without departing from the scope of the invention.

〔The invention's effect〕

The effects obtained by the representative inventions among the inventions disclosed in the present application will be briefly described as follows.

Forming a base extraction electrode of the bipolar transistor;
The gate electrode of the MISFET is formed in a different process, and
Since the sidewall spacers (insulating layers) formed on the side walls of the two electrodes are formed in the same step, deterioration of performance due to forming both electrodes in the same step can be avoided, and the manufacturing process MIS with LDD structure without increasing
The formation of the FET and the self-alignment separation of the emitter and base electrodes of the bipolar transistor can be performed.

As a result, a mixed semiconductor device with low gate resistance and high-speed operation can be manufactured.

[Brief description of the drawings]

FIGS. 1A, 1B, 1C, 1D, 1E and 1F show the steps of Embodiment I applied to the method of manufacturing a mixed semiconductor device having a Bi-CMOS according to the present invention. Sectional views, FIGS. 2A, 2B, 2C and 2D show embodiments of the present invention.
FIGS. 3A to 3D and FIGS. 4A to 4C show cross sections of respective parts in the manufacturing process of II.
FIG. 7 is a diagram for describing a problem of a method of manufacturing a mixed-type semiconductor device having In the drawing, 100: silicon substrate, 1: selective oxide film for element isolation, 2: gate oxide film, 3: N-type polycrystalline silicon layer, 4: P-type polycrystalline silicon layer, 4A: base Lead electrode, 5 ... oxide film (insulating film), 6 ... embedded contact portion, 7 ... low concentration diffusion layer of NMOS, 8 ... bipolar external base layer (P type semiconductor region), 9 ... embedded contact N-type diffusion layer, 10 ... sidewall spacer, 11
... NMOS source / drain, 12 base layer of bipolar transistor, 13 emitter electrode of bipolar transistor, 14 emitter diffusion layer of bipolar transistor, 15 silicide layer, 16 N-type impurity layer, 17
…… Diffusion prevention oxide film, 18A …… Gate electrode, 18 …… N
Type polycrystalline silicon, 19 ... tungsten silicide, 20
...... Tungsten silicide for base extraction electrode.

Continuation of the front page (72) Inventor Mitsuru Hirao 4026 Kuji-cho, Hitachi City, Ibaraki Prefecture Within Hitachi Research Laboratory, Hitachi, Ltd. (56) References JP-A-62-155553 (JP, A) JP-A-63-239856 (JP) , A) JP-A-63-37643 (JP, A)

Claims (1)

(57) [Claims] 1. A bipolar transistor in which a side wall spacer is formed on a side wall of a base extraction electrode and an emitter electrode is formed in self alignment with the side wall spacer, and a side wall is formed on a side wall of a gate electrode mainly composed of a transition metal. A mixed-type semiconductor device having a MISFET forming a spacer, wherein the base extraction electrode of the bipolar transistor and the gate electrode of the MISFET are formed in different steps, and thereafter, the sidewall spacer is formed on the side walls of the two electrodes. Are formed in the same step.