JP2721474B2 - Receiver for spread spectrum communication - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a receiver for spread spectrum communication, and more particularly to an improvement in synchronization establishment or synchronization tracking in a direct spread (DS) spread spectrum (SS) communication system.

[0002]

2. Description of the Related Art A direct spread (DS) spread spectrum communication system (hereinafter referred to as an SS system) has advantages such as being strong in interference and hardly causing interference. Intensive research has been conducted as one of communication systems for mobile communication such as telephones.

[0003] Fig. 19 shows a schematic configuration of this SS type transceiver. Fig. 19 (A) is a transmitting side (satellite station or base station), and Fig. 19 (B) is a receiving side (earth). Station or mobile station). On the transmitting side, a pseudo-noise signal (PN code) generator 4 generates a binary PN code, and multiplies the information signal by spread modulation. Then, a predetermined carrier is phase-modulated and transmitted as an SS signal from the antenna 5. On the other hand, on the receiving side, the SS signal is received by the antenna 6 and supplied to the synchronizing circuit 7 to establish synchronization of the code used by the PN code generator 4 on the transmitting side, and the same code is spread by the spread demodulator 8.
Supply to The spread demodulator 8 performs spread demodulation by multiplying the received SS signal by the code from the synchronization circuit 7, and further demodulates the spread-demodulated signal by the information demodulator 9.

Here, in order to establish synchronization in the synchronization circuit 7, frequency synchronization for accurately tuning by searching an uncertain frequency region and searching for a phase matching point with the transmitted PN code. Therefore, it is necessary to realize timing synchronization for suppressing the timing deviation within a predetermined range.

FIG. 20 shows a general circuit configuration for performing frequency synchronization and timing synchronization shown in, for example, “Spread Spectrum Communication System” by Mitsuhiko Yokoyama (published by Science and Technology Publishing Company, 1988). ing. In response to a command from the frequency controller 11, the frequency of the VCO 12 is fixed at a certain value and output. On the other hand, the clock 14 of the PN code generator 15 is also set to a certain value according to a command from the clock controller 13. In this state, the sine wave from the VCO 12 and P
The signal from the N code generator is multiplied to generate a signal for spread demodulation. Then, the received SS signal from the antenna 6 is multiplied by the spread modulation signal, and the bandpass filter BPF
16. The component that has passed through the BPF 16 is squared by a squarer 17, detected by an integrator 18, and its level is compared with a predetermined threshold by a search control logic circuit 19. If the level is equal to or higher than the threshold value, it is determined that the initial acquisition has been completed, the search is stopped, and the operation shifts to a tracking operation using a delay lock loop (DLL). On the other hand, when the level is equal to or less than the threshold, the clock is advanced by a predetermined step (Δ / 2), and the level comparison is performed each time. This operation is performed for a time corresponding to one cycle of the PN code. If the initial acquisition is not completed by this operation, the frequency of the VCO 12 is further changed by a predetermined amount, and the level comparison is performed. FIG. 21 schematically shows a search operation as described in the same document as FIG. 20, in which the horizontal axis is a time axis representing timing, and the vertical axis is a frequency axis representing frequency. The clock and frequency are shifted by predetermined steps until the level becomes equal to or higher than a predetermined threshold, and a search is sequentially performed on (t, f). This operation is a synchronous cell whose level is equal to or higher than the threshold (shaded area in the figure)
Until it reaches.

[0006] After the initial acquisition is completed, tracking of data timing is performed using a delay lock loop (DLL) or the like.

On the other hand, as a method for establishing synchronization, a method using a matched filter (matched filter) instead of using such a sliding correlation has been proposed. FIGS. 22 and 24 show, for example, IEICE Transactions Vo.
l. J69-BNo. 11pp. 15 shows a method of establishing synchronization using a matched filter shown in FIGS. FIG. 22 shows an example of a carrier phase synchronization and data timing synchronization circuit using a matched filter. This shows a method of synchronizing with respect to the phase of a carrier wave and synchronizing with respect to data timing after frequency synchronization is established. A method for establishing frequency synchronization will be described later. The received SS signal is transformed into two orthogonal local signals (a signal from the VCO 19 and a signal obtained by phase-shifting this signal by π / 2) prepared by the receiving side and a baseband signal by a low-pass filter LPF21.
This is sampled by a sample hold circuit S / H22,
It is supplied to the correlator 23. The correlator 23 is composed of a matched filter and has a PN code PN for a desired signal.
(K) is prepared, and multiplication is performed for each chip of the PN1 cycle of the received SS signal and the PN1 cycle prepared in advance, and the sum is calculated.

FIG. 23 shows a schematic configuration of a correlator 23 composed of a matched filter. Receive SS
The signals are sequentially stored in the shift register 23a one chip at a time. On the other hand, the coefficient generator 23b generates a PN code sequence, and multiplies the SS signal stored in the shift register 23a for each chip. The result of the multiplication is supplied to the adder 23c, and the sum is calculated and output. Coefficient generator 23
When the timing of the PN code sequence from b and the PN code of the received SS signal match, the output from the adder 23c becomes the maximum (matched pulse). Then, by sampling and holding the signal product from the correlator 23 (I and Q) with the matched pulse, information on the phase difference is obtained every PN1 period. Furthermore, the carrier is supplied to the VCO 19 through an appropriate loop filter 25 to establish carrier phase synchronization. After the phase synchronization of the carrier wave is established, the phase difference of the carrier wave between transmission and reception becomes 0, so that the data can be demodulated by the polarity of the matched pulse. Also, by using the matched pulse which is the maximum value of the correlator, the data timing is equivalently tracked.

FIG. 24 shows an example of a frequency synchronization circuit using a matched filter similar to that shown in FIG. This shows a method of frequency synchronization performed prior to the operation shown in the circuit of FIG. 22 in that a squarer 26, a matched pulse detector 27, a CPU 28, and a frequency counter 29 are added to the output side of the correlator 23. That is, the output from the squarer 26 is added by the adder and supplied to the matched pulse detector 27. This square sum output is the frequency difference Δω
Becomes maximum at 0, the CPU 28 instructs the VCO to find a frequency so that the output detected by the matched pulse detector 27 becomes maximum, and establishes synchronization. After the frequency synchronization is established, tracking is performed by monitoring the frequency of the VCO with the frequency counter 29 and controlling the local signal frequency so that the frequency always becomes a reference value. Although not shown in FIG. 22, the detection of the matched pulse is performed in the same manner as in FIG. The detection method in the matched pulse detector is described in detail in the same document.

[0010]

As described above, as a method of establishing frequency synchronization and timing synchronization, a method using a sliding correlator and a method using a matched filter are known. There is a problem that it takes a long time to establish synchronization.

That is, with respect to the initial acquisition, in either case, in principle, when frequency synchronization is achieved, the frequency at which the correlation pulse level becomes a peak is searched while changing the center frequency. If timing synchronization has not been established, it is difficult to detect a peak. In particular, in the sliding correlation method, as described above, it is necessary to detect the peak by changing the timing simultaneously with the frequency. In the example of FIG. 21, it takes a long time from the initial setting (t0, f0) to reach the synchronous cell. You need it.

As a method of shortening the frequency search time, for example, (1) a satellite beacon signal is used, and (2) one of the stations participating in communication always transmits a pilot signal, and the other station transmits the pilot signal. (3) Use a carrier recovery circuit (4) Use a passive synchronous circuit (5) Use an auxiliary signal, etc. .
(1) Not applicable without a beacon signal. (2) Not applicable without a pilot signal. Even if there is a spread spectrum, a frequency search operation is required. Susceptible to interference waves or frequency selective fading.

(3) It takes a long time to recover the carrier.

(5) Not applicable without an auxiliary signal. Examples in the case of utilizing passive synchronization circuit (4) is Ru include JP-B-63-31127. This
This is because the PN code cycle and add characteristic, that is, the delayed multiplication of the PN code is converted into a PN code having a different delay time. Using the characteristics that can be obtained, it is possible to establish timing synchronization even if there is uncertainty in the frequency due to passive operation.
no and the add properties, there is a problem that can not be applied in a more general PN code series.

Further, a configuration is also conceivable in which a plurality of frequency synchronization systems are prepared and a frequency at which the correlation pulse level has a peak at different frequencies is searched. However, there is a problem that the configuration of the apparatus becomes complicated and large.

[0016] Also, with respect to tracking using a matched filter having excellent timing synchronization characteristics, a frequency shift such that the phase changes during the time (data timing interval) required for detecting a correlation pulse is not considered. Tracking is not possible, especially in mobile satellite communications, and when subject to the Doppler effect due to mobile station or satellite position fluctuations, a frequency shift may occur, and this tracking failure may occur frequently. is there.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and has as its object to shorten initial acquisition time, reduce tracking failure due to frequency fluctuation, reliably establish synchronization, and track. It is an object of the present invention to provide a receiver for spread spectrum (SS) communication capable of performing the above.

[0018]

According to a first aspect of the present invention, there is provided a receiving apparatus for spread spectrum communication.
Local for converting received signal to baseband signal
A VCO that outputs a signal, and is converted to a baseband signal.
The correlation between the one-chip differential detection output of the received signal and the PN sequence is established, timing synchronization is established, and a baseband signal is converted into a baseband signal in accordance with a correlation receiver for providing data timing and a data timing provided from the correlation receiver.
The received signal and the PN sequence are correlated, and the oscillation frequency of the VCO is feedback-controlled based on the obtained correlation value.
And a frequency control unit that establishes frequency synchronization.

According to a second aspect of the present invention, there is provided a receiving apparatus for spread spectrum communication according to the first aspect of the present invention, wherein the delay circuit delays a received signal by one chip. A multiplier for multiplying the received signal by the time-delayed received signal to perform delay detection of the received signal; and a PN-sequence differential sequence for correlation between the multiplier output and the PN-sequence differential sequence. A multiplier that calculates while shifting the generation timing, an integration discharge filter, and a determination unit that establishes synchronization of data timing by comparing a correlation value with the multiplier output PN sequence with a predetermined threshold value. It is characterized by having a correlation receiver configured.

In order to achieve the above object, a spread spectrum communication receiving apparatus according to a third aspect of the present invention is the spread spectrum communication receiving apparatus according to the first aspect, wherein the delay circuit delays a received signal by one chip time. A multiplier for multiplying the received signal by the time-delayed received signal and performing delay detection of the received signal;
A matched filter that uses N differential sequences as a reference sequence, a cyclic adder that performs a cyclic addition of the matched filter output for each output data at a data timing cycle, and a maximum determination for determining a maximum value from the cyclic adder output And a correlation receiver comprising:

According to another aspect of the present invention, there is provided a receiver for spread spectrum communication, comprising:
Output local signal to convert to baseband signal
And a received signal converted into a baseband signal
And a correlation receiver for tracking the data timing by taking a correlation between the one-chip differential detection output and the PN sequence, and a base station according to the data timing given from the correlation receiver.
A multiplier for multiplying the received signal converted to the received signal and the PN code, an integration discharge filter for demodulating data from the multiplication result, and a sine wave and a cosine wave having a small positive and negative frequency in the multiplication result. Multiplying and integrating to obtain positive and negative frequency correlation, and from the frequency correlation result, the oscillation frequency of the VCO
AF that performs frequency synchronous tracking by feedback control of
C section .

According to a fifth aspect of the present invention, there is provided a receiver for spread spectrum communication according to the fourth aspect, further comprising a delay circuit for delaying a received signal by one chip time. A multiplier for multiplying the received signal by the time-delayed received signal and performing delay detection of the received signal; a shift register for slightly shifting the timing of the differential sequence of the PN sequence back and forth; A multiplier and an integration discharge filter for respectively correlating the output of the multiplier with the differential sequence whose timing is slightly shifted back and forth; an adder for obtaining a difference between outputs of the integration discharge filter; and an output of the adder. And a correlation filter for tracking data timing based on the output of the loop filter. .

According to a sixth aspect of the present invention, there is provided a receiving apparatus for spread spectrum communication according to the fourth aspect of the present invention.
The correlation receiver described above is characterized in that the data timing is tracked so that the timing at which the maximum correlation value is given is at a fixed location.

Further, in order to achieve the above object, a spread spectrum communication receiver according to claim 7, wherein the received signal
Output local signal to convert to baseband signal
Means for integrating a VCO, a multiplication signal of a pseudo-noise code generated at a predetermined data timing and a reception signal converted to a baseband signal, and averaging the integration result according to a predetermined averaging parameter ; Output and predetermined
Compare with the threshold value, and if it is less than the threshold value,
Shifts the data timing of the
If the average value is greater than the
Value and feed the oscillation frequency of the VCO
Back control means .

According to another aspect of the present invention, there is provided a receiver for spread spectrum communication, comprising the steps of:
Output local signal to convert to baseband signal
To VCO, pseudo-noise code for pilot signal generated at predetermined data timing, and baseband signal
Means for integrating the multiplied signal with the received signal, and averaging the integration result according to a predetermined averaging parameter ;
The averaged output is compared with a predetermined threshold.
In some cases, the current data timing is
Shift, and if it is equal to or greater than the threshold,
Oscillation of the VCO by sequentially changing parameters and thresholds
Means for feedback-controlling the frequency .

[0026]

In the receiving apparatus for SS communication according to any one of the first to sixth aspects, the detection of the PN code in chip units is performed by the delay circuit. Time synchronization. Then, the frequency search is performed in synchronization with the time and the data is demodulated, so that the initial acquisition time can be reduced.

In the receiving apparatus for SS communication according to the seventh and eighth aspects, an averaging time (mean parameter) and a threshold value according to the averaging time are set.
If the current data timing is not correct by comparison with the threshold value, fine tuning of the frequency is not performed. If the current data timing is equal to or greater than the threshold value, it is determined that the data timing may be correct, and the averaging time (and Since the frequency control is performed by changing the threshold value, the fine adjustment of the redundant frequency can be omitted, and the search can be completed in a short time.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of an SS receiving apparatus according to the present invention will be described below with reference to the drawings. In the embodiment, both data modulation and spread modulation are BPSK (two-phase modulation).

First Embodiment <At Initial Capture> FIG. 1 shows the configuration of a first embodiment of the present invention. The SS signal received by the antenna is divided into two orthogonal local signals prepared on the receiving side (a signal from the VCO 100 and a signal obtained by phase-shifting this signal by π / 2 by the phase shifter 102) and a low-pass filter (LPF). After being converted to a baseband signal, the signal is supplied to the correlation receiver 104.
The correlation receiver 104 performs delay detection as described later and outputs a data timing signal. Then, the data timing signal is supplied to the PN generator 106, and a PN code is generated at the obtained timing, and is multiplied by the SS signal by the multiplier. The multiplied signal is integrated discharge filter circuit (I &
After being integrated and discharged at the data timing interval in D), it is squared by the squarer 108, and the I component and the Q component are added by the adder and supplied to the frequency control unit 110. The frequency control unit 110 compares the input signal level with a predetermined threshold level, and supplies a control signal to the VCO 100 so that the level becomes equal to or higher than the threshold value, thereby achieving frequency synchronization.

Although not shown in the drawing, when digital processing is performed, for example, low-pass filter outputs are converted into digital signals by A / D converters.

FIG. 2 shows a correlation receiver 10 according to this embodiment.
4 are shown. The correlation receiver 104 includes a one-chip delay circuit 104a, a multiplier 104b, and a correlator 104d.
And a part of the received SS signal converted to the baseband is supplied to the one-chip delay circuit 104a. The one-chip delay circuit 104a delays the input signal by one chip and supplies the delayed signal to the multiplier 104b. Multiplier 104
In b, the multiplication of the undelayed SS signal and the one-chip-delayed SS signal is performed and supplied to the correlator 104d. The correlator 104d multiplies a PN differential sequence prepared in advance by an input signal (delay detection) as described later, and outputs a correlation pulse.

FIGS. 3 and 4 show a specific configuration of the correlator 104d. FIG. 3 shows a case where a matched filter is used, and FIG. 4 shows a case where a sliding correlator is used. First, in FIG. 3, the differential detection output from the multiplier 104b is sequentially stored in the register 105a. On the other hand, a series having a PN code differential is output from the coefficient generator 105b, multiplied by a multiplier for each chip, and the sum is calculated by the adder 105c. When the timing of the differential detection output coincides with the timing of the differential sequence of the PN code, the output pulse from the adder 105c becomes maximum, and this correlation pulse is output as data timing.

It should be noted here that, in this embodiment, since the correlation pulse is output using the delayed detection output for each chip, the influence of the frequency rotation between chips due to the frequency difference between the transmitted and received carrier waves. In addition, the data timing can be obtained with little influence of the phase difference between the transmission and reception carriers. When the delay detection is performed as described above, there is a possibility that the influence of noise may be more strongly affected. However, it is possible to eliminate the influence of noise by using a cyclic adder or the like. Also in the configuration of FIG. 3, the output pulse from the adder 105c is supplied to the cyclic adder 105d, and is sequentially added to the previous data after performing predetermined weighting for each PN cycle. After several additions, the probability of the addition result being maximum corresponding to the matched pulse increases, and data timing can be obtained. Although FIG. 3 shows the case where the delay detection output is input every one chip time, the same configuration can be realized when the delay detection output is input every 1/2 chip time. In that case, the shift register 105a
Is shifted every half chip time and the coefficient generator 105b
Are obtained by repeating the same differential series twice.

On the other hand, in FIG. 4, the delayed detection output from the multiplier 104b is multiplied by the differential sequence of the PN code by the multiplier, and then supplied to the integration discharge filter (I & D) 105e. As shown in FIG. 5, the differential sequence of the PN code can be obtained by delaying the PN code sequence from the PN generator by one chip using a delay circuit and multiplying the result. In the integrating discharge filter 105e, the multiplication result is, for example, 1
The PN cycle time is integrated, the integrated energy is discharged, the output is sampled, and supplied to the averaging circuit 105f.
The averaged output is compared with a predetermined threshold value by a determination unit 105g. If the averaged output is equal to or less than the threshold value, the PN code differential sequence generation unit 105h is instructed to shift the generation timing of the differential sequence. Then, the timing search is continued, and if it is equal to or larger than the threshold, a data timing signal is output.
Even when this integration discharge filter is used, the correlation between the one-chip differential detection output and the differential sequence of the PN code is calculated as in the case of using the above-described matched filter. The data timing can be reliably obtained without being affected.

<At the time of tracking> FIG. 6 shows a circuit configuration for tracking. As described above, the correlation receiver 104 calculates the correlation between the differential detection output and the differential sequence of the PN code, and outputs a data timing signal. Then, a PN code is generated at this timing, and is multiplied by the SS signal by the multiplier. At the time of initial acquisition, after squaring as shown in FIG. 1, the frequency control unit 110 compares the square with a predetermined threshold. At the time of tracking, the I component and Q component from the multiplier are AFC (Automatic Automatic). Frequency
Control) section 107.

The AFC unit 107 multiplies each of the I component and the Q component by a cosine wave of a minute frequency Δf given from the oscillator 107a and a sine wave shifted by π / 2 by the phase shifter 107b in the multipliers 107c to 107f. , Adders / subtractors 107g to 107j add / subtract the results of the multiplication in the combinations shown in the figure, and perform integration discharges of the respective addition / subtraction results in integration discharge filters 107k to 107n according to data timing. Squared with 107r, 2
The outputs of the multipliers are added by the adders 107s and 107t, the respective addition results are added with the polarity indicated by the adder 107u, and the addition results are averaged via the loop filter 107v, and the averaging result becomes zero. Thus, the VCO 100 is controlled to track the frequency fluctuation. This method utilizes the property that the magnitude of the correlation pulse decreases with the amount of frequency difference. A positive and negative frequency difference is generated between the cosine wave and the sine wave, and the frequency is adjusted so that the difference between the two becomes zero. This is a control method, and is a method similar to a data timing tracking method using a DLL. The output of the adder 107 s has a positive frequency difference,
A correlation pulse having a negative frequency difference is output to the adder 107t.

The operation will be described below. Now, it is assumed that the carrier frequency for reception has changed by a small amount fx due to the movement of the moving object or the position change of the satellite. As a result, the received SS signal becomes d (t) PN (t) cos [2π (f
c + fx) t + θ]. Here, d (t) is a data signal, PN (t) is a PN sequence, fc is a carrier frequency, and θ is an arbitrary phase defined by [0, 2π].

The product of the output of the VCO 100 and the received SS signal is: d (t) PN (t) cos [2π (fc + fx) t + θ] cos [2πfct] = (1/2) d (t) PN (t) ) {Cos [2.2π (fc + fx) t + θ] + cos (2πfxt + θ)}. Then, harmonic components are removed by the LPF, and (1/2) d (t) PN (t) cos (2πfxt + θ) is obtained. Similarly, by multiplying the received SS signal and the output of the π / 2 phase shifter 102 and removing a harmonic component by an LPF, (1/2) d (t) PN (t) sin (2πfxt + θ) is obtained. . When the timing of the PN code is held by the timing tracking system, the generation timing of the PN code generator 106 is the same as the timing of the received SS signal,
The I and Q components of the multiplier output are (1 /
2) d (t) cosX and (1/2) d (t) sinX are input to the AFC unit 107. Here, X = 2πfxt
+ Θ.

Next, let φ be an arbitrary phase defined by [0, 2π], and let the cosine wave given by the oscillator 107a be c
os (2πΔft + φ) = cosY, and the sine wave given by the phase shifter 107b is sin (2πΔft + φ) = si
If nY, multipliers 107c, 107d, 107e,
The 107f outputs are sinXcosY and sin, respectively.
XsinY, cosXsinY, and cosXcosY are output. Therefore, by performing addition and subtraction as determined in the figure, the addition and subtraction units 107g, 107h, 107i, 1
As the 07j output, sinXcosY−cosXsinY = sin (XY) = sin [2π (fx−Δf) t + θ−φ], cosXcosY + sinXsinY = cos (XY) = cos [2π (fx − Δf) t + θ−φ], sinXcosY + cosXsinY = sin (X + Y) = sin [2π (fx + Δf) t + θ + φ], cosXcosY−sinXsinY = cos (X + Y) = cos [2π (fx + Δf) t + θ + φ]. The integration discharge filter performs an integration operation to obtain a correlation value from the product of PN,
The influence of the phase terms (θ−φ) and (θ + φ) is removed by the multiplier. It should be noted that the influence of the phase is removed by s
According to the relationship of in ² A + cos ² A = 1. Therefore, a component corresponding to the correlation power related to the frequency of the difference from which the influence of the phase (θ−φ) has been removed is obtained from the output of the adder 107 s, and the influence of the phase (θ + φ) is also removed to the adder 107 t. A component corresponding to the correlation power related to the frequency of the sum is obtained. Since the magnitude of the correlation pulse decreases with the frequency difference, if fx is positive, the value of the adder 107e becomes larger and the value of the adder 107u becomes negative. Conversely f
If x is negative, adder 107u is positive. Also, f
If x is zero, the value of the adder 107u is also zero. A
The FC unit 107 operates to cancel the fluctuation of the frequency difference in this way.

The correlator 104d of the correlation receiver 104
When the integrating discharge filter shown in FIG.
At the time of data timing tracking, as shown in FIG. 7, the delay detection output is divided into two systems, each of which is integrated and detected by an integration discharge filter, and one is inverted and added, so that the output of the loop filter becomes zero. The configuration may be such that the generation timing of the code differential sequence is adjusted. For example, 105i is a differential sequence at a timing 1/2 chip time earlier than the data timing, and 105j is a differential sequence at a timing 1/2 chip time later than the data timing.

Although not shown in the figure, the phase difference between the transmitted and received carrier waves is detected by, for example, the arctangent function (tan ^-1 ) from the integrated discharge filter output of each of I and Q in FIG. Is controlled by controlling the VCO 100 so that the phase difference becomes 0. If the phase difference is 0, data demodulation can be performed by determining the polarity of the matched pulse of the output of the I-side integrating discharge filter shown in FIG. Become.

In this embodiment, a case is described in which a PN code is used which does not necessarily satisfy the Cycle and Add characteristics. However, when the Cycle and Add characteristics are satisfied,
It goes without saying that the circuit is further simplified by utilizing this characteristic.

Second Embodiment FIG. 8 shows a circuit configuration of a second embodiment. Receive S
The S signal is converted into two orthogonal local signals (a signal from the VCO 200 and a signal obtained by phase-shifting this signal by π / 2 by the phase shifter 202) and a baseband signal by the LPF, and both the I and Q components are AFC mean. It is supplied to the unit 204. Although not shown in the figure, when digital processing is performed, for example, each of the LPF outputs is converted into a digital signal by an A / D converter. The AFC mean section 204 outputs a demodulated data symbol using a PN code, as described later, and detects a correlation pulse P0 for capturing data timing and supplies it to the processor 206. Further, the phase difference is detected using a loop filter, and the VCO 200 is controlled so that the phase difference becomes zero. on the other hand,
The I and Q components are also supplied to the timing section 208. In the timing section 208, the correlation pulses PΔ and P− are expressed by a PNΔ ( or PN2Δ ) code and a PN−Δ ( or PN−2Δ ) code in which the timing of the PN code is shifted by Δ (or 2Δ) and −Δ (or −2Δ). Δ is detected and supplied to the processor 206. The processor 206 compares the input correlation pulses P0, PΔ, P-Δ with a predetermined threshold value, detects a data timing signal, and detects a mean used by the AFC mean unit 204.
Adjust the parameters as appropriate and output. Processor 206
The data timing signal obtained by
0, and at this timing, the PN code generator 212
Generates a PN code, and outputs PN2Δ, PNΔ, PN-Δ, and PN-2Δ for parallel search. In this embodiment, Δ = Tc / 2 (Tc: one chip cycle) is set.

FIG. 9 shows the AFC mean section 20 of this embodiment.
4 is shown. The PN code from the PN code generator 212 and the I and Q components of the SS signal are multiplied by a multiplier and supplied to the integration discharge filter 204a. The integration discharge filter 204a integrates the input multiplication result over the data timing interval and detects the energy. The output from the integration discharge filter 204a is the squarer 20
4b squared and added, mean3 part (averaging part)
204c. The mean3 unit performs averaging processing of the correlation pulse using the mean parameter 3 supplied from the processor 206, and sets P0 as the processor 2
06. On the other hand, a signal obtained by multiplying the PN code and the I and Q components of the SS signal by a multiplier is a mean1 part (averaging part).
204d. The mean1 unit 204d performs an averaging process using the mean parameter 1 supplied from the processor 206, and supplies the result to the phase calculation unit 204e. The phase calculator 204e calculates tan ^-1 (Q / I), detects the phase difference θ, and calculates the phase difference θ.
And the averaging time (mean parameter 1)
The phase amount per hit (that is, the frequency correction amount) is calculated by differentiator 204.
g and output the frequency control signal to VCO2
00 is controlled.

FIG. 10 shows the timing section 208 of this embodiment.
Is shown. PNΔ (or PN2Δ) signal from PN code generator 212 and I and Q of SS signal
The PN-Δ (or PN-2Δ) from the PN generator 212 and the I and Q components of the SS signal are multiplied by a multiplier and supplied to the integration discharge filter 208a. The output from the integration discharge filter 208a is squared by a squarer and mea
The signal is supplied to an n3 unit (averaging unit) 208c. This mea
The n3 unit 208c is the me of the AFC mean unit 204 described above.
An average process of correlation pulses is performed using the mean parameter 3 supplied from the processor 206 in the same manner as in the an3 unit 204c.
06 and supplies the difference to the processor 206 as an output DLL for a delay locked loop.

Incidentally, the above-described mean1 part, mean3
As shown in FIG. 11, the section includes a cyclic adder (A), a low-pass filter LPF or a loop filter such as a lag-lead filter (B), and an integral discharge filter I & D (C).
Or any combination of them as appropriate (m
The mean1 part can use a cyclic adder, and the mean3 part can use an integrating discharge filter.

The receiving apparatus for SS communication according to the present embodiment has the above-described configuration, and the operation thereof will be described below in detail with reference to the flowcharts of FIGS. First, the processor 206 determines the mean parameter used in the AFC mean section 204 and the timing section 208, that is, the mean parameter.
Parameter 1 and mean parameter 3 are set to appropriate values (mp1 (1), mp3 (1), respectively), and the band of the loop filter is set to a predetermined width B1 (S1).
101). Further, the code used in the timing section 208, that is, the PN code is set to PN-2Δ and PN2Δ (S
102). Next, the data timing is set to T0 (S
103). At this time, the operation of the DLL is stopped,
Do not change data timing at DLL output. Then, the correlation pulse output P0 supplied from the AFC mean section 204 and the timing section 208 under this initial setting condition.
Waits until the correlation pulse outputs PΔ and P−Δ supplied from are determined, respectively, and after the determination, proceeds to the following processing to perform a parallel search.

First, the respective outputs P0, PΔ, P-Δ
Is compared with a first threshold value S1 (S104, S104
105, S106). This threshold value is set according to the above-described mean parameter 1 and mean parameter 3. If the outputs P0, PΔ, and P−Δ are all equal to or smaller than the threshold value S1, the timing T is shifted to T + 2Δ, and the same comparison is performed again (S107). This timing shift is continued until any of the outputs exceeds the threshold value. If any of the outputs exceeds the threshold value S1, the mean parameter 1 is set to the initial setting mp1 (1)
Is changed to mp1 (2) (S108). As described above, the mean parameter 1 is a parameter that gives a time for averaging the I and Q components of the SS signal and a time constant for differentiating the detected phase difference in order to determine the frequency control amount in the AFC mean unit 204. It is. Therefore, m
When the ean parameter 1 is small, it is weak to noise but reacts quickly to frequency offset, and when it is large, it converges almost to the optimum value when there is no frequency offset, but reacts to frequency offset. Has the characteristic of being slow. Therefore, when one of the outputs is equal to or greater than the threshold value S1, the mean parameter 1
Is changed from mp1 (1) to mp1 (2) which is larger than mp1 (1) (that is, mp1 (1) <mp1 (2)), it is possible to perform fine adjustment of the frequency that takes a long time.

Then, as described above, the mean parameter 1
Is changed to mp1 (2), the parallel search is performed again, and the outputs P0, PΔ, P−Δ are compared with the threshold value. In addition,
Since the mean parameter 1 has been changed to a large value,
The threshold value to be compared with the output is also changed from S1 to a larger second threshold value S2 (S1 <S2) for comparison (S1).
109, S110, S111). If none of the outputs exceed the threshold value S2, the mean parameter 1 is set to mp
Returning to 1 (1) (S112), the process returns to S107 and the data timing is stepped to perform a search at the next timing. If the output exceeds the threshold value, it is determined that acquisition (synchronization establishment) has been completed, and the data timing T
Is set to the timing at that time (S113, S11
4) The operation of the timing section 208 is switched from the parallel search mode to the DLL mode to perform synchronous tracking. That is, the PN code used in the timing section 208 is PN-Δ,
PNΔ (S115), the DLL output, that is, FIG.
The data timing T is controlled so that the difference ([PΔ] − [P−Δ]) of the correlation pulse output from the mean unit 208c at 0 becomes 0 (S116). In the tracking mode, first, in S117 to S121, it is determined whether the correlation pulse output P0 still has a value equal to or larger than the threshold value S2, and the values of the mean parameter 1 and the mean parameter 3 are increased to a larger value mp1 (3 ) And mp3 (2). This is a process for surely performing the initial pull-in operation of the DLL. Note that a method of providing a timer and repeating a loop may be used for S117 to S120. Further, the band of the loop filter is changed from B1 to B2 (S12).
2). Here, the characteristics of the mean parameter 1 are as described above, but the mean parameter 3 is a parameter that gives an averaging time for obtaining the outputs PΔ and P−Δ from the data timing unit 208. Therefore, when the mean parameter 3 is small, it reacts quickly to the data timing deviation, but is easily affected by noise.
Conversely, when the mean parameter 3 is large, it converges almost to the optimum value if there is no data timing shift.
It has a characteristic that it responds slowly to timing deviation. Therefore, by changing the mean parameter 3 to a large value in this manner, highly accurate tracking can be performed.

Then, the threshold value is changed to the third threshold value which is larger than that of the mean parameters 1 and 3 (S2 <S3), and is compared with the correlation output P0 (S2).
123-S128). As long as the correlation output P0 is equal to or larger than the threshold value, it is determined that tracking is being performed, and the DLL operation is continued. On the other hand, if the correlation output P0 becomes equal to or less than the threshold value, it is determined that tracking is difficult. In this embodiment, however, it is not immediately determined that tracking is not possible. Has been determined. That is, the value of the mean parameter 1 is changed to mp1 in S124.
When the value of (3) is changed to mp1 (2), and the value of the mean parameter 3 is changed from mp3 (2) to mp3 (1). Continues the tracking, and the mean parameters 1 and 3
Is not tracked even if the value of the threshold value or more is not obtained even with mp1 (2) and mp3 (1), that is, if the output is not more than the correlation output at the time of completion of the above-mentioned acquisition, it is determined that tracking is impossible, and Redo the process from the captured.

As described above, in this embodiment, a plurality of mean
Acquisition and tracking are performed by appropriately changing parameters and thresholds, and when the initially set timing may be correct, fine adjustment is made to change the value of the mean parameter and remove the frequency offset for the first time. So do
The initial acquisition time can be shortened and tracking can be performed reliably.

Third Embodiment The second embodiment exemplifies a case in which a data-modulated SS signal is captured and tracked from the transmitting side (base station).
It is also conceivable that the base station side may simultaneously transmit a pilot signal which is not subjected to data modulation only of spread modulation and has the same frequency and the same timing as the data signal. FIG.
FIGS. 15 and 16 show the reception and acquisition of the pilot signal,
FIG. 14 shows the overall configuration, and FIGS. 15 and 16 show AFCm in FIG. 14 respectively.
This is the configuration of the ean section and the configuration of the timing section. These configurations are different from the above-described configurations of capturing and tracking the data signal (FIGS. 8, 9 and 10) in that the integration discharge filter 204a of the AFC mean section is changed to a mean 2 section that performs averaging processing with a mean parameter of 2. Points, a data spreading code generator 305 for obtaining demodulated data, and an integrating discharge filter 306 separately, and an AFC mean section and a mean 3 section 20 for averaging in a timing section.
4c does not exist (averaging is performed only in the mean2 part).

That is, the received SS signal is converted into two orthogonal local signals (a signal from the VCO 200 and a signal obtained by phase-shifting the signal by π / 2 by the phase shifter 202) and a baseband signal by the LPF. , And Q are supplied to the AFC mean section 300. Although not shown in the drawing, when digital processing is performed, for example, low-pass filter outputs are converted into digital signals by A / D converters. The AFC mean unit 300 detects a correlation pulse P0 for capturing data timing by using a pilot PN code as described later and supplies it to the processor 302. Further, the phase difference is detected using a loop filter, and the VCO 200 is controlled so that the phase difference becomes zero. On the other hand, both the I and Q components are also supplied to the timing section 304. The timing unit 304 shifts the timing of the pilot PN code by Δ (or 2Δ) and −Δ (or −2Δ) to PNΔ ( or PN2).
Δ ) code and PN-Δ ( or PN-2Δ ) code to detect correlation pulses PΔ and P-Δ and supply them to the processor 302. In the processor 302, the input correlation pulse P
0, PΔ, and P−Δ are compared with a predetermined threshold, and AFCm
The mean parameter used in the mean section 300 is appropriately adjusted and output. The data timing signal obtained by the processor 302 is supplied to a clock controller 210. At this timing, a PN code is generated from a PN code generator 212, and PN2Δ, PN for parallel search is generated.
Δ, PN−Δ, and PN−2Δ are output.

FIG. 15 shows a circuit configuration of the AFCmean unit 300.
The sign and the I and Q components of the SS signal are multiplied by a multiplier, and
It is supplied to the n2 part 300a. In the mean2 part, an averaging process is performed using the mean parameter 2 supplied from the processor 302, and further squared by the squarer 204b to obtain I,
The Q component is added and supplied to the processor 302 as P0. On the other hand, a signal obtained by multiplying the PN code and the I and Q components of the SS signal by a multiplier is supplied to a mean1 unit (averaging unit) 300c. In the mean1 unit 300c, the processor 30
An averaging process is performed using the mean parameter 1 supplied from 2 and supplied to the phase calculator 300d. The phase calculation unit 300d calculates tan-1 (Q / I), detects the phase difference θ, supplies the phase difference θ to the loop filter 300e, and furthermore, calculates the phase amount per averaging time (mean parameter 1) (ie, frequency correction). Is calculated by the differentiator 300f to control the VCO 200.

FIG. 16 shows a circuit configuration of the timing section 304, and the PN Δ from the PN code generator 212 is shown.
(Or PN2Δ) code and the I and Q components of the SS signal, and PN-Δ (or PN-2) from the PN generator 212.
Δ) and the I and Q components of the SS signal are multiplied by a multiplier.
It is supplied to the n2 unit 304a. The output from the mean2 unit 304a is squared by the squarer 304b, and P-Δ,
The difference is supplied to the processor 302 as PΔ, and the difference is supplied to the processor 302 as an output DLL for a delay locked loop. In addition, as the mean2 part, FIG.
One of the averaging means (A), (B), and (C) shown in FIG. 1 can be used.

As compared with the second embodiment, the integration discharge filter 2
Means 04a and 208b each perform averaging processing
It has been changed to two parts 300a and 304a,
This is caused by performing a correlation process on a pilot signal not subjected to data modulation. That is, if the averaging time is 1 data time or more for a signal that is subjected to data modulation, even if the timings match and there is a correlation,
The averaged output may become zero due to data polarity inversion, but if data modulation is not applied, there is no data polarity inversion, so there is no need to perform the integration time in data timing units, providing more flexibility. By performing averaging over one data time or more, the averaging operation after the squaring operation can be performed in this portion in advance, so that the circuit scale can be reduced.

Since the mean parameter 1 is a parameter relating to establishment and tracking of frequency synchronization, a parameter corresponding to a time shorter than one data time is assumed.

Hereinafter, a processing method for capturing and tracking a pilot signal with such a configuration will be described in detail with reference to the flowcharts of FIGS. First, the processor 30
2 is a mean parameter used in the AFC mean unit 300 and the timing unit 304, that is, mean parameters 1 and 2 are set to appropriate values (mp1 (1) and mp2, respectively).
(1)) is set (S201). The code used in the timing unit 304, that is, the PN code is PN-2Δ,
PN2Δ is set (S202). Next, the data timing is set to T0 (S203). At this time, D
The operation of the LL is stopped, and the data timing is not changed by the output of the DLL. And under this initial setting condition, AFC
The correlation pulse output P0 supplied from the mean unit 300 and the correlation pulse output P supplied from the timing unit 304
Wait until Δ and P−Δ are determined, and after the determination, proceed to the following processing to perform parallel search.

First, the respective outputs P0, PΔ, P-Δ
Is compared with a predetermined first threshold value S1 (S204, S
205, S206). This threshold value is set according to the above-described mean parameter 1 and mean parameter 2. If the outputs P0, PΔ, and P−Δ are all equal to or smaller than the threshold value S1, the timing T is shifted to T + 2Δ, and the same comparison is performed again (S207). This timing shift is continued until any of the outputs exceeds the threshold value. If any of the outputs exceeds the threshold value S1, the mean parameter 1 is set to the initial setting mp1 (1)
Is changed to mp1 (2) (S208). The relationship between the mean parameter 1 and the response and convergence corresponding to the frequency offset is the same as in the second embodiment.

Then, as described above, the mean parameter 1
Is changed to mp1 (2), the parallel search is performed again, and the outputs P0, PΔ, P−Δ are compared with the threshold value. In addition,
Since the mean parameter 1 has been changed to a large value,
The threshold value to be compared with the output is also changed from S1 to a larger second threshold value S2 (S1 <S2) for comparison (S1).
209, S210, S211). If none of the outputs exceed the threshold value S2, the mean parameter 1 is set to mp
The process returns to 1 (1) (S212), and the process returns to S207 to step the data timing and search at the next timing. If the output exceeds the threshold value, it is determined that acquisition (synchronization establishment) has been completed, and the data timing T
Is set to the timing at that time (S213, S21
4) The operation of the timing section 304 is switched from the parallel search mode to the DLL mode to perform tracking. That is,
The PN code used in the timing section 304 is PN-Δ, PN
It is set to Δ (S215), and the data timing T is controlled so that the difference between the DLL output, that is, the correlation pulse output ([PΔ] − [P−Δ]) becomes 0 (S216). In the synchronous tracking mode, first, in S217 to S221, it is determined whether or not the correlation pulse output P0 still has a value equal to or larger than the threshold value S2.
Increase the value of the an parameter 2 to a larger value mp1 (3), m
Change to p2 (2). These are processes for reliably performing the DLL pull-in operation. The operation of S217 to S220 may be a method of providing a timer and repeating the loop for a predetermined time. The characteristics of the mean parameter 1 are as described above. On the other hand, when the mean parameter 2 is small, it reacts quickly to the data timing deviation, but is easily affected by noise, and conversely, the mean parameter 2 is large. In this case, the data almost converges to the optimum value if there is no data timing deviation, but the characteristic is that the response to the timing deviation is slow. Therefore, by changing the mean parameter 2 to a large value, it becomes possible to perform highly accurate tracking.

Then, the threshold value is changed to a third threshold value which is larger than that of the mean parameters 1 and 2 (S2 <S3) and compared with the correlation output P0 (S2).
223). As long as the correlation output P0 is equal to or larger than the threshold value, it is determined that tracking is being performed, and the DLL operation is continued. On the other hand, when the correlation output P0 becomes equal to or less than the threshold value, it is determined that tracking is difficult.
It is determined whether or not the tracking can be continued by gradually decreasing the mean parameter (S224 to S228). That is,
In S224, the value of the mean parameter 1 is changed from mp1 (3) to mp1 (2), and the mean parameter 2 is changed to mp1 (2).
After changing to 2 (1) and comparing with the threshold value S3 or S2 again, if the value is equal to or more than the threshold value, the tracking is continued and m
ean parameters 1 and 2 are mp1 (2), mp
If a value equal to or larger than the threshold value is not obtained even in 2 (1), that is, if only an output less than or equal to the correlation output at the time of completion of the above-described acquisition is obtained, it is determined that tracking is impossible, and the processing is repeated from the above-described acquisition.

As described above, in the case of a pilot signal, there is no polarity inversion (BPSK) in data units, and when the timings match, the product of the received SS signal and the PN code has the same polarity. It is not necessary to perform averaging processing like a data signal after performing squaring processing by a squaring device, and capture and tracking can be performed with a simpler configuration. As for data demodulation, it is possible to perform despreading using a spreading code for data in accordance with a given timing, and obtain a demodulated data symbol from the polarity of the correlation pulse. In the embodiment, both BP and BP are used for data modulation and spread modulation.
Although the case of SK has been shown, one or both of them are QPS
Even in the case of K modulation, it can be easily extended by considering the polarity of the spreading code or the correlation pulse.

[0063]

As described above, the SS according to the present invention is
According to the communication receiver, the initial acquisition time can be significantly reduced, and the demodulation of information data can be performed with good tracking even for a carrier frequency shift.

[Brief description of the drawings]

FIG. 1 is a configuration block diagram of a first embodiment of the present invention.

FIG. 2 is a configuration block diagram of a correlation receiver of the embodiment.

FIG. 3 is a block diagram illustrating a configuration of a correlation unit according to the embodiment.

FIG. 4 is a block diagram illustrating another configuration of the correlation unit according to the embodiment.

FIG. 5 is a block diagram showing a configuration of a PN code differential sequence generating circuit according to the embodiment.

FIG. 6 is a configuration block diagram of the embodiment at the time of tracking.

FIG. 7 is a block diagram illustrating a configuration of the correlation unit when tracking according to the embodiment.

FIG. 8 is a configuration block diagram of a second embodiment of the present invention.

FIG. 9 is a block diagram illustrating a configuration of an AFC mean unit of the embodiment.

FIG. 10 is a configuration block diagram of a timing unit of the embodiment.

FIG. 11 is a configuration block diagram of a mean section of the embodiment.

FIG. 12 is an operation flowchart of the embodiment.

FIG. 13 is an operation flowchart of the embodiment.

FIG. 14 is a configuration block diagram of a third embodiment of the present invention.

FIG. 15 is a block diagram illustrating a configuration of an AFC mean unit of the embodiment.

FIG. 16 is a block diagram illustrating a configuration of a timing unit according to the embodiment.

FIG. 17 is an operation flowchart of the embodiment.

FIG. 18 is an operation flowchart of the embodiment.

FIG. 19 is a configuration block diagram of a conventional system.

FIG. 20 is a configuration block diagram of a conventional receiving device.

FIG. 21 is an explanatory diagram of a conventional frequency and timing search.

FIG. 22 is a block diagram showing a configuration at the time of tracking of a receiving apparatus using a conventional matched filter.

FIG. 23 is a configuration diagram of a matched filter.

FIG. 24 is a block diagram showing a configuration of a conventional receiving apparatus using a matched filter at the time of frequency supplementation and tracking.

[Explanation of symbols]

 6 Antenna 15, 106, 212 PN code generator 104 Correlation receiver 204, 300 AFC mean section 206, 302 Processor 208, 304 Timing section

Claims (8)

(57) [Claims] A spread spectrum communication receiving apparatus for receiving a signal spread spectrum by a pseudo noise code by a direct spread method and demodulating information data from the received signal, for converting the received signal into a baseband signal. local
A VCO that outputs a signal and one-chip delay of the received signal converted to a baseband signal
A correlation receiver for obtaining a correlation between the detection output and the PN sequence, establishing timing synchronization, and providing data timing; and a reception signal and a PN sequence converted into a baseband signal according to data timing given from the correlation receiver. And the VCO of the VCO is calculated based on the obtained correlation value .
A frequency control unit that establishes frequency synchronization by feedback-controlling an oscillation frequency , and a receiving device for spread spectrum communication. 2. A delay circuit for delaying a received signal by one chip time; a multiplier for multiplying the received signal by the time-delayed received signal to perform delay detection of the received signal; A multiplier for calculating the correlation with the differential sequence of the series while shifting the generation timing of the differential series of the PN series, an integrating discharge filter, and comparing the correlation value with the output PN series of the multiplier with a predetermined threshold value 2. A receiving apparatus for spread spectrum communication according to claim 1, further comprising a correlation receiver comprising: a determination unit configured to establish synchronization of data timing by performing the determination. 3. A delay circuit for delaying a received signal by one chip time, a multiplier for multiplying the received signal by the time-delayed received signal and performing delay detection of the received signal, and an output of the multiplier. A matched filter that uses a differential sequence of a PN sequence as a reference sequence, a cyclic adder that performs cyclic addition on the output of the matched filter for each output data at a data timing period, and determines a maximum value from the output of the cyclic adder The spread spectrum communication receiver according to claim 1, further comprising a correlation receiver comprising: a maximum determination unit; 4. A spread spectrum communication receiving apparatus for receiving a signal spread spectrum by a direct spreading method by a pseudo noise code and demodulating information data from the received signal, for converting the received signal into a baseband signal. local
A VCO that outputs a signal and one-chip delay of the received signal converted to a baseband signal
A correlation receiver that obtains a correlation between the detection output and the PN sequence and tracks data timing; and multiplies a product of the received signal converted into a baseband signal and a PN code according to the data timing given from the correlation receiver. And an integration discharge filter for demodulating data from the multiplication result, and multiplying and multiplying the multiplication result by a sine wave having a small positive and negative frequency and a cosine wave to obtain a positive and negative frequency correlation, from the frequency correlation result Feedback the oscillation frequency of the VCO
And an AFC section for performing frequency synchronization tracking by controlling the frequency, and a receiving apparatus for spread spectrum communication. 5. A delay circuit for delaying a received signal by one chip time, a multiplier for multiplying the received signal and the time-delayed received signal to perform delay detection of the received signal, and a differential sequence of a PN sequence A shift register for slightly shifting the timing of the timing back and forth; a multiplier and an integration discharge filter for respectively correlating the output of the multiplier with the differential sequence whose timing is shifted slightly forward and backward; And a loop filter for averaging the output of the adder, the correlation receiver comprising: a correlation receiver for tracking data timing by the loop filter output. 5. The receiver for spread spectrum communication according to 4. 6. A spread spectrum apparatus according to claim 4, comprising the correlation receiver according to claim 3, wherein the data timing is tracked such that the timing at which the maximum correlation value is given is at a fixed location. Communication receiver. 7. A spread-spectrum communication receiver for receiving a signal spread spectrum by a pseudo-spread code by a pseudo-noise code and demodulating information data from the received signal, for converting the received signal into a baseband signal. local
A VCO for outputting a signal, the pseudo noise code and base that caused at a predetermined data timing
Multiply the multiplied signal with the received signal
Means for averaging the integration result according to a predetermined averaging parameter ; comparing the averaged output with a predetermined threshold;
If it is less than or equal to the current data timing
Shifts by an interval, and if it is equal to or greater than the threshold,
The VCO by sequentially changing the equalization parameter and the threshold.
Spread spectrum communication receiving apparatus characterized by having a means for feedback controlling the oscillation frequency of the. 8. A spread spectrum communication receiving apparatus for receiving a signal spread spectrum by a direct spreading method by a pseudo noise code and demodulating information data from the received signal, for converting the received signal into a baseband signal. local
A VCO that outputs a signal, a multiplication signal of a pilot signal pseudo-noise code generated at a predetermined data timing and a reception signal converted to a baseband signal are integrated, and the integration result is averaged according to a predetermined averaging parameter. Means for comparing the averaged output with a predetermined threshold value,
If it is less than or equal to the current data timing
Shifts by intervals, and if the threshold is exceeded,
The VC is obtained by sequentially changing the averaging parameter and the threshold value.
Means for feedback controlling the oscillation frequency of the O, spread spectrum communication receiver characterized by having a.