JP2719252B2 - Thin film transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor formed as a switching element on an active matrix substrate used for, for example, a shutter array or a liquid crystal display device.

[0002]

BACKGROUND ART TFT described above, conventionally, FIG
3 (plan view) and FIG. 4 (cross-sectional view along line AA in FIG. 3 )
Is known as shown in FIG. In this thin film transistor, for example, a semiconductor layer 22, a gate insulating film 23, and a gate electrode 24 are formed in this order on a transparent insulating substrate 21, and ion implantation is performed on the semiconductor layer 22 from above using the uppermost gate electrode 24 as a mask. Then, contact regions 22a and 22b having a low impurity concentration distribution are formed. Further, each contact region 22a, 22
A source electrode 25a and a drain electrode 25b are formed from b to the substrate 21. The drain electrode 25b is electrically connected to a picture element electrode (not shown) formed by partially overlapping the drain electrode 25b. Further, a protective film 26 is formed so as to cover the entire surface of the substrate 21.

[0003]

However, the above-mentioned conventional thin film transistor has the following problems. That is, as shown in FIG. 4 , the semiconductor layer 22 and the source electrode 25a are close to each other, except that one end D of the contact layer 22a exists between them. Similarly, the semiconductor layer and the drain electrode 15b are close to each other only because one end E of the contact layer 12b exists between them. For this reason, the source electrode 15
Leakage occurs between a and the drain electrode 15b, making it difficult for the thin film transistor to operate normally.

In particular, recently, as a display device using a liquid crystal or electroluminescence (EL), an HD (H
The development and commercialization of large-capacity, high-density active matrix display devices for high definition (TV), graphic displays, and the like are being promoted. When used, 10 ^-9 to 10 ^-11
In some cases, a leakage current of about A was generated and the device became unusable.

The present invention has been made to solve such a problem, and provides a thin film transistor which can suppress the occurrence of leakage and can be used for an active matrix type display device using a large current. The purpose is to:

[0006]

A thin film transistor according to the present invention comprises a semiconductor layer having at least a contact region and a channel region, a gate insulating film, and a gate electrode laminated on a substrate in this order. A thin film transistor in which a source electrode and a drain electrode are respectively formed in contact with the contact region which is at least partially overlapped on both ends in the width direction of the semiconductor layer wider than the semiconductor layer and is present near the overlapped portion; in, the gate insulating film is opposite side surfaces in a width direction, toward the widthwise length of the gate electrode side of the substrate side widthwise length of the gate insulating film is formed by a short inclined surface, the width of the semiconductor layer One
The contact region at each of the opposite ends
One side in the width direction by ion implantation from the edge film side
The gate insulating film side end of the surface is inclined with respect to the gate insulating film.
It is located below the middle of the side surface, and the other end in the width direction
Is formed with the side face of the semiconductor layer positioned at the end face of the semiconductor layer.
The channel region of the conductor layer is provided below the gate insulating film in the semiconductor layer portion avoiding the contact region, thereby achieving the above object.

[0007]

[0008]

[0009]

[0010]

According to the present invention, the gate insulating film is formed so that the side surfaces on both sides in the width direction are inclined surfaces in which the length in the width direction on the gate electrode side is shorter than the length in the width direction on the substrate side of the gate insulating film. Have been. Therefore, when impurities are implanted from the side of the gate electrode, contact regions at both ends in the width direction of the semiconductor layer are formed.
The region is made semiconductor by ion implantation from the gate insulating film side.
The gate end on the side of the gate insulating film on one side in the layer width direction is the gate.
It is located halfway down the inclined side surface of the insulating film, and
The side surface on the other end side in the conductor layer width direction is located at the end surface of the semiconductor layer.
It can be formed in a bent state .

[0011]

Therefore, since the contact region also exists below the gate insulating film, the thickness of the contact region between the channel region and the source electrode and between the channel region and the drain electrode increases, and the thickness of the contact region increases. As a result, the distance between the channel region and the source electrode and the distance between the channel region and the drain electrode become longer.

[0013]

Embodiments of the present invention will be described below.

(Embodiment 1) FIG. 2 is a plan view showing a part of a thin film transistor of this embodiment, and FIG. 1 is a sectional view taken along line BB of FIG. In this thin film transistor, a semiconductor layer 2, a gate insulating film 3, and a gate electrode 4 are provided in this order on a transparent insulating substrate 1 such as glass. The gate insulating film 3 has a trapezoidal cross section in which the lower width is longer than the upper width, and is formed by inclining both side surfaces 3a, 3b at an inclination angle θ. The electrode 4 is formed such that its lower width is equal to the upper width of the gate insulating film 3. On the other hand, the semiconductor layer 2 existing under the gate insulating film 3 has a width on the upper side longer than the width on the lower side of the gate insulating film 3 and the width in the width direction of the semiconductor layer 2 (BB line). The contact regions 2a and 2b formed by ion-implanting impurities are formed from both ends and below both side surfaces 3a and 3b of the gate insulating film 3. Note that the gate electrode 4 is electrically connected to a gate electrode wiring 7 for transmitting a scanning signal.

The source electrode 5 is divided from the semiconductor layer 2 to the substrate 1 by the gate insulating film 3.
a and a drain electrode 5b are formed, and a picture element electrode (not shown) formed by partially overlapping the drain electrode 5b is electrically connected to the drain electrode 5b. On the other hand, a source electrode wiring 8 for transmitting a source signal is electrically connected to the source electrode 5a. The protective film 6 is formed over the entire surface of the substrate 1 in such a state, and the thin film transistor of this embodiment is configured.

Next, a method of manufacturing the thin film transistor having this structure will be described.

First, as shown in FIG. 1, a semiconductor layer 2 is formed by depositing and patterning amorphous silicon to a thickness of 200 Å to 1500 Å on an insulating substrate 1 such as glass. Next, a gate insulating film 3 made of SiN _x or the like is formed on the semiconductor layer 2.
Is formed in a thickness of 500 Å to 5000 Å in the same manner. At the time of this formation, the side surfaces 3a and 3b of the gate insulating film 3 are formed using a technique of dry etching and wet etching. Side 3
a, 3b are less than 90 °, desirably 10 °
To 70 °, more preferably 30 ° to 50 °.
The point is that, by inclining, the thickness at the lower portion of both side surfaces 3a and 3b is reduced, and the angle is set so that impurities can be ion-implanted also into the semiconductor layer 2 under the both side surfaces 3a and 3b. Note that the inclination angles θ of both side surfaces 3a and 3b may be different from each other.

Next, on the gate insulating film 3, Ta, T
A single-layer or multi-layer metal such as i, Al, Cr or the like is deposited on the gate insulating film by sputtering to a thickness of 2,000 to 4,000 angstroms and patterned to form the gate electrode 4. At the time of patterning, the gate electrode 4 has the same shape and shape as the upper surface of the gate insulating film 3 thereunder.
Make to size.

Next, ions of a group V element or a compound thereof, or an impurity of a group III element or a compound thereof are implanted into the semiconductor layer 2 at an acceleration voltage of 1 kV to 100 kV. Preferably, ion implantation is performed at 10 kV to 50 kV. At this time, the impurity is implanted into a portion of the semiconductor layer 2 not covered with the gate insulating film 3 and a portion of the semiconductor layer 2 covered with the side surfaces 3a and 3b of the gate insulating film 3, so that the contact region is formed. 2a and 2b are formed. Contact
Region 2a is located at one end side in the width direction of the semiconductor layer 2 (FIG.
1 (on the right side of FIG. 1) on the side surface 3a of the gate insulating film 3.
Side surface located at the lower part of the way and on the other end side (left side in FIG. 1)
Is formed on the end face of the semiconductor layer 2. Contour
The contact region 2b is located at one end of the semiconductor layer 2 in the width direction.
The upper end of the side surface (left side in FIG. 1) is placed on the side surface 3 of the gate insulating film 3.
b, and at the other end (right side in FIG. 1)
The side surface is formed at the end face of the semiconductor layer 2. The central portion of the semiconductor layer 2 covered with the gate insulating film 3 is kept in its original state without being doped with impurities, and functions as a channel region. The thickness of the semiconductor layer 2, the gate insulating film 3, and the gate electrode 4 are the same as those of the contact region 2.
It may be determined according to the degree of ion implantation of a and 2b.

Next, a resist film having a reverse taper shape is formed on the gate electrode 4 by dichlorobenzene treatment or the like, and thereafter, Ti, Cr, Mo, Al and the like are deposited in a thickness of 2000 Å to 4000 Å and lifted off. As a result, a source electrode 15a and a drain electrode 15b are formed in predetermined regions on the semiconductor layer 2 and the substrate 1.

Next, a protective film 6 is formed on the entire surface of the substrate 1. Thus, the thin film transistor of the present embodiment shown in FIG. 1 is manufactured.

Therefore, in the thin film transistor manufactured as described above, as shown in FIG.
a and 2b are present. For this reason, between the channel region and the source electrode 5a and between the channel region and the drain electrode 5b are isolated by the presence of the contact regions 2a and 2b into which impurities are implanted at a low concentration, and the source electrode 5a and the drain electrode 5b are separated. Can be suppressed from occurring.

[0023]

[0024]

[0025]

[0026]

[0027]

[0028]

[0029]

[0030]

[0031]

[0032]

[0033]

In the above embodiment, the semiconductor layer 2 is used.
Use amorphous silicon, but 500 ~ 20
00 angstroms of polysilicon may be used.

Further, in the above embodiment, the gate insulating film 3
It was used SiN _X as may be used SiO _2.

[0036]

According to the present invention, since a contact region in which an impurity is implanted also exists under the gate insulating film, the leakage current generated between the source electrode and the drain electrode is reduced by about one to two digits. It is possible to suppress the occurrence of leakage, and as a result, the present invention can be applied to an active matrix display device requiring a large current. Further, according to the present invention, the inclination of the gate insulating film is reduced.
By adjusting the angle of inclination of the inclined side, contact
It is also possible to control the position of one end of the
The length of the channel region, that is, the channel length
Can be performed frequently.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view (a cross-sectional view taken along line BB of FIG. 2) showing a thin film transistor of the present embodiment.

FIG. 2 is a plan view showing the thin film transistor of FIG.

FIG. 3 is a plan view showing a conventional thin film transistor.

FIG. 4 is a sectional view taken along line AA of FIG . 3 ;

[Description of Signs] 1 Insulating substrate 2 Semiconductor layer (channel region) 2a Contact region 2b Contact region 3 Gate insulating film 3a, 3b Side surface 4 Gate electrode 5a Source electrode 5b Drain electrode 6 Protective film

 ──────────────────────────────────────────────────続 き Continuation of front page (72) Inventor Hiroshi Morimoto 22-22 Nagaikecho, Abeno-ku, Osaka City Inside Sharpe Co., Ltd. (56) References JP-A-61-224360 (JP, A) JP-A-2-159730 (JP, A) JP-A-60-55665 (JP, A) JP-A-1-125866 (JP, A)

Claims (1)

(57) [Claims] A semiconductor layer having at least a contact region and a channel region, a gate insulating film, and a gate electrode are formed in this order on a substrate, and the width of the semiconductor layer is wider than the gate insulating film and the gate electrode. A thin film transistor in which a source electrode and a drain electrode are formed in contact with the contact region which is at least partially overlapped with both end portions in the direction and is present near the overlap portion, wherein the gate insulating film has both sides in the width direction. sides, formed towards the widthwise length of the widthwise length the gate electrode side from the substrate side of the gate insulating film is a short inclined surface, the contact territory in each of widthwise end portions of the semiconductor layer of
The region has the width due to ion implantation from the gate insulating film side.
The gate insulating film side end on one side in the direction
Located below the middle of the inclined side surface of the rim, and
The other side surface in the width direction is positioned at the end surface of the semiconductor layer.
Formed Te, set the semiconductor layer portion in which a channel region of the semiconductor layer is avoided the contact area even under the gate insulating film
It kicked the thin film transistor.