JP2718478B2 - Error correction device for long distance codes - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial application] An error correcting code such as a BCH code or a Reed-Solomon code is used, and a large number of words can be used as one block to correct errors of a large number of words contained in this block. A code having a correction capability is used in an optical disk, data transmission, and the like.

The present invention relates to a long distance code error correction device for decoding a code capable of correcting a large number of errors with one correction sequence (hereinafter, referred to as a long distance code) at a high speed and performing error correction. The present invention relates to a long-distance code error correction device, which was previously filed by Japanese Patent Application No. 62-195240, to further improve and reduce its size.

[Conventional technology]

In order to correct an error in a large number of words using a BCH code, a Reed-Solomon code, or the like, it is necessary to generate a syndrome from received data and obtain a coefficient of an error locator polynomial.

That is, the error locator polynomial is a polynomial having a root corresponding to the value corresponding to the error location, and the data position where the error has occurred can be calculated by calculating the coefficient of each term of the error locator polynomial.

Conventionally, as a method for obtaining the coefficient of such an error locator polynomial, Peterson, Berlekamp Massey, Euclid's mutual division method and the like are known, but any method is a hardware that attempts to realize a circuit by hardware. Problems have arisen, such as not being suitable for miniaturization due to the large amount, and slowing down the processing speed when trying to realize by software.

The present applicant has made Japanese Patent Application No. 62-10
In No. 0169, a data word indicating a syndrome or an error position is set in each element of a matrix, and the matrix of the long-distance code in which a coefficient or an error pattern of each term of an error position polynomial is obtained by subjecting the matrix to a left basic deformation. Filed an error correction system and its device. And
An error correction device which further improved the above and further improved the speed was filed by Japanese Patent Application No. 62-195240. FIG.
The configuration of a long distance code error correction device filed in Japanese Patent Application No. 62-195240 is shown.

Hereinafter, the principle and operation of the device shown in FIG. 7 will be described. A read on a Galois field GF (2 ⁸ ) in which one word is composed of 8 bits and four words can be corrected (t = 4) with 255 words as one block. -An explanation will be given using a Solomon code as an example. The calculation of addition, subtraction, multiplication, and division in the following is all based on the calculation of mod 2.

Now the value of each word of the received data contain errors and r ₀ ~r _254, the reception data R (x) is given by the following equation (1).

R (x) = r ₀ x ²⁵⁴ + r ₁ x ²⁵³ +... + R ₂₅₃ x ¹ + r ₂₅₄ (1) The syndromes S _{0 to} S ₇ generated from the received data are α ^{0 in the} expression (1). , Α ¹ ,..., Α ⁷ are respectively given by the following equations.

On the other hand, the mislocation polynomial σ (x) is defined by the following equation.

σ (x) = (x + V ₁ ) (x + V ₂ ) (x + V ₃ ) (x +
^{_{V 4) = x 4 + σ}} 3 x 3 + σ 2 x 2 + σ 1 x + σ 0 ...... (3) V 1 ~V 4 herein shows the error position, that the word position in error.

Gives an error position polynomial (3) the following equation (4) the relationship is established between the coefficients σ ₀ ~σ ₃ and the syndrome S ₀ to S ₇ of the.

When the shape of the matrix is changed by transposing the right side of the equation (4) to the left side, the following equation (5) is obtained.

Further, when the left basic deformation is performed, the following equation (6) is obtained.

The equation (6) from (3) coefficients σ ₀ ~σ ₃ of formula is obtained as (7) below.

σ ₀ = a ₀ σ ₁ = a ₁ σ ₂ = a ₂ σ ₃ = a ₃ (7) On the other hand, the following relationship is established between the error patterns Y _{1 to} Y ₄ and the syndromes S _{0 to} S _7. I do.

Here, V _{1 to} V ₄ are error positions obtained from equation (3) based on the coefficients σ _{0 to} σ ₃ .

When the form of the matrix is changed by transposing the right side of the equation (8) to the left side, the following equation (9) is obtained.

When the equation (9) is left fundamentally deformed in the same manner as the equation (6), the following is obtained.

As is clear from the equation (10), the error patterns Y _{1 to} Y ₄ can be obtained by the left basic modification of the given matrix in the same manner as the coefficients σ ₀ to σ ₃ .

Here, the left-hand four rows 5 in the equations (5) and (9)
When the matrix of columns is represented by a general formula, it is represented by the following formula (11).

In the equation (11), the diagonal element a _1,1 in the first column is set to “1” by the left basic deformation, and the other elements a _2,1 , a a
When performing a process of transforming _3,1 , a _4,1 into “0”, each element a _1,2 ′, a _2,2 ′, a _3,2 ′, a _4,2 ′
Are determined as follows.

a _1,2 '= a _1,2 ÷ a _1,1 a _2,2 ' = a _1,2 ÷ a _1,1 × a _2,1 + a _2,2 a _3,2 '= a _1,2 ÷ a _1,1 × a _3,1 + a _3,2 a _4,2 '= a _1,2 ÷ a _1,1 × a _4,1 + a _4,2 ... (12) Error correction shown in Fig. 7 Based on the above principle, the apparatus obtains the coefficient or error pattern of each term of the error locator polynomial by subjecting the matrix given by equation (10) to the left fundamental transformation. From 20 registers a _{i, j,} which store 20 data words corresponding to each element a _{i, j} (i = 1,..., 4, j = 1 _,. And a data word exchanging unit 7 comprising _two buffer registers R ₁ and R ₂ provided for each column.
It is composed of an arithmetic processing unit 73 for performing the arithmetic processing of equation (2) and (12), and a “0” detecting unit 40 for performing row replacement control and the like.

The operation of FIG. 7 is performed by changing the coefficients σ _{0 to} σ ₃
Is described as an example.

If the syndrome S ₀ to S ₇ is supplied, first, matrix storage unit
The input gate A of each register a _{i, j} of 71 is controlled, and each syndrome S _{0 to} S ₇ is registered in a register a _{i, j} corresponding to each element a _{i, j} of a matrix.
Write to _{i and j} respectively. As a result, the registers a _{i, j} store the matrix states represented by the first term on the left side of the above equation (5), that is, the states S _{0 to} S _{7 in the} states represented by the following equation (13).

Here, in order to facilitate understanding of the subsequent processing operation,
Syndromes S ₀ to S shown below using specific numerical values as a value of _7.

S ₀ = 0 S ₁ = 15 S ₂ = 85 S ₃ = 115 S ₄ = 193 S ₅ = 115 S ₆ = 161 S ₇ = 231 By substituting the values of the syndromes S _{0 to} S ₇ into the above equation (13) The following equation (14) is obtained.

From this equation (14), the coefficient σ ₀ of each term of the error locator polynomial
As described above, in order to obtain σ ₃ , it is necessary to transform the matrix of the equation (14) to the basic left as shown in the following equation (15).

First, the first column in equation (14) is However, since _a1,1 in the first row and the first column is 0, it cannot be deformed as it is. So, this a _1,1
Replace the entire first row containing = 0 with another non-zero row.
In this example, the second line is replaced.

That is, the “0” detection circuit 74 _sets a _1,1 = 0 in the first row and first column.
Is detected, the five registers a _{1,1 to} a
Data words stored in _1,5 (0,15,85,115,193)
To the buffer registers R ₁₁ , R ₂₁ ,
The data words (15, 85, 115, 193, 115) stored in the five registers a _{2,1 to} a _2,5 in the second row are temporarily saved in R ₃₁ , R ₄₁ , and R ₅₁ , respectively. To the buffer registers R ₁₂ , R ₂₂ , R ₃₂ , R ₄₂ , and R ₅₂ respectively.
Then, the data words (15, 85, 115, 193, 115) of the buffer registers R ₁₂ , R ₂₂ , R ₃₂ , R ₄₂ , and R ₅₂ are opened to the input gates C and the registers a _{1,1 to} a _1,5 in the first row. stores, buffer register _{R 11, R 21, R 31} , R 41, first line of data words saved in the R ₅₁ (0,15,85,115,19
3) is written into the registers a _{2,1 to} a _2,5 in the second row, and the data words in the first and second rows are exchanged. By replacing the rows, the matrix of equation (14) becomes as shown in the following equation (16).

After replacing the rows as described above, the first column of equation (16) is changed Is performed.

That is, the output gate H of the register a _1,1 and the register a
_{1 and 2} of the output gate I, register a _2,1, a _3,1, the output gate K and registers a _{2, 2} of a _4,1, a _3,2, opens the output gate J of a _{4, 2,} The values of these registers 15,85,0,85,115,15,115,
193 is sent to the arithmetic processing unit 73. The operation processing unit 73 executes the operation of the expression (12) by the reciprocal generator D ₀ , the multipliers M _{1 to} M ₄ , and the adders A _{1 to} A ₄ , and calculates the first column of the expression (16). _A2,1 = 15, _a2,2 = 1 in each row of the second column when transformed to
5, a _2,3 = 87, a _2,4 58 are obtained, and the respective values are added to the adder A ₁
Output from the ~A _4.

The adder A ₁ to A ₄ each value 15,15,87,58 output from is stored in the second column each line from the input gate D of each register a _2,1 ~a _2,4. Therefore, at the end of this processing, the values stored in the registers a _{i, j} of the matrix storage unit 71 are as shown in the following equation (17).

The point to be noted in the above equation (17) is that the registers a _{1,1 to} a _1,4 corresponding to the elements a _{1,1 to} a _{1,4 in} the first column, respectively.
Is the value of the syndrome stored in , And retains the previous value of 15,0,85,115. This is because the numerical values actually required to find the coefficients σ _{0 to} σ ₃ of each term of the error locator polynomial are, as is clear from the equations (6) and (7), the first to the first.
When the fourth column is transformed into a unit matrix, only the values of each row in the fifth column are finally obtained. Therefore, it is not necessary to rewrite the values of the columns for which the computation has been completed for the part of the unit matrix. is there.

When the transformation processing of the first column is completed as described above, the processing shifts to the transformation of the second column, and the second column is transformed in the same manner as described above. Is performed.

When the same processing is repeatedly executed up to the third and fourth columns, each register a _{i, j} of the matrix storage unit 71 stores the following (1
8) A value like the equation is obtained.

From equation (18), the coefficient σ ₀ of each term of the error locator polynomial
as σ ₃ Is obtained.

In the above equation (18), the values in each row of the first to fourth columns are not rewritten and remain the same as the previous values. Is equivalent to

[Problems to be solved by the invention]

In the above-described long distance code error correction apparatus, by arranging the operation means in each row, the elements in each row can be transformed in parallel using one column as a processing unit, so that the processing time can be remarkably reduced. However, it is necessary to prepare one register a _{i, j} corresponding to each element a _{i, j} of the matrix giving the data word, and to control the gates of each register independently. As a result, the size of the apparatus cannot be sufficiently reduced.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an error correction device that has a small amount of hardware and can be reduced in size.

[Means for solving the problem]

In order to achieve the above object, the present invention has a structure in which one word is composed of W bits and a coefficient or an error pattern of each term of an error locator polynomial is obtained from a syndrome when decoding a long distance code capable of correcting a maximum of t words of error. , A data word A _{(i + j−2)} (where 1 ≦ i ≦ t, 1 ≦ j ≦ t + 1, A) is assigned to each element q _{i, j} of a matrix of t rows and (t + 1) columns.
_{0 to} A _2t-1 set the syndrome or error position)
In a long distance code error correction device in which the coefficients of the above polynomial are obtained by subjecting this matrix to the left basic transformation, the bit width (W × t) and the number of addresses (t
+1), and a memory in which each of the (t + 1) addresses and each column of the matrix correspond to each other in a one-to-one correspondence. The arithmetic processing is performed on a column basis by writing / reading the data.

Also, even when the value of the diagonal element of the column to be left-reformed is “0”, the value of the corresponding column of another row selected for replacement is read directly from the memory without replacement, and the next Column values are now calculated.

[Action]

Since the addresses of the memory correspond to the columns of the matrix in a one-to-one correspondence, data words such as syndromes constituting each element of the matrix are stored at the corresponding address positions in the memory in column units. Therefore, t rows (t +
1) A matrix for obtaining a coefficient or an error pattern of each term of the error locator polynomial composed of data words in a column is configured.

Also, when the value of the diagonal element of the column to be left fundamentally deformed of the matrix stored in the memory is “0”, the row of the memory cannot be replaced because the address of the memory is configured in units of columns. Without exchanging the row including the diagonal element, the value of the column of another row to be exchanged is read, and the value of the next column by the left basic transformation is calculated based on this value.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention. In the figure, reference numeral 1 denotes a random access memory (hereinafter, referred to as RAM) for storing data words corresponding to each element of a matrix for performing a left basic transformation, and 2 inputs a data word such as a syndrome to the RAM. Shift registers for latching, 3 and 4 are registers for latching data words in column units taken out of memory to perform left basic transformation, and 5 and 6 are data words for arithmetic operation by left transformation in registers 3 and 4. A selector for selecting from the data words in column units latched in the register, 7 for a divider, 8 for a multiplier, 9 for an adder, and 10 for selecting the operation result of the divider 7 or the adder 9 to the buffer 11. A transmission selector, 11 is a buffer, and 12 is a control circuit including a CPU for controlling the processing operation.

FIG. 2 shows an example of the address configuration of the RAM 1 for storing the data words. In the example of FIG. 2, the matrix (11) given above, that is, the following equation (21) is used. Is an example of a RAM that stores a matrix of 4 rows and 5 columns indicated by
Each data word giving each element a _{i, j} of the matrix is 8
Becomes a bit configuration, and in each of the first to fifth columns of the matrix,
Addresses # 1 to # 5 are assigned corresponding to 1: 1.
Therefore, the total bit number of RAM1 in FIG. 2 is 8 × 4 × 5 =
160 bits. By accessing the RAM 1 by designating any one of the addresses # 1 to # 5, the data word at the position of each element a _{i, j} of the matrix can be read / written in column units. Shift register 2, as shown in FIG. 3, and a number of registers 2 ₁ to 2 _t equal to the number of rows t matrix.

By the way, when performing the left basic transformation process of the matrix, as described in the section of the related art, the diagonal element becomes 0 during the process.
, After replacing with another line that is not 0,
It is necessary to find the value of the next column by the above equation (12).
However, as is apparent from FIG. 2, in the present invention, the addresses of the memory and the columns of the matrix are made to correspond to 1: 1.
Since data words are read / written in column units at the corresponding address positions, it is difficult to exchange rows in the RAM, and even if it is possible, complicated processing is required. . Therefore, in the present invention, instead of exchanging rows, the value of the next column is calculated directly from each value of the exchanging row as described below.

That is, a _1,1 = 0, a _2,1 ≠ 0 in the above equation (21).
When the second row is selected as a replacement row in the left basic transformation of the first column in which the diagonal element is 0, the value a of each row in the second column is selected by the left basic transformation of the first column. _{1,2 to} a
_4,2 can be obtained by the following equation (22).

a _1,2 = a _2,2 ÷ a _2,1 × a _1,1 + a _1,2 a _2,2 = a _2,2 ÷ a _2,1 a _3,2 = a _2,2 ÷ a _{2, 1} × a _3,1 + a _3,2 a _4,2 = a _2,2 ÷ a _2,1 × a _4,1 + a _4,2 ... (22) The expression (22) is obtained by the above-mentioned expression (12). Naturally, the same operation result as the expression is given.

Here, the above equation (22) is generalized, and the column to be subjected to the left basic transformation is the i-th column. The row that is replaced with the row of the diagonal element 0 in the i-th column is the d-th row. The following expressions (23) are used to represent the values a _{1, j to} a _{4, j} of the next j-th column.

The present invention realizes the left basic transformation process of the matrix by repeatedly executing the equation (23).

Proceeding to the operation of the embodiment shown in FIG. 1, the case where the number of error-correctable words t = 4, that is, the coefficients σ _{0 to} σ ₃ of each term of the error locator polynomial are obtained using eight syndromes S _{0 to} S ₇ Will be described with reference to the flowcharts of FIGS. 4A to 6 as an example. Incidentally, Figure 4A is a flowchart of a process operation for storing the syndromes S _i in the RAM1, Figure 4B is RAM1
4C is a flowchart for performing a left basic transformation process for each column of the matrix stored in FIG. 4, and FIG. 4C is a flowchart 1 for determining the end of the left basic transformation process.

First, the syndromes S _{0 to} S ₇ are stored in the RAM 1 by the above-described formula (13).
That is, the process of substituting the matrix state as shown in the following equation (24) will be described with reference to the flowchart of FIG. 4A.

Initial set to i = 0 in step [1], taking the syndrome S ₀ which has been entered in step [2] by a shift clock to the shift register 2. Next, in step [3], i is incremented by 1, and in step [4], i ≧ t =
Steps [2] and [3] are repeated until the number becomes 4. Thus, the shift register 2 are four syndromes S ₀ to S ₃ of the first row in (24) is stored.

In step [5], address # 1 the first column of the syndrome S ₀ to S ₃ stored in the (second see figure) to the shift register 2 which corresponds to the first column of matrix (24) in RAM1
After writing, again syndrome S _i in step [6]
Is input to the shift register 2 and i is +
Do one.

The above process is repeated until i ≧ 2t (= 8) is detected in step [8]. Steps [1] to i = 8
When the process of [8], is in the RAM1 are syndromes S ₀ to S ₇ represented by a matrix of (24) is stored.

Next, the left basic transformation of the matrix stored in the RAM 1 is executed according to the flowchart of FIG. 4B. In addition, since it is thought that explanation using specific numerical values will help the understanding, in the following explanation, the syndromes S _{0 to} S ₇ will be described.
S ₀ = 0, S ₁ = 15, S ₂ as in the above equation (14).
= 85, S ₃ = 115, S ₄ = 193, S ₅ = 115, S ₆ = 161, S ₇ = 231
And Substituting this value into equation (24) yields the following.

First, in step [9], an address p = 1 is set,
Start the left elementary transformation of the first column of the matrix.

In step [10], p = 1, that is, # in RAM1
The syndrome (0, 15, 85, 115) of one address is read and stored in the register 4. Then, in a subroutine (described later) of step [11], it is determined whether or not the diagonal element (first row) of the first column is 0.
A row d to be replaced with a column, in this example, d = 2, that is, the second row is determined as a replaced row. Then, in step [12], based on the obtained d = 2, the selector 5 and the selector 6 select the value of the d = 2 row, and the selector 10 sets the b side for the d = 2 row, For the lines other than the second line, the setting is made so that the a side is selected. In step [13], the all-zero flag AZ provided in the control circuit 12 is reset to "0".

In step [14], i is incremented by 1, and in step [15], i =
2, that is, the value (15, 85, 115, 193) in the second column is read and stored in the register 3.

In step [16], the first data stored in the registers 3 and 4
Divide the operation of equation (23) from the values in the row and the second column
7. The values a _{1,2 to} a _4,2 in the second column when the first column is left fundamentally deformed are calculated by the multiplier 8 and the adder 9. That is, a _1,2 = a _2,2 ÷ a _2,1 × a _1,1 + a _1,2 = 85/15 × 0 + 15 = 15 a _2,2 = a _2,2 ÷ a _2,1 = 85 / 15 = 15 a _3,2 = a _2,2 ÷ a _2,1 × a _3,1 + a _3,2 = 85/15 × 85 + 115 = 115 a _4,2 = a _2,2 ÷ a _2,1 × a _4,1 + a _4,2 = 85/15 × 115 + 193 = 193 The value of the second column (15,15,115,
193) is written into the second column of RAM1, that is, address # 2, through the buffer 11. Then, in the subroutine (described later) of step [17], “0” of a row that has not become a diagonal element is detected, and if the values of the rows that have not become a diagonal element are all “0”, The zero flag Z in the control circuit 12 is set to "1", i is set to +1 in step [18], and the flag of the all-zero flag AZ is set by AZ = AZ + Z.

Steps [14] to [18] are replaced with step [1]
9] until i ≧ t + 2 (= 6),
When i = 6, the process of converting each column into a unit matrix is terminated, and the termination condition of the process is determined according to FIG. 4C.

That is, in step [20], if p <t + 1, the process proceeds to step [21] to continue the processing, and p = t + 1
If so, the process ends. In step [21], if the all-zero flag AZ ≠ 0, the process proceeds to step [22],
If AZ = 0, the process ends. If AZ ≠ 0, p is incremented by 1 in step [22], and the column to be fundamentally deformed is shifted to the right by 1
After shifting to the column, the process jumps to step [10], and the above processing is performed in step [20] or step [21], where p = t + 1,
Repeat until AZ = 0.

When the above-mentioned processing is completed, all the left basic transformations of the matrix of the above-described equation (25) stored in the RAM 1 are completed, and each element is as shown in the following equation (26).

Therefore, each value in the fifth row of the equation (26) gives an error position σ _{0 to} σ ₃ , and as in the case of the above-described conventional example, Is obtained.

FIG. 5 shows the details of the subroutine for obtaining the row d of the diagonal element shown in step [11] of FIG. 4B.

In step [30], it is determined from p = 1 (address # 1), and p = 1, that is, the column to be executed is address #
When it is 1, C (1) to C (t) are all set to 0 in step [31]. Here, C (i) indicates whether the i-th row is a diagonal element, and C (i) = 0 indicates that the i-th row is not yet a diagonal element.

Next, in step [32], i = 1 is initially set, and in step [33], the data of the p-th row and the i-th column, that is, the data of the first row and the first column (p = 1, i = 1) stored in the register 4 is obtained. Put D. In the case of the matrix of the equation (25), D = 0.

In step [34], D ≠ 0 and C (1) =
0 is determined, D ≠ 0, and C (1) =
If it is 0, the row of the element is determined as the diagonal element at that time in step [35]. On the other hand, if D ≠ 0 and (1) = 0, i is incremented by 1 in step [36].
If i> p in step [33], the process returns to step [33]. When i <p, it is determined that there is no row to be a diagonal element, an error is detected in step [38], and the process is terminated.

On the other hand, in step [34], the next row i (= 2) can be used as a diagonal element, that is, the value D = 15 ≠ 0 of the second row and the first column
Is determined, the row i = 2 is determined as the row d of the diagonal element to be replaced with the first row, and step [11] in FIG. 4B is performed.
Return to

FIG. 6 shows details of a subroutine for detecting "0" of a row which has not become a diagonal element, which is shown in step [17] of FIG. 4B.

That is, in step [40], the initial value of the row i to be inspected is set to 1 and the zero flag Z is set to 1, and in step [41], the value of the j-th row of the output of the selector 5 is set to D.

In step [42], it is determined that D ≠ 0 and C (j) = 0,
If ≠ 0, C (j) = 0, proceed to step [43]; otherwise, proceed to step [44].

In step [43], since there was a row that did not become a diagonal element and the value was not 0, the zero flag Z was reset to 0, and j was incremented by 1 in step [44]. 45] until j> p. Through the above processing, "0" is detected for a row that has not become a diagonal element.

〔The invention's effect〕

As described above, according to the present invention, only one memory is used in place of the t (t + 1) registers used in the conventional error correction device for the matrix for obtaining the coefficients of the error position polynomial or the error position. , And the processing is executed in units of columns, so that the amount of hardware can be reduced and this type of error correction device can be further downsized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of one embodiment of the present invention, FIG. 2 is a diagram showing an address configuration of a RAM in FIG. 1, and FIG. 3 is a diagram showing a configuration example of a shift register in FIG. 4A to 4C are flowcharts of the operation of the above embodiment, FIG. 5 is a flowchart of a subroutine for obtaining a row d of a diagonal element, and FIG. 6 is "0" of a row which is not a diagonal element. FIG. 7 is a block diagram showing a conventional example of an error correction device. 1 ... RAM, 2 ... Shift register, 3,4 ... Register, 5,6 ...
Selector, 7: Divider, 8: Multiplier, 9: Adder, 10
... selector, 11 ... buffer, W ... bit number of one word,
t: the number of words that can be corrected, q _{i, j} ... each element of the matrix, A
_{(i + j-2)} ... data word.

Claims (2)

(57) [Claims] When decoding a long-distance code capable of correcting an error of up to t words in one word having a W-bit structure, t rows (t + t) are used to obtain a coefficient or an error pattern of each term of an error locator polynomial from a syndrome.
1) A data word A is _assigned to each element q _{i, j} of the column matrix.
_{(i + j-2) (where,} 1 ≦ i ≦ t, 1 ≦ j ≦ t + 1, A 0 ~A 2t-1 position of the syndrome or the error) above by setting a left base deforming the matrix In an error correction device for a long distance code in which a coefficient of a polynomial is obtained, a bit width (W × t) and the number of addresses (t + 1) are used.
And (t + 1) addresses and each column of the matrix
It has a memory corresponding to 1: 1 and is characterized in that arithmetic processing is performed on a column basis by writing / reading data words of each column of the matrix to corresponding address positions of the memory on a column basis. Long distance code error correction device. 2. The value of the diagonal element of the column to be left-basis-deformed is "0"
In this case, the row is not replaced, and the value of the corresponding column of another row selected for replacement is read directly from the memory to calculate the value of the next column. 1) An error correcting device for a long distance code as described above.