JP2713570B2 - Self-routing channel - Google Patents

Description

The present invention relates to an interconnection network used for communication between processors of a computer or a self-routing communication path based on distributed control by hardware such as a communication path for high-speed packet switching. About. [Prior art] In a centralized control type communication channel used in a digital exchange, etc., the routing control is centralized and software-processed in one place, so the larger the communication channel, the more complicated the routing control becomes. In addition, the processing speed was limited. Eliminate such von Neumann shaped bolt neck,
In order to realize a high-speed and large-capacity communication channel, a self-routing communication channel based on distributed control by hardware has been actively studied in recent years. FIG. 9 is an explanatory diagram showing an example of a conventional self-routing communication channel. For details, Urushiya and Imagawa, "One Configuration of Self-routing Communication Channel," IEICE General Conference 8-17
4 See the paper in 1987. In the figure, 11-1, 11-2,..., 11-n are serial-parallel conversion circuits, 12-1, 12-2,.
2, ...... 13-n are parallel-serial conversion _{circuit, IN 1, IN 2, ......} IN n is incoming _{line, OUT 1, OUT 2, ......} OUT n is the outgoing line (where the (n = 2 ^k And k is a natural number).
The (1 ≦ i ≦ k) stage communication path stage has n elements (S _{1i to} S _ni ), and an internal link (Y
_{1i to} Y _ni ), and are cascaded in a cyclic manner in a single direction (S _1i → S _2i →... → S _ni → S _1i ). The communication information input to each incoming line (IN _{1 to} IN _n ) is parallelized by the serial / parallel conversion circuits (11-1 to 11-n) to the number of bits (P) equal to the packet length (the number of bits of the communication information). After being developed, the communication path stages (12-1 to 12-
k) by being moved to the outgoing line position of interest, is output by the parallel-serial conversion circuits (13-1 to 13-n) parallel-serial converted out line _{(OUT 1, OUT 2, ......} OUT n) to . The operation of the communication path stage will be described below. First, each incoming line (IN ₁ to IN _n), the header information indicating the difference outgoing line position to output the communication information (referred to as 0) and the incoming line position (referred to as I) ( The communication information including H) is input. The header information is given by the following equation. H = (O−I) mod n Here, the symbol “mod” indicates a modulo function. That is, It is. The operation of the i-th communication channel stage 12-i is as follows. Each element included in the communication path stage 12-i ( _S1i to
S _ni ) is a communication input from the input line (X _{1i to} X _ni ), based on the _i-th header information bit hi counted from the top of the header information input from the input line (X _{1i to} X _ni ). after information of the moving between the elements only h _i · 2 ^ki by internal link (Y _1i ~Y _ni), finally reaches the element (S _1i ~S _ni) connected to an output line _{(X 1 (i + 1)} ~ _{Xn (i + 1)} )
Output to The above operation is the same in the first to kth communication path stages, and the movement of communication information between elements and the movement between communication path stages are all performed in synchronization. As a result, the communication information input from the incoming line is composed of the first to kth communication path stages based on the header information (routing control information) indicating the difference between the outgoing line position and the incoming line position. in the self-routing speech path, it is moved to the output position, and is output to the target output line (OUT ₁ ~OUT _n). To do broadcast connection operation for outputting the communication information is input to all of the outgoing line from the incoming line using conventional such self routing speech path, each element (S _1i ~S _ni) is
The communication information input from the input line may be output to the next communication path stage, and may be moved by 2 ^ki between the elements, and then output to the next communication path stage. [Problems to be Solved by the Invention] As described above, in the conventional self-routing communication path, even when communication information input to an arbitrary incoming line is output to an arbitrary outgoing line, communication information within the communication path is Is a non-blocking communication path that does not collide, and has the advantages that the number of elements is as small as nlog ₂ n with respect to the number of input / output lines n, and that routing control is simple. After being expanded to the number of bits equal to the packet length (the number of bits of the communication information) in parallel and sent to the communication path stage, the amount of hardware of the serial-parallel conversion circuit, the communication path stage, and the parallel / serial conversion circuit is proportional to the packet length. There was a disadvantage that it increased. For example, a 16 × 16 switch requires about 90k gates to handle communication information with a packet length of 128 bits, and a packet length of 2
In the case of 56 bits, about 170k gates are required. Also,
There is a restriction that the packet length to be handled must be constant. SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems, to reduce the amount of hardware even when the packet length to be handled is long, to keep it to a certain value or less, and to handle an arbitrary length of packet length. Is to provide. [Means for Solving the Problems] In order to achieve the above object, according to the first invention of the present application, n incoming lines, and serial communication connected to each of the incoming lines and inputted from the incoming line A total of n serial-to-parallel conversion circuits for converting information into parallel n-bit information and outputting the same, and a total of n for converting each parallel n-bit information to parallel communication information and outputting the serial communication information Parallel-to-serial conversion circuits, a total of n outgoing lines respectively connected to the respective output sides of the n parallel-to-serial conversion circuits, the n serial-to-parallel conversion circuits, and the n parallel-to-serial conversion circuits (Where n = 2 ^k , where k is a natural number), and an incoming line position where the communication information is input, and an outgoing line position where the communication information is to be output. Based on the header information including the k-bit routing control information indicating the difference between In a self-routing communication path that controls a communication path stage to guide communication information from an input line position to a target output line position, each communication line stage is cascaded in a unidirectional manner by an internal link. A total of n elements connected
Each element is composed of a total of n sub-elements, each sub-element includes one header information holding circuit, and the header information holding circuit for each sub-element circulates between each other. Cascade-connected to form an n-bit cyclic shift register. In the second invention of the present application, in the self-routing communication path, each of the communication path stages includes a total of n elements cascade-connected in a single direction by an internal link in a cyclic manner,
Where each element consists of a total of n sub-elements,
Each of the sub-elements includes first and second two header information holding circuits, and each of the first and second header information holding circuits for each sub-element includes a first and a second header information holding circuit.
Are cascaded in a cyclic manner between the first holding circuits to form an n-bit first cyclic shift register, and the second holding circuit is mutually connected between the second holding circuits. Are cascaded in a cyclic manner to form a second cyclic shift register of n bits. Then, not only the routing control information but also the broadcast control information is taken in. [Operation] The self-routing communication channel according to the first invention of the present application is:
In each communication path stage, after the communication information is expanded into n bits in parallel, the parallel n bits are shifted one bit at a time from the end and arrive at n input lines, which correspond to the n input lines. Since the header information bits input from the input line are cyclically moved between the n sub-elements while synchronizing with the arrival timing of the communication information to hold the header information bits, the header information bits are expanded in parallel. If the number of bits is an integer multiple of n, an arbitrary packet length can be handled, and a self-routing communication path can be configured with a fixed amount of hardware independent of the packet length. Further, according to the second aspect of the present application, a broadcast connection in which one incoming line is connected to all n outgoing lines is possible. Embodiment FIG. 1 is a circuit diagram showing an embodiment of the present invention. In the figure, 11-1, 11-2,..., 11-n are serial-parallel conversion circuits,
-1,12-2, ... 12-k is the communication path stage, 13-1,13-2, ... 13
n is parallel-serial conversion _{circuit, IN 1, IN 2, ......} IN n is incoming line, OU
T ₁ , OUT ₂ ,..., OUT _n are outgoing lines (there is a relationship of n = 2 ^k ). Each of the i-th (1 ≦ i ≦ k) communication path stages has n elements composed of switch circuits (E _{1i to} E _ni ) and control circuits (C _{1i to} C _ni ). E _{1i to} E _ni ) are cascade-connected in a single direction in a cyclic manner by internal links (Y _{1i to} Y _ni ) (E _1i → E _2i →... → E _ni → E _1i ). The communication information input to each of the incoming lines (IN _{1 to} IN _n ) is expanded in parallel by the serial-to-parallel conversion circuits (11-1 to 11-n) into the number of bits (n) equal to the number of incoming lines, and then further expanded. Its parallel n
The bits are shifted one bit at a time from the end into the communication path stage and enter the communication path stage, and the communication path stages (12-1 to 12
-K), it is moved to the target outgoing line position, and then the parallel / serial conversion circuits (13-1 to 13-n)
Parallel-to-serial conversion is out of line (OUT ₁ by, OUT _2, ...... OU
T _n ). In FIG. 1A, for example, serial communication information (a, b, c,...) Input to the incoming line IN _m is expanded into n bits in parallel by a serial / parallel conversion circuit, and then, one bit at a time from the end. FIG. 8 is an explanatory diagram showing in a manner that the input _light is shifted to the traveling direction and is input to input lines X _m1-1 , X _m1-2 ,..., X _m1-n . Returning to FIG. 1, the operation of the circuit will be described below. First, each of the incoming lines (IN _{1 to} IN _n ) includes the communication information including header information (H) indicating the difference between the outgoing line position (O) from which communication information is to be output and the incoming line position (I). Is entered.
The header information is given by the following equation. H = (O−I) mod n Here, the symbol “mod” indicates a modulo function. That is, It is. Therefore, the header information (routing control information) is represented by k bits (k = 1og ₂ n). It should be noted that FIG. 1B shows an example of the frame configuration of the communication information. Since the movement of communication information between elements in the communication path stage and between the communication path stages is performed synchronously and every clock,
Finally, the communication information arriving at the parallel / serial conversion circuit includes a delay variation because the passage route differs depending on the header information H (equal to the difference between the input and output positions). For this reason, the parallel-to-serial conversion circuits (13-1 to 13-n) incorporate a delay fluctuation absorbing circuit as shown in FIG. 1C (a). In FIG. 1C (a), F1 and F2 are flip-flops, D is an n-bit delay circuit, and A is an AND gate. FIG. 1C (b) is a time chart of the signals of each part in FIG. 1C (a). Please refer to both figures. In the input, when routing control information is (n-1), that is, when incoming line position is the outgoing line position IN ₁ is OUT _n, the input signal A with respect to the arrival at the n bit periods as A1, A2 When the routing control information is 0, that is, when the incoming line position is IN _n and the outgoing line position is OUT _n , the input signal B is immediately after A2 without separating n-bit periods from A2 as in B1. There is a delay variation that appears in At the output, such delay fluctuations are absorbed and all n
It will be appreciated that the output is at the bit period. Returning to FIG. 1, the operation of the i-th communication channel stage 12-i will be described below. Each control circuit (C _{1i to} C _ni ) is connected to a signal line corresponding to the i-th bit of the input lines (X _{1i to} X _ni ) that are developed in parallel into n bits. said header information bits to extract h _i, the header information bits in synchronization with the communication information bits arriving by shifting one bit to each of the switch circuits (E _1i ~E _ni) from the parallel expanded input lines to the n bits h _i is cyclically moved by an n-bit shift register in each control circuit (C _{1i to} C _ni ), and the header information bit
Based on h _i , the communication information bits are moved by h _i · 2 ^(ki ) between the switch circuits (E _{1i to} E _ni ), and the output line (X _{1 (i +1)} ~
(X _{n (i + 1)} ). The details of the operation of the above element will be described with reference to the configuration example of the element shown in FIG. 2 and the time chart of FIG. FIG. 2 is a circuit diagram showing an example of the configuration of the element on the m-th row (1 ≦ m ≦ n) in the communication path stage of the i-th stage (1 ≦ i ≦ k), and E _{mi-1 to} E _mi-n Is a sub-switch circuit, C _{mi-1 to} C
_mi-n is a sub-control circuit, and E _mi-j and C _mi-j (1 ≦ j ≦
A sub-element is constituted by a pair of n). The sub switch circuit E _mi-j has an input line X _mi developed in parallel to n bits.
And signal lines X _mi-j , Y _mi-j , and X _m respectively corresponding to the j-th bit of the input internal link Y _mi and the output line X _{m (i + 1)} and the output internal link Y _{(m + 1) i. (i + 1) -j} and Y _{(m + 1) ij} are connected. On the other hand, the sub-control circuits C _{mi-1 to} C _mi-n are cascaded in a cyclic manner, and as a whole, constitute an n-bit cyclic shift register. The input line X _mi-i is connected to the sub control circuit C _mi-1 . As shown in the time chart of FIG. 3, the input line X
2 The ^{_{mi-i (k-i +}} 1) communication information bit by bit intervals (h _1, x
₁₁ , h ₂ ) arrive one bit at a time and the input internal link Y _mi-i
Up to 2 ^(ki) one bit behind the communication information bit
Communication information bits of the bit _{(y 11 ~y 14, y 15} ~y 18, y
_19- ) arrive. Similarly, the communication information bit arrives at the input line X _{mi- (i + 1)} and the input internal link Y _{mi- (i + 1)} , but the input line X _mi-i and the input internal link Y _mi- Each bit is delayed by 1 bit compared to _i . The operation of the circuit is described below. First, the OR gate (OR) in the sub-switch circuit (E _mi-i )
1) and input line X _mi-i by flip-flop (DFF1)
_{Alternatively} , the communication information bits (h ₁ , y
_{11 ~y 14, X 11, y} 15 ~y 18, h 2, y 19 ~) are taken into the flip-flop DFF1. On the other hand, the sub control circuit (C _mi-i )
AND gate (AND3, AND4) and OR gate (OR2)
And flip-flop (DFF2), the input line X _mi-i
Upper header information bits (h ₁ , h ₂ ) and clock signal CK
i is taken into the flip-flop DFF2. Where CKi is
X based on the information input from _{mi-i
Output to mi- (i + 1)} or Y _{(m + 1) ii} , and Y if the information input from Y _mi-i is not shifted by 2 ^(ki) from the previous stage
If it is shifted from _{(m + 1) ii} by 2 ^(ki) , it is a clock to output to X _mi-i . The output signal H _mi-i has a repetition pattern of logic 1 up to 2 ^(ki) -1 bits counted from the header information bit and the next 1 bit is logic 0. The output signal H _mi-i is connected to AND gates (AND1, AND2) in the sub-switch circuit E _mi-i , and the flip-flop (D
Communication information bits taken into DF1) is h ₁ = 1 a long if the output in links Y to the _{(m + 1) ii),} the output line if h ₁ = 0 X
Output to _{m (i + 1) -i} . Further, the signal H _mi-i is transferred to the next sub-control circuit (C _{mi- (i + 1)} ), and then the signal H _mi-i is _sent to a cyclic shift register composed of n flip-flops (DFF2). Forwarded to click. As a result, n-bit parallel signals (X _mi-i , Y _mi-i ) that arrive with a delay of 1 bit
And the signal (H _mi-i ) is synchronized, and arbitrary j (1 ≦ 1)
j ≦ n), all communication information bits input from the input line (X _mi-j ) are moved between the switch circuits by h _i · 2 ^(ki), and then connected to the last arrived switch circuit. Output to the output line. FIG. 2A shows an AND gate (A _mi-i ) in the sub-switch circuit (E _mi-i ) for use in the control of the i-th stage in FIG. 2 and removing unnecessary header information bits in the next and subsequent communication channel stages.
FIG. 14 is a circuit diagram showing a configuration example to which an ND5) is added. FIG. 3A is a time chart showing the output line (X _{m (i + 1) -i} ) and the output internal link (Y
It will be appreciated that unnecessary header information bits (h ₁ , h ₂ ) have been removed from _{(m + 1) ii} ). FIG. 4 is a circuit diagram showing another embodiment of the present invention. In the figure, the storage circuits (34-1 to 34-34) are connected between the k-th communication path stage (12-k) and the parallel / serial conversion circuits (13-1 to 13-n).
−n), which is different from FIG. These storage circuits are provided to communicate communication information from a plurality of incoming lines to the same single outgoing line. That is, by temporarily storing communication information in the storage circuit, it is possible to avoid collision of communication information output to the same output line by the same parallel-serial conversion circuit. FIG. 5 is a circuit diagram showing another embodiment of the present invention. The difference from FIG. 1 is that the following means are added. In each of the i-th communication path stages 12-i, each control circuit (C _{1i to} C _ni ) has an input line (X
_{1i to} X _ni ) corresponding to the J-th bit (J corresponds to the position of the broadcast control bit instructing to output the communication information input from the incoming line to all outgoing lines; see FIG. 1B). Signal lines (X _{1i-J to} X _ni-J ) are connected. The direction control bit b is extracted from the signal lines, and each switch circuit (E _1i to E _ni ), the broadcast control bit b is cyclically moved by a second n-bit shift register in each control circuit in synchronization with the communication information bit arriving one bit at a time. B = 1 based on the communication information bit
If it is directly output to the output line _{(X 1 (i + 1)} ~X n (i + 1)),
And 2 ^(ki) pieces only move between the switching circuit and finally arrived switching circuits (E _1i ~E _ni) connected to an output line _{(X 1 (i + 1)} ~X n (i + 1)) Output to Moreover, any not control the switching circuit (E _1i ~E _ni) if b = 0. The configuration shown in FIG. 5 enables a one-to-one connection that connects one incoming line to n outgoing lines in addition to a one-to-one connection that connects an incoming line and an outgoing line in a one-to-one relationship. FIG. 6 is a circuit diagram showing a configuration example of an element for realizing the above operation, and FIG. 7 is a time chart thereof.
The description of the circuit operation will be apparent by analogy with the circuit operation of the other embodiments already described. FIG. 8 is a circuit diagram showing still another embodiment of the present invention. In the figure, the storage circuits (34-1 to 34-n) are connected between the k-th communication path stage (12-k) and the parallel / serial conversion circuits (13-1 to 13-n).
34-n), which is different from FIG. This is provided to communicate communication information from a plurality of incoming lines to the same outgoing line. By temporarily storing the communication information in the storage circuit, collision of communication information output to the same outgoing line by the same parallel-serial conversion circuit can be avoided. [Effects of the Invention] As described above, according to the present invention, non-blocking communication in which communication information does not collide with each other in a communication path even when communication information input to an arbitrary incoming line is output to an arbitrary outgoing line. It is possible to construct a path, the required number of elements is as small as nlog ₂ n with respect to the number n of input / output lines, and the routing control is simple. Furthermore, if it is an integer multiple of the number n of bits that are parallel-expanded, it is possible to handle a packet length of an arbitrary length, and it is possible to configure a self-routing communication path with a fixed amount of hardware independent of the packet length. is there. For example, in a 16 × 16 switch, about 20 k gates are sufficient regardless of the packet length.
5, When the packet length is 256 bits, it is about 1/9, and the amount of hardware can be greatly reduced. If the number of input / output lines is an integer multiple of n, an arbitrary packet length can be handled, and the flexibility is dramatically increased. If necessary, one-to-one connection and N-to-1 (1 ≦ N ≦
n) Connection (multiplexing) and one-to-n connection (broadcast connection) are possible, and an extremely flexible self-routing communication path can be provided.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG.
FIG. 1B is a time chart for explaining the operation of the serial-parallel conversion circuit in FIG. 1, FIG. 1B is an explanatory diagram showing a frame configuration example of the communication information, and FIG. 1C (a) is the delay variation built in the parallel-serial conversion circuit in FIG. FIG. 1C (b) is a time chart for explaining the operation of the absorption circuit, FIG. 2 is a circuit diagram showing an example of the configuration of the elements in FIG. 1, and FIG. 2A is FIG. FIG. 3 is a time chart explaining the operation of FIG. 2, FIG. 3A is a time chart explaining the operation of FIG. 2A, and FIG. Circuit diagram showing another embodiment,
FIG. 5 is a circuit diagram showing another embodiment of the present invention, FIG. 6 is a circuit diagram showing a configuration example of elements in FIG. 5, FIG. 7 is a time chart for explaining the operation of FIG. FIG. 9 is a circuit diagram showing still another embodiment of the present invention, and FIG. 9 is a circuit diagram showing a conventional example of a self-routing communication path. Description of reference numerals 11-1, 11-2, 11-n ... serial-parallel conversion circuit, 12-1, 12-2, 12
-N: communication path stage, 13-1, 13-2, 13-n: parallel-to-serial conversion circuit

Claims (1)

(57) [Claims] n incoming lines, a total of n serial-parallel conversion circuits connected to each of the incoming lines and serially / parallel-converted serial communication information input from the incoming line into parallel n-bit information and output; A total of n parallel-to-serial conversion circuits for converting the input parallel n-bit information into serial communication information and outputting the serial communication information, and connected to each output side of the n parallel-to-serial conversion circuits, respectively. A total of n outgoing lines, and k communication path stages (where n = ^2k , where k is a natural number) connecting the n serial / parallel conversion circuits and the n parallel / serial conversion circuits.
Based on header information including k-bit routing control information indicating a difference between an incoming line position where the communication information is input and an outgoing line position where the communication information is to be output, and In the self-routing communication path that guides the input from the input incoming line position to the target outgoing line position, each of the i-th (where 1 ≦ i ≦ k) -stage communication path stages are each developed into n bits in parallel. N sets of input lines from the preceding stage, n sets of output lines that are similarly developed and directed to the following stage, and each are connected between one set of the input lines and one set of the output lines, A total of n elements cascade-connected in a single direction in a cyclic manner by internal links also expanded to n bits in parallel with each other, and each element includes communication information expanded to n bits in parallel. Corresponding to each bit of It consists of a total of n sub-elements, each sub-element of which has one of the input lines which are developed in parallel to n bits and one of the output lines which is also developed in parallel to n bits. Are connected as a pair, one of the internal links similarly expanded in n bits is connected as an input / output line, and one sub-element is provided with one header information holding circuit. Included,
The header information holding circuits of the respective sub-elements are cascade-connected in a cyclic manner between each other to constitute an n-bit cyclic shift register. In the sub-element corresponding to the i-th bit of the input line that has been expanded in parallel, when a header information bit is present on the i-th input line, the header information bit is transferred to the sub-element via the header information holding circuit. It is taken into the cyclic shift register and counted from the header information bit (2
^(ki) -1) A repetition pattern in which the first bit is logic 1 and the next 1 bit is logic 0 is fetched into the cyclic shift register and circulated regardless of the presence or absence of a header information bit. When the signal in each of the header information holding circuits constituting the cyclic shift register is logic 1, the signal bit input from the input line or the input internal link side is output to the output internal link side, A self-routing communication path for outputting a signal bit input from an input line or an input internal link side to an output line side when a signal in the circuit is logic 0. 2. 2. The self-routing communication channel according to claim 1, wherein n information storage circuits are connected between said n parallel-serial conversion circuits and said k communication channel stages. You want a self-routing channel. 3. n incoming lines, a total of n serial-parallel conversion circuits connected to each of the incoming lines and serially / parallel-converted serial communication information input from the incoming line into parallel n-bit information and output; A total of n parallel-to-serial conversion circuits for converting the input parallel n-bit information into serial communication information and outputting the serial communication information, and connected to each output side of the n parallel-to-serial conversion circuits, respectively. A total of n outgoing lines, and k communication path stages (where n = ^2k , where k is a natural number) connecting the n serial / parallel conversion circuits and the n parallel / serial conversion circuits.
Comprising k-bit routing control information indicating the difference between the incoming line position at which the communication information is input and the outgoing line position to be output, and converting the communication information from the input line position at which it is input. On the basis of header information including 1-bit broadcast control information for instructing output to all outgoing line positions, the communication path stage is controlled to transmit communication information from the input incoming line position to a target outgoing line position. Or the self-routing communication path leading from the input incoming line position to all the outgoing line positions, the i-th (where 1 ≦ i ≦ k) -stage communication path stages each have n bits. N sets of input lines from the front stage expanded in parallel, n sets of output lines similarly expanded to the next stage, and each are connected between one set of the input lines and one set of the output lines. At the same time, A total of n elements cascaded in a single direction in a cyclic manner by an internal link expanded in parallel to n bits, wherein each element of the communication information is expanded to n bits in parallel. , Each of which has one of the input lines expanded in parallel to n bits and one of the output lines similarly expanded to n bits in parallel. Are connected in pairs, one of the internal links similarly expanded in parallel to n bits is connected as an input / output line, and each of the sub-elements is connected to the first and second sub-elements. And the first and second header information holding circuits for each sub-element are such that the first holding circuit is a cyclic type between the first holding circuits. N bits The first cyclic shift register of the
The second holding circuit is cascaded in a cyclic manner between the second holding circuits to constitute an n-bit second cyclic shift register. The elements in each i-th communication path stage include: In a sub-element corresponding to the ith bit of the input line, which is developed in parallel to n bits, when the routing control information bit is present on the ith input line, the routing control information bit is converted to the first bit. The first cyclic shift register is fetched into the first cyclic shift register via the header information holding circuit, and logic ⁽ 1) is counted up to the (2 ^(ki) -1) th bit counted from the routing control information bit, and the next bit is logic 0. Irrespective of the presence or absence of the routing control information bits, the repetition pattern is fetched into the first cyclic shift register and circulated, and is expanded into n bits in parallel. The J input of the broadcast control information bits among the field lines (1 ≦
(J ≦ n) In the sub-element corresponding to the input line of the bit, when the broadcast control information bit exists on the input line of the J-th bit, the broadcast control information bit is transmitted to the second line.
In each of the sub-elements, the signal in each of the first header information holding circuits is logic 1 or the second in the second cyclic shift register. When the signal in the header information holding circuit is logic 1, the signal bit input from the input line or the input internal link side is output to the output internal link side, and the signal in each of the first header information holding circuits is logic 0. Or the signal in the second header information holding circuit is logic 1
Wherein the self-routing communication path outputs the signal bit input from the input line or the input internal link side to the output line side. 4. 4. The self-routing communication path according to claim 3, wherein n information storage circuits are connected between said n parallel-serial conversion circuits and said k communication path stages. You want a self-routing channel.