JP2703178C - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION       [0001]     [Industrial applications]   The present invention controls access to a frame buffer memory for storing image forming data.
An image forming system for obtaining a hard copy by
The image forming data for the data is stored in the frame buffer memory, and the image forming data is stored in the frame buffer memory.
Address control for drawing data, drawing address control, and refresh
A technology that is effective when applied to a system that forms an image by performing address control
It is.       [0002]     [Prior art]   Conventionally, display and drawing address control for the frame buffer memory are performed.
CRTC (cathode ray tube controller) or A as controller
CRTC (Advanced Cathode Ray Tube Controller) used
These are described in “LSI Handbook” issued by Ohmsha on November 30, 1984.
Of the horizontal and vertical synchronizing signals as described in
Timing, various parameters such as the number of characters and pixels per line, and the number of raster lines
Data is set programmable, and the display data is displayed on the CRT display accordingly.
It basically has a display control function to supply to the device, and has no
During the display period, a drawing or dynamic framebar for changing the contents of the display screen
The buffer memory is refreshed.       [0003]   The present inventors have proposed a method similar to raster scanning in a CRT display device.
For controlling a hard copy device such as a laser printer for forming an image,
The application of the spray controller was discussed. That is, the frame buffer
Control of print data output address for memory
Control of print data for the
Try to make display controller support refresh address control
Things.       [0004]     [Problems to be solved by the invention]   In hard copy devices such as laser printers, optical systems and photosensitive drums
Printing required according to the state of the mechanical drive system that drives the paper and supplies paper
Data must be supplied. By the way, hardware like a laser printer
For example, in a copy device, a line feed or page break during a normal print operation,
Page break when trouble such as running out of paper or ink
Therefore, the required initialization timing of the mechanical system is often different.
You. In such a situation, the display controller must provide horizontal and vertical synchronization signals.
Display address control is performed in full synchronization with the display controller.
When configuring the system by using it as it is, change the state of the mechanical system of the hard copy device.
Dedicated timing adjustment circuit for controlling print data output address according to
Is required, which complicates circuit configuration and control.
The title was found.       [0005]   In addition, refresh address control by the display controller
And completely synchronized with the vertical sync signal, making it relatively
Hard copy devices, such as laser printers, that can be run at short intervals
In the case of, the non-image forming period is one
Is not specified, and an output request for image formation data is issued randomly according to the operation of the mechanical system.
In order to perform refreshing at the minimum necessary interval,
Print data output address control according to the mechanical system status of the hard copy device
Timing control circuit for refreshing
Function must be added, and the print data output address
Control of the output timing of the scan address, drawing address, and refresh address is extremely difficult.
It will be difficult.       [0006]   An object of the present invention is to facilitate printing according to the state of a printer mechanical system of a hard copy device.
Provides an image forming system that can perform lint data output address arithmetic control
Is to do. Further, another object of the present invention is to reduce the frame buffer memory. Regarding fresh, print data output address according to the status of printer mechanical system
Refresh timing at predetermined intervals easily in the context of
An object of the present invention is to provide an image forming system capable of controlling the image forming.       [0007]   The above and other objects and novel features of the present invention are described in the present specification and the accompanying drawings.
Will be apparent from.       [0008]     [Means for Solving the Problems]   A brief summary of the typical inventions disclosed in the present application is as follows.
It is as described.       [0009]   That is, the image forming data is read from the frame buffer memory and
An image forming system for forming an image on a medium by giving the image to a mechanical system.
From the printer mechanical system control unit to control the image forming operation by the mechanical system
Instruction signal output according to the operation state of the image forming data output address arithmetic control
For inputting the image data and reading out the image forming data in synchronization with the instruction signal
Performs arithmetic control to store the image formation data output address in the frame buffer memory.
Supplies the image forming data in synchronization with the state of the printer mechanical system.
To be given to the mechanical system.       [0010]   UpFrame buffer memoryIsRequires refresh of stored information. At this time,
In each memory cycle of the frame buffer memory, the refresh address
The output operation of the image forming data output address has priority over the output operation. Also
,Output of sequentially updated refresh address to frame buffer memory
The number of times is counted by the counting means at each refresh interval, and is controlled at predetermined times.
And the refresh address output cycle in each refresh interval.
By the time the number reaches the predetermined number, the arbitration means operates the image forming data included in the instruction signal.
Data output request, the image formation data output address corresponding to the request
Refresh address generation that prioritizes the refresh output to the refresh address output
Road Is adopted.       [0011]   The instruction signal indicates that an image can be formed by receiving the supply of the image forming data.
Request for image formation data output, and the operation to change the medium on which the image is to be formed.
Line feed in accordance with a page feed signal and an operation to feed a line forming an image on the medium
It can be a signal. At this time, the image forming data output address arithmetic control
The section sets the image forming data output address in synchronization with the instruction by the page break signal.
Initialize to the start address of image forming data in the system buffer memory
Address calculation control for the image forming data in synchronization with the instruction by the line feed signal.
Performs arithmetic control to initialize the output address to the beginning of the next line.
The initialization is performed in synchronization with the instruction by the image formation data output request signal immediately after the initialization.
Outputs the initialized image forming data output address, and outputs the initialized
The image forming data output request signal after the external output of the output image forming data output address
The image forming data output address is changed in the row direction and output in synchronization with the instruction
I do.       [0012]   In the printer mechanical system, light travels in a row direction along the axial direction of the photosensitive drum.
Scanning direction, and the laser light according to the image forming data described above according to the rotation of the photoconductor.
While repeating scanning, an electrostatic latent image is formed on the surface of the photoreceptor, visualized, and
A laser printer mechanical system for obtaining a hard copy can be adopted.       [0013]     [Action]   According to the above-described means, it is possible to respond to the state of the printer mechanical system of the hard copy device.
By enabling address control for image formation data output at the timing,
Requires a dedicated timing adjustment circuit to absorb state fluctuations of the printer mechanical system
Output data according to the status of the mechanical system of the hard copy device.
The dress calculation control is easily achieved with a small-scale circuit configuration.       [0014]   Also, a refresh at a predetermined refresh interval set in advance is performed. By defining the timing in relation to the output request of the image forming data,
In relation to print data output address operation control according to the state of the printer mechanical system
The required refresh control is easily achieved at predetermined intervals.
You.       [0015]     【Example】   FIG. 1 shows a laser printer system as an embodiment of an image forming system according to the present invention.
FIG.       [0016]   In FIG. 1, LZPMCN is a laser printer mechanical system, and a laser diode.
The output of the laser light source LZRSRC including the light is exposed through the rotating polygon mirror RMLR.
Includes an optical system that irradiates the body drum INKDRM. Against photoconductor drum INKDRM
The irradiation of the laser beam is displaced in a substantially horizontal direction, and the photosensitive drum INKDRM
In response to the rotational drive, laser light is emitted in a manner similar to what is called raster scanning. Leh
Although not particularly limited, an electrostatic latent image is formed on the irradiation portion of the
The latent image is visualized through the apparatus, and the ink or the like constituting the visualized image
It is configured to be transferred and fixed to the PR to obtain a hard copy.       [0017]   In FIG. 1, the FBM can rewrite print data in a so-called bitmap system.
Consisting of DRAM (Dynamic Random Access Memory)
This is a frame buffer memory. Data bus from frame buffer memory FBM
The print data read to DBUS is converted into a video signal V by the parallel / serial conversion circuit PSC.
It is converted to S and supplied to the laser control unit LZRC. This video signal VS is
This is a signal for obtaining a pattern to be printed, and the laser control unit LZRC receives the signal.
On / off modulation control of light is performed in accordance with the video signal VS to generate a laser light source LZRSR.
The laser light is output from C. The output laser beam passes through a rotating polygon mirror RMLR.
Then, the image is formed so as to be scanned on the photosensitive drum INKDRM.       [0018]   The drive control of the laser printer mechanical system LZPMCN is performed by the printer mechanical system controller. Performed by the MCCTR. Printer machine system control unit MCCTR
The control signal MCTR is supplied to the laser printer mechanical system LZPMCN, and the
The mechanical system status signal MSTS indicating the control operation status and the like caused by the laser printer machine
Supplied from system LZPMCN. The printer mechanical system controller MCCTR has a mechanical system
Based on the status signal MSTS, a page break signal CP, a line feed signal CR, a print address
Output request signal PRREQ. Each of the above signals is a laser printer mechanical system
This corresponds to the operation state of the LZPMCN, and the page break signal CP is particularly limited.
Is not performed, but corresponds to the timing of forming a latent image on the photosensitive drum INKDRM.
It is formed based on the generation timing of the paper feed trigger signal. Line feed signal C
R is not particularly limited, but is a beam detection for detecting a laser beam indicating a line feed.
It is formed based on the output of the device BS. Print address output request signal PRREQ
The status of each part of the laser printer mechanical system LZPMCN is not particularly limited.
In response to receiving laser irradiation and enabling synchronous operation for image formation.
Output instruction level.       [0019]   In FIG. 1, LZPCTR is a laser printer print controller, and
Print data output address calculation control for the frame buffer memory FBM,
Control of drawing of print data to the frame buffer memory FBM and frame buffer
Peripheral memory that supports refresh address control for the flash memory FBM.
Troller. Control operation of this laser printer print controller LZPCTR
The timing is basically based on the above-described page feed signal CP, line feed signal CR, print address.
Operation of the laser printer mechanical system LZPMCN by the output request signal PRREQ
It is configured to follow the state. In addition, the laser printer print control device LZP
The CTR is coupled to the system bus SYSMBUS and the host processor H
A predetermined control operation is executed based on a command supplied from the MPU.       [0020]   FIG. 2 is a block diagram showing an example of a laser printer print control device LZPCTR.
It is. FIG. 2 particularly shows details of the address signal generation system.
The linter print control device LZPCTR is roughly divided into a frame buffer memory Print output address for controlling output address calculation of print data for FBM
And the print data to the frame buffer memory FBM.
Processor DRWPRO for controlling data drawing and frame buffer memory
Refresh address generation circuit for performing refresh address control on FBM
RFGEN. Print output address operation control unit LZC
Print output address data PADRS output from TR, drawing processor D
The drawing address data DADRS output from RWPRO and the refresh address
Refresh address data RFAD output from the dress generation circuit RFGEN
RS is a predetermined address output data ADRS based on priority control described later.
From the output buffer ABF via the address bus ABUS
It is provided to the memory FBM.       [0021]   FIG. 3 is a block diagram showing details of the print output address calculation control unit LZCTR.
FIG. The print output address calculation control unit LZCTR includes an address calculation register.
It has a star array REG. This register array REG corresponds to the top of the page.
Address register SA for storing address data to be stored, frame buffer
Memory width register MW for storing the number of addresses per row of the memory FBM,
Print address increment that stores the address increment value for each recycling
Register PAI, temporary start address register for storing the start address of each row
The register TSA is composed of a current address register TA that stores the current address.
Is done. Start address register SA, memory width register MW, print address
The address increment register PAI is connected to the host buffer via the input buffer DBF.
Initial data is set by data supplied from the processor HMPU.
Temporary start address register TSA and current address register T
In A, the contents are sequentially rewritten according to the result of operation of the print output address.
.       [0022]   Start address register SA, temporary start address register TSA
, And the output terminal of the current address register TA via gates G1 to G3. It is coupled to one input terminal of the arithmetic circuit AU and has a memory width register MW,
And the output terminal of the print address increment register PAI is the gate G4 and
It is coupled to the other input terminal of the arithmetic circuit AU via G5. Output of arithmetic circuit AU
The terminal is coupled to the input terminal of the output buffer ABF, and is connected to the gate G6.
And the temporary start address register TSA and the current address via G7.
Connected to the input terminal of the slave register TA.       [0023]   Each of the gates G1 to G7 is connected to a selection control signal output from the decoder DCDR.
Open / close control. This decoder DCDR has an RS type horizontal control signal.
Output signal of flip-flop HCFF, RS type vertical control flip-flop V
The CFF output signal, the print address output request signal PRREQ, and the clock
The clock signal CLK is supplied. Reset of horizontal control flip-flop HCFF
A logical sum signal of the line feed signal CR and the page feed signal CP is supplied to the terminal R,
The page break signal CP is supplied to the reset terminal R of the direction control flip-flop VCFF
Is done. Horizontal control flip-flop HCFF and vertical control flip-flop
Each of the set terminals S of the VCFF has a print address output request signal PRREQ.
Is supplied.       [0024]   The line feed signal CR, page feed signal CP, and print address output request signal P
RREQ is not particularly limited, but its high level is set to the active level.
. The line feed signal CR and page break signal CP are the print address output request signal P
RREQ is set to the active level (print address output request instruction level)
Beforehand, the required level is determined in advance. Because, in this embodiment, a line feed or a line feed
When a page is needed, the laser printer mechanical system LZPMCN is
The line feed signal CR and the page feed signal CP are activated in response to the control timing.
The status required for line breaks or page breaks is set to the active level.
After achieving by the PMCN, the print address output request signal PRREQ is activated.
This is because it is controlled to the active level.       [0025]   Each line feed signal CR, page feed signal CP, print address output request signal PR
REQ and a print output address arithmetic control sequence based on the clock signal CLK.
As shown in FIG. 4, the cans are output after the page break signal CP is activated and the line feed signal CR.
After the active of the Punt output output shown in FIG.
Leslie is formed. That is, the page break signal CP is set to the active level and the horizontal
Direction control flip-flop HCFF and vertical direction control flip-flop VCFF
The print address output request signal PRREQ is
At the active level, one memory size in the frame buffer memory FBM
Gate 1 is opened in the range of the clock and stored in the start address register SA.
The start address data of the relevant page is
The data is stored in the output buffer ABU via the path AU and the address output enable
Page top address data in response to the active level of the
Is stored in the frame buffer memory FBM as the print output address signal PADRS.
Supplied. At this time, the page top address output via the arithmetic circuit AU
Data is transferred to the temporary register via gates G6 and G7 which are controlled to be on.
It is stored in the star TSA and the current address register TA. Such a memory cycle
Each operation sequence in the clock signal is executed according to the cycle of the clock signal CLK.
It is.       [0026]   In the subsequent memory cycle, the horizontal control flip-flop HCFF
And when the vertical control flip-flop VCFF is maintained in the set state
In other words, when the line feed signal CR or the page feed signal CP is set to the active level,
Horizontal control flip-flop HCFF and / or vertical control in response to change
When the flip-flop VCFF is not reset, in each memory cycle
Is the data stored in the current address register TA and the print address increment.
The data stored in the data register PAI is added by the arithmetic circuit AU to the output buffer
The signal is stored in the ABU and the address output enable signal ADRE is activated.
In accordance with the level, the calculated address data is used as a print output address signal.
It is supplied to the frame buffer memory FBM as PADRS. At this time, The addition result address data output via the circuit AU is the current address
It is stored in the register TA. Each operation sequence in each such memory cycle is
, In the same manner as described above in accordance with the cycle of clock signal CLK. Therefore,
Print output address for the first line of the frame buffer memory FBM after a page break
As shown in FIG. 5, the dresses are sequentially SA, SA + PAI, SA + 2PAI.
, SA + 3PAI,...       [0027]   Next, the line feed signal CR is set to the active level, and the horizontal control flip
Only the HCFF is reset, and then the print address output request signal
When the signal PRREQ is set to the active level, the frame buffer memory FBM
Within one memory cycle in the temporary start address register TSA
Address of the page stored in the memory and the size of the memory width register MW.
Is added in the arithmetic circuit AU, and the addition result data (the first address in the second row) is added.
Address data is stored in the output buffer ABU, and the address output enable
In response to the change of the active signal ADRE to the active level,
Data is output as a print output address signal padrs in a frame buffer memory.
Provided to the FBM. At this time, the addition result output via the arithmetic circuit AU
Address data is temporarily stored via gates G6 and G7 which are controlled to be on.
It is stored in the re-register TSA and the current address register TA. Such memory
Each operation sequence in the cycle corresponds to the cycle of the clock signal CLK as described above.
Is performed according to the       [0028]   In the subsequent memory cycle, the horizontal control flip-flop HCFF
And when the vertical control flip-flop VCFF is maintained in the set state
In other words, when the line feed signal CR or the page feed signal CP is set to the active level,
Horizontal control flip-flop HCFF and / or vertical control in response to change
When the flip-flop VCFF is not reset, in each memory cycle
Is the data stored in the temporary address register TA and the print address increment.
And the data stored in the data register PAI are added by the arithmetic circuit AU, and the output buffer Is stored in the ABU and the address output enable signal ADRE is activated.
In response to the change to the print level, the calculated address data is
It is supplied to the frame buffer memory FBM as a dress signal PADRS. this
At this time, the addition result address data output via the arithmetic circuit AU is
Is stored in the address register TA. Each operation cycle in each such memory cycle
The sequence is executed according to the cycle of the clock signal CLK as in the above.       [0029]   Accordingly, the second line of the frame buffer memory FBM after the page break is
The print output address is, as shown in FIG. 5, sequentially SA + MW, SA + M
W + PAI, SA + MW + 2PAI, SA + MW + 3PAI,... Less than
Similarly, the print output address is calculated for the row of.       [0030]   FIG. 6 shows a print output address in the print output address calculation control unit LZCTR.
This figure shows the output timing of the address data.
Output timing depends on the active level of the print address output request signal PRREQ.
The transition to the bell is delayed by one memory cycle. This delay
The number of cycles is based on the laser printer mechanical system LZPMCN and the corresponding print data.
In the case of the characteristic of being changed from 0 to several cycles in relation to the synchronous operation with the
It is.       [0031]   As described above, the address calculation by the print output address calculation control unit LZCTR is performed.
Processing is constant such that it is completely synchronized only with a synchronization signal such as clock signal CLK.
, The line feed signal CR, the page feed signal CP, and the print
Printer output LZPMC based on the address output request signal PRREQ.
It is executed according to the state of N. Therefore, the laser printer mechanical system LZPMCN
Specially requires a dedicated timing adjustment circuit that absorbs state fluctuations
No, print output address according to the status of laser printer mechanical system LZPMCN
The arithmetic control can be easily achieved with a small system configuration.       [0032]   FIG. 7 is a block diagram showing a detailed example of the refresh address generation circuit RFGEN.
FIG.       [0033]   In FIG. 7, RFINT denotes a frame buffer memory F composed of a DRAM.
The refresh interval data required for the BM is stored in the host processor HMP.
A refresh interval register initially set by U. I
TVCNT is an interval timer that always increments by one every memory cycle.
Unta. The count value of this interval counter ITVCNT is
The comparator COMP compares the data with the refresh interval data.
The coincidence detection signal φcomp output from the comparator COMP has an interval
Not only functions as a reset signal for the counter ITVCNT, but also
The refresh count data set in the flash count register NRFR is counted
Function as an instruction signal for preset transfer to the NBRCNT.
Of the refresh control flip-flop circuit RFEXF. Re
The refresh count register NRFR stores
The number of times of fresh data is initially set via the host processor HMPU.
You. According to this embodiment, the refresh count data is four times. Number of cows above
The counter NBRCNT is a down counter and determines whether the refresh count data is "4".
Counts down to “0”, and when the decrement operation reaches “0”.
And the count-up signal φcnt indicating the refresh control flip-flop
This is a reset signal for the circuit RFEXF. Therefore, the refresh interval
From the start point of the file until the count counter NBRCNT is decremented to “0”
The output signal φrfreq of the refresh control flip-flop circuit RFEXF is
The high level is set as the refresh request level.       [0034]   The output signal φrereq is output from the print output address operation control unit LZPCTR.
Print address output instruction signal PASTB (not particularly limited,
, The level change timing of the print address output request signal PRREQ.
And the inverted signal of the signal whose delay has been delayed for a predetermined time) is taken. It is output from the gate AND as a substantial refresh control signal φref.
The refresh control signal φref is a print address output instruction signal PAST
B does not request output of a pudding address in a predetermined memory cycle
Sometimes it is set to a high level as a substantial refresh instruction level. That is,
In each memory cycle of the frame buffer memory, the refresh address
The output operation of the print address has priority over the output operation. Refresh system
The control signal φref is set to a high level as a refresh instruction level
And a predetermined refresh address from the refresh address counter RFADCNT.
Output the address data RFADRS to the address bus ABUS, and output
After the address signal is determined, the refresh control signal φref goes low.
Refresh address counter RFA in response to a memory cycle until
DCNT performs a count operation to output predetermined refresh address data
. Further, the refresh control signal φref has a refresh instruction level of
At a predetermined timing (memory circuit),
(Corresponding to a cycle). Number counter NB
The count operation by RCNT is performed during the high level period of the refresh control signal φref.
All the time, the count operation by the refresh address counter RFADCNT and
They are executed at the same timing. Note that DEL is slow in FIG.
It is an extension circuit.       [0035]   Here, the operation cycle of the laser printer mechanical system LZPMCN is the frame buffer.
Is often slower than the memory cycle of the
The print data read in a cycle is read in words or bytes.
The output timing of the print output address PADRS is shown in FIG.
As shown in FIG. 8, with respect to the memory cycle of the frame buffer memory FBM,
Substantially randomly skipped.       [0036]   For example, as shown in FIG. 8, the refresh interval starts from time t0.
When started, the refresh control flip-flop RFEXF is set to the set state. As a result, the output signal φrfreq changes to a high level as a refresh request level.
Is done. This output signal φrfreq is supplied to the drawing processor DRWPRO,
When it is at the high level as the refresh request level, the drawing pro
The output of the drawing address data DADRS by the processor DRWPRO is prohibited.
In the first memory cycle MC1 after time t0, the print address output is required.
Output request φrfreq and the print address output instruction signal
Refresh control signal φr which is an AND signal with the inverted level signal of signal PASTB
ef is set to the active level, whereby the memory cycle MC1 is
And the refresh address data RFADR is a refresh address counter.
The signal is supplied from RFADCNT to the frame buffer memory FBM.       [0037]   In the next memory cycle MC2, a print address output request is issued.
In response, the print address output instruction signal PASTB is active.
Since the level is set to the high level, the refresh output from the AND gate circuit AND is performed.
The control signal φref is set to the low level, whereby the memory cycle MC
2, the refresh address by the refresh address counter RFADCNT
The output operation of the memory address data RFADR is prohibited, and the frame buffer memory F
The BM has a print address from the print output address operation control unit LZPCNT.
Data PADRS is provided. At this time, the refresh address generation circuit RF
In the GEN, the number of times the refresh control signal φref of the low level
Decrement operation by counter NBRCNT and refresh address count
The update operation of the refresh address by the RFADCNT is prohibited.
The remaining three refresh address output operations in the refresh interval
Is the memory cycle after which no print address output operation is required
To be possible. According to FIG. 8, a print address output operation is required.
In the memory cycles MC3 to MC5 which are not performed, the next refresh
The dress data RFADRS is supplied to the frame buffer memory FBM.       [0038]   In this manner, four refreshes are performed in one refresh interval. After the address data RFADRS is output, the counter NBRCNT is output.
The count-up signal φcnt output from the
The fresh control flip-flop circuit RFEXF is reset. Therefore,
When the count value of the interval counter ITVCNT is
Data and the refresh control flip-flop circuit RFEXF is set again.
Until time t1 when the state is changed to the output signal φ which functions as a refresh request signal.
rfreq is maintained at a low level.       [0039]   The output signal φrfreq is low during a period from the memory cycle MC6 to the time t1.
Level, the print address is output during the memory cycle in between.
In a memory cycle in which no power request is issued (for example, memory cycle MC6),
The output of the drawing address data SADRS by the processor DRWPRO is allowed,
Further, a memory cycle in which a print address output request is issued (for example, a memory circuit).
In the cycle MC7), printing by the print output address calculation control unit LZCTR is performed.
The output operation of the address data PADRS has the highest priority.       [0040]   FIG. 9 shows the relationship between the print address output request signal PRREQ and various address data.
Although the output timing is shown in FIG.
1 when the lint address output request signal PRREQ changes to the active level.
The memory cycle is delayed. This number of delay cycles is
Synchronous operation between the linter machine system LZPMCN and its corresponding print data supply system
Is changed to 0 to several cycles.       [0041]   As described above, the refresh address generation circuit RFGEN operates at a preset location.
Print timing for refresh timing at regular refresh intervals
Laser printer machine by specifying it in relation to the
Relation with print data output address calculation control according to the state of mechanical system LZPMCN
Easily achieve required refresh address output control at specified intervals
To achieve.       [0042]   According to the above embodiment, the following effects can be obtained. (1) The address calculation processing by the print output address calculation control unit LZCTR is as follows.
A fixed time that is completely synchronized only with a synchronization signal such as a clock signal CLK
Line feed signal CR, page feed signal CP, and print address.
The status of the laser printer mechanical system LZPMCN based on the output request signal PRREQ
It is executed according to. Therefore, the state change of the laser printer mechanical system LZPMCN
Without the need for a special timing adjustment circuit to absorb motion.
Print output address calculation control according to the state of the user printer mechanical system LZPMCN
Can be easily achieved with a small system configuration. (2) Due to the above operation and effect, the laser printer print controller LZPCTR
Line breaks and page breaks during normal printing operations, as well as running out of paper and ink
When a page break occurs when such a trouble occurs, the mechanical system
Even if the required initialization timing is often different, the optical system and the photosensitive drum
Status of the laser printer mechanical system LZPMCN that drives the printer and supplies paper
And that the necessary print data must be supplied in accordance with
This can be achieved by a simple circuit configuration. Therefore, laser printer
Compared to a system configuration in which a display controller is used as is for controlling
There is no need for an additional timing adjustment circuit or special control for
Data system can be realized easily and with a simplified configuration. (3) The refresh address generation circuit RFGEN performs a predetermined refresh
The refresh timing in the refresh interval is stored in the print address data.
The laser printer mechanical system LZ
In connection with print data output address arithmetic control according to the state of PMCN
The required refresh address output control can be easily achieved at predetermined intervals.
Can be. (4) The refresh address generation circuit RFGEN operates during the refresh request period.
This is given to the drawing processor DRWPRO to prohibit the output of drawing address data.
And a print address output request is made during the refresh request period. Output of refresh address data is prohibited during printing.
The priority order of the address output in the LZPCTR
Data PASRS> refresh address data RFADRS> drawing address data
Data DADRS can be easily controlled in order. (5) From the above-mentioned respective effects, the laser printer print control device LZPCTR
Output of print address, drawing address, and refresh address as a whole
Force timing control is remarkable according to the state of laser printer mechanical system LZPMCN.
It can be executed easily and reliably. In this regard, the laser printer system
The simplicity and simplification when configuring the system can be realized.       [0043]   Although the invention made by the inventor has been specifically described based on the embodiments,
The present invention is not limited thereto, but may be any seed without departing from the gist thereof.
Needless to say, it can be changed in various ways.       [0044]   For example, the laser printer print control device LZPCTR of the above embodiment is
Buffer memory by the drawing processor DRWPRO built in
, But the present invention is not limited to this.
However, the functional blocks differ from those of the laser printer print controller LZPCTR.
The drawing function is supported by the drawing processor or the host processor.
You may do it. In the above embodiment, the laser printer mechanical system LZPMCN
Line feed signal CR as an instruction signal for instructing the state to the laser printer print control device.
, The page break signal CP, and the print address output request signal PRREQ,
Other Modifiers if the signal is in accordance with the status of the laser printer mechanical LZPMCN
Various signals can be used. Furthermore, laser printer mechanical system LZ
Depending on the configuration of the mechanical drive system of a hard copy device such as PMCN,
The meaning of the signal indicating the state can also be changed.       [0045]   In the above description, the invention made mainly by the inventor has been described based on the background
The case of application to a laser printer system, which is an application field, has been described. The light source is not limited to this, and it is not necessary to use a rotating polygon mirror.
Laser printer having a print head in which laser elements are arranged in a matrix
Non-impact printer using a matrix with a liquid crystal shutter,
Uses an impact printer with a dot matrix printhead.
It can be widely applied to the used image forming system. The present invention, at least,
Access the frame buffer memory that stores data in bitmap format and
It can be applied to the conditions for processing image forming data for hard copy devices.
it can. In that case, the image forming data stored in the frame buffer memory
Is not limited to those that can be directly converted to a video signal.
A format in which a video signal of a pattern such as characters is referred to and converted into a video signal may be used.       [0046]     【The invention's effect】   The effects obtained by typical ones of the inventions disclosed in the present application are simplified.
This is described below.       [0047]   That is, image forming data output is performed at a timing corresponding to the state of the printer mechanical system.
Address control for the printer, so it is dedicated to absorbing the state fluctuation of the printer mechanical system
Printer machine without the need for any timing adjustment circuits or special controls for it
An image can be formed by performing address calculation for print data output according to the system status.
System can be easily realized with a small-scale circuit configuration.       [0048]   The number of refresh addresses output to the frame buffer memory is
While controlling by a predetermined number while counting by the counting means at each fresh interval,
, An output request for image forming data was detected until the count value reached a predetermined value.
When the image forming data output address corresponding to the request is
Since the priority is given to the output, at a predetermined refresh interval set in advance
Refresh timing is specified in relation to the image formation data output request.
The print data output address according to the status of the printer mechanical system.
Refresh control required at specified intervals can be easily performed in connection with arithmetic control. It can be carried out.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a laser printer system according to one embodiment of the present invention. FIG. 2 is a block diagram illustrating an example of a laser printer print control device. FIG. 3 is a block diagram illustrating an example of a print output address calculation control unit. FIG. 4 is an explanatory diagram showing an example of a print address output operation sequence. FIG. 5 is an explanatory diagram showing contents of print output address data sequentially output. FIG. 6 is an explanatory diagram showing output timing of print address data in a print output address calculation control unit. FIG. 7 is a block diagram showing a detailed example of a refresh address generation circuit. FIG. 8 is a time chart illustrating an example of a mutual output timing of a print address, a refresh address, and a drawing address. FIG. 9 is an explanatory diagram showing output timings of a print address output request signal and various address data. [Description of Signs] LZPMCN Laser Printer Machine System FBM Frame Buffer Memory LZRC Laser Controller PADRS Print Output Address Data DADRS Drawing Address Data RFADRS Refresh Address Data LZCTR Print Output Address Operation Controller CP Page Break Signal CR Line Feed Signal PRREQ Print Address Output Request Signal MCCTR printer machine control unit MCTR machine system control signal MSTS machine system status signal HCFF horizontal control flip-flop VCFF vertical control flip-flop SA start address register TSA temporary start address register TA current address register PAI print address increment register RFGEN refresh address Generator RFINTR Fresh interval register ITVCNT interval counter COMP comparator NRFR refresh count register NBRCNT number of times counter RFFEX refresh control flip-flop RFADCNT refresh address counter AND AND gate circuit DRWPRO drawing processor

Claims (1)

Claims 1. An image forming apparatus according to claim 1 , wherein said image forming data is stored in a bitmap format .
A frame buffer memory in which the image forming data is Ru is the refresh control, and the printer machine system for forming an image on a medium in accordance with image formation data to be read from the frame buffer memory, the image forming operation by the printer machine system, printer machine A printer mechanical system control unit that outputs a control signal to the system and receives and controls the status signal of the printer mechanical system, and inputs an instruction signal output from the printer mechanical system control unit according to the operation state of the mechanical system. , One memory of the frame buffer memory included in the instruction signal.
In synchronization with the image forming data output request signal output after a period longer than the recycling time, the address calculation control for reading out the image forming data from the frame buffer memory is performed, and the image forming data output address has priority over the refresh control. An image forming data output address operation control unit that supplies the image forming data to the frame buffer memory and controls reading of the image forming data. 2. A frame buffer memory for storing image forming data in a bitmap format, a printer mechanical system for forming an image on a medium in accordance with image forming data read from the frame buffer memory, and a printer mechanical system. A printer mechanical system control unit that outputs a control signal of the printer mechanical system and receives and controls a status signal of the printer mechanical system, and outputs the image forming operation according to the operating state of the mechanical system from the printer mechanical system control unit. Input an instruction signal, and in synchronization with the instruction signal, perform an address operation control for reading out image formation data from the frame buffer memory, and supply an image formation data output address to the frame buffer memory. An image formation data output address operation control unit for performing read control of The number of outputs of the refresh address sequentially updated to the frame buffer memory is counted by the counting means at each refresh interval, and is controlled at a predetermined number of times. A refresh address generating circuit for, when the arbitration means detects a request for outputting image forming data included in the instruction signal, giving priority to the output of the image forming data output address corresponding to the request to the output of the refresh address. An image forming system, characterized in that: 3. An image forming data output request signal for indicating that an image can be formed by receiving the supply of image forming data, a page break signal according to an operation of changing a medium on which an image is to be formed, and And a line feed signal according to an operation for line feed of an image forming line on the medium. The image forming data output address operation control unit sets the image forming data output address in the frame buffer memory in synchronization with an instruction by the page feed signal. Performs an address operation control for initializing to the head address of the image forming data, performs an operation control for initializing the image forming data output address to the head of the next line in synchronization with the instruction by the line feed signal, and executes the image immediately after the initialization. The initialized image forming data is synchronized with the instruction by the forming data output request signal. Outputting an output address, changing the image forming data output address in the row direction in synchronization with an instruction by the image forming data output request signal after externally outputting the initialized image forming data output address, and outputting the changed address. 3. The image forming system according to claim 1, wherein: 4. The printer mechanical system according to claim 1, wherein a scanning direction of light is a row direction along an axial direction of the photosensitive drum, and scanning by laser light according to the image forming data is repeated as the photosensitive member rotates. The image forming system according to any one of claims 1 to 3, wherein the image forming system is a laser printer mechanical system that forms an electrostatic latent image on a surface of a photoreceptor, visualizes the electrostatic latent image, and obtains a hard copy on a medium. .