JP2702265B2 - Semiconductor storage device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to the operation of a cell information potential difference amplifier circuit.

[Conventional technology]

A conventional amplifying circuit (hereinafter referred to as a sense circuit) for a cell information difference potential generated in a digit of a semiconductor memory device is a second circuit.
As shown in the figure, a Pch flip-flop 8, a sense amplifier digit signal feedback Nch flip-flop 9 and a sense amplifier 10 are provided.

The sense operation control circuit 13 is a P-channel (ch)
A flip-flop activation signal 1, a word line (decoder) activation signal 12, a sense amplifier digit signal feedback Nch flip-flop activation signal 3, a cell digit / sense amplifier digit separation signal 4, and a sense amplifier activation signal 5 are generated. The write control circuit 20 generates a write control signal 18. The data amplifier 16 and the write driver 17 are connected to the I / O bus 14. Row decoder 1
1 is connected to the word line. Column decoder 15
Is connected to the gate of the transistor in the column switch 19.

 Next, the operation will be described.

First, the cell digit 6, the sense amplifier digit 7, the Pch flip-flop activation signal 1, and the sense amplifier digit signal feedback Nch flip-flop activation signal 3 are at 1/2 Vcc level.

First, the word line 2 is selected, and cell information is output to the cell digit 6 and the sense amplifier digit 7. Then, when a sufficient signal amount difference occurs between the pair digits, the sense amplifier activating signal 5 is activated. At that time, the cell digit sense amplifier digit separation signal 4 is changed from high level to low level. This is to increase the amplification speed of the sense amplifier digit 7.

At that time, to transmit the low level to the cell digit 6,
The sense amplifier digit signal feedback Nch flip-flop activating signal 3 is also activated. After that, the Pch flip-flop activation signal 1
Is activated.

Thus, the sensing operation is completed. When writing data to the cell, the column driver 19 is opened by the column decoder 15 and the write control signal 18 becomes high level, thereby activating the write driver 17 and inverting the sense amplifier digit 7, thereby causing the sense amplifier digit signal feedback flip-flop. In step 9, the cell digit 6 is inverted.

 The above is the operation of the conventional sense circuit.

[Problems to be solved by the invention]

However, the conventional sense circuit must invert the Pch flip-flop 8 by the sense amplifier digit signal feedback Nch flip-flop 9 when writing data. It takes time.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor memory device in which the above-mentioned problem is solved and the cell digit can be quickly inverted.

[Means for solving the problem]

The configuration of the present invention is a semiconductor memory device in which a first flip-prop, a pair of cell digits, a second flip-prop, a pair of transfer gates, and a pair of sense amplifier digits are cascaded. The pair of transfer gates respectively connecting the cell digit and the pair of sense amplifier digits are inactivated at the time of sense amplifier amplification by a signal from the sense operation control circuit, and directly at the time of writing by the write signal from the write control circuit. It is characterized by being activated in a controlled manner.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a semiconductor memory device according to one embodiment of the present invention.

In FIG. 1, this embodiment applies a write control signal 18 from a write control circuit 20 and a cell digit / sense amplifier digit separation signal 4 from a sense operation control circuit 13 to a transfer gate 22 via an OR gate 21. doing. Other circuit blocks are the same as in FIG. The Pch flip-flop 8 includes a pair of P-channel MOS transistors, each having a drain connected to the cell digit 6 and a source commonly connected.
The gates are connected to each other drain. Nch flip-flop 9 also includes a pair of N-channel MOS transistors.

The cell digit sense amplifier digit separation signal 4 becomes high level when the write control signal 18 becomes high level.

Until the completion of the sensing operation, the operation is the same as that of the conventional sense circuit. However, at the time of writing, the sense digit / sense amplifier separation signal 4 becomes high level, and the write driver 17 directly inverts not only the sense amplifier digit 7 but also the cell digit 6. .

As described above, in the present embodiment, the drain of a Pch transistor in which the other cell digit 6 is connected to the gate is connected to one cell digit 6 of a pair digit (hereinafter referred to as a cell digit) to which a dynamic cell is connected. ,
The other cell digit 6 has the same configuration, connects its sources to each other, and further gates the digit (hereinafter, referred to as sense amplifier digit 7) in which the other sense amplifier is connected to the paired cell digit. , The drain of the Nch transistor connected to the other, the other sense amplifier digit 7, and the source of those Nch transistors having the same configuration as the cell digit are connected to each other, and the cell digit 6 and the sense amplifier digit 7 are connected to each other. Is provided when the sense amplifier is activated, and is activated when writing.

〔The invention's effect〕

As described above, according to the present invention, since the cell digit / sense amplifier digit separation signal at the time of writing is set to the high level, the writing driver can invert directly to the cell digit, and the time at the time of writing can be shortened. Has an effect.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a semiconductor memory device according to one embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional semiconductor memory device. 1 ... Pch flip-flop activation signal, 2 ... word line, 3 ... sense amplifier digit signal feedback Nch flip-flop activation signal, 4 ... cell digit / sense amplifier digit separation signal, 5 ... sense amplifier activation signal,
6 ... cell digit, 7 ... sense amplifier digit, 8
... Pch flip-flop, 9 ... Sense amplifier digit signal feedback Nch flip-flop, 10 ... Sense amplifier, 11 ... Row decoder, 12 ... Word line (decoder)
Activating signal, 13 ... Sense operation control circuit, 14 ...
... I / O bus, 15 ... column decoder, 16 ... data amplifier, 17 ... write driver, 18 ... write control signal, 19 ... column switch, 20 ... write control circuit, 21 ... OR gate.

Claims (1)

(57) [Claims] 1. A semiconductor memory device in which a first flip-prop, a pair of cell digits, a second flip-prop, a pair of transfer gates, and a pair of sense amplifier digits are cascade-connected. The pair of transfer gates respectively connecting the cell digit and the pair of sense amplifier digits are inactivated at the time of amplification of the sense amplifier by a signal from the sense operation control circuit, and are directly activated at the time of writing by the write signal from the write control circuit. A semiconductor memory device characterized in that the semiconductor memory device is controlled and activated.