JP2700041B2 - Cell switching equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial application field] The present invention divides various information such as voice, data, and image into blocks called cells in the information communication field, and performs high-speed transmission and exchange. ATM (Asynchronous Transf
er Mode) relates to a cell switching device in communication.

[Prior art] ATM (Asynchronous Tr) for high-speed transmission and exchange
In ansfer mode communication, a unit called a cell in which multimedia information is blocked and a header including destination information is added is used. This cell has a fixed length according to the international standard. On the other hand, the interface speed in the ATM communication system is based on 155.52 Mb / s, and some of the speeds of an integer multiple thereof, for example, 62
2.08Mb / s etc. is becoming an international standard.

In an ATM switch that performs switching by directly referring to the header information of a cell by hardware, a cell multiplexing / demultiplexing circuit may be used at the input / output of the ATM switch to accommodate an interface different from the interface of the switch. Many. Figure 9 shows Hayami et al., “ATM for Broadband ISDN.
Switching System ", IEICE Technical Report, Vol.90
It is a block diagram of the prototype system shown in No.158, SSE90-40, pp.13-18, 1990. FIG. 10, FIG. 11, and FIG. 12 are configuration diagrams of an ATM switch module, a cell multiplexing circuit, and a cell separating circuit in the same example. In the figure, (1)
Is the incoming line, (2) is the outgoing line, (3) is the ATM switch, (4)
Is a cell multiplexing circuit, (5) is a cell separation circuit, (6) is an input port, (7) is an output port, (8) is a cell switching device,
(31) is an ATM switch module, (32) is a buffer,
(33) is the highway.

 Next, the operation will be described.

Fig. 9 shows the configuration of the prototype system. In the example shown here, the basic components of the broadband ISDN, the broadband home network, the broadband remote concentrator, and the wideband central office exchange are integrated. Now, a broadband remote concentrator will be described. The communication path of the device is composed of an ATM switch (3), a cell multiplexing circuit (4), and a cell separation circuit (5) in addition to the interface portion. The information generated in the house is divided into blocks of a fixed length to form cells, arrives at the broadband remote concentrator via the optical subscriber line, and is first input to the input port (6) of the cell multiplexing circuit (4). The interface speed of this optical subscriber line is an international standard of 155.52.
Mb / s. On the other hand, the interface speed of the ATM switch (3) is 1.2 Gb / s and cannot accommodate the optical subscriber line directly.
It is possible to accommodate this. Therefore, the cell multiplexing circuit (4) shown in FIG. 11 has eight 155.52 Mb / s input ports (6).
Are multiplexed in cell units, and output to the input line (1) of the ATM switch (3) as one 1.2 Gb / s interface. The cell multiplexing circuit (4) includes an ATM switch module (31) corresponding to the number of input ports. Cell multiplexing temporarily stores cells in a buffer (32) in an ATM switch module (31), and avoids cell collision on the incoming line (1) while coordinating with other ATM switch modules (31). Thus, cell multiplexing is performed by reading cells from the buffer (32) at high speed.

Next, the operation of the ATM switch module will be described with reference to FIG. The ATM communication path has a configuration in which the ATM switch modules (31) are arranged in a grid pattern, and the modules are connected by a 1.2 Gb / s highway (33). 8 ATM switch modules (31) with 1.2Gb / s interface
× 8 exchange is possible. In the ATM communication system, cells are multiplexed aperiodically and input from a plurality of incoming lines toward one outgoing line, so that cell collision on the outgoing line may occur.
In order to avoid this, a function of temporarily queuing cells by a buffer is required. Each ATM switch module (31) is connected to another ATM switch module (31) by an output highway (33), and includes a buffer (32) in each ATM switch module (31). AT
When a cell is input to the M switch module (31), it is determined whether or not switching is performed by comparing the routing information added to the cell with the output highway number set in each ATM switch module (31). If the routing information matches the set highway number, the cell is stored in the buffer (32). When cells are read from the buffer (32), arbitration is required between the ATM switch modules (31), and this multiplexing control is performed by circulating tokens. Also, all
The highway (33) accommodating the cells output from the ATM switch module (31) becomes the light beam (2) and enters the cell separation circuit (5).

Next, the operation of the cell separation circuit will be described with reference to FIG. The cell separation circuit (5) has a function of separating cells into a plurality of output ports (7) for one outgoing line (2). The cell flow arriving at the outgoing line (2) is statistically cell multiplexed, and the cell of each output port destination does not arrive regularly, but its ratio varies with time. Therefore, since the cell separation circuit (5) requires a large number of buffers to absorb the fluctuation, a plurality of ATM switch modules (31) are provided for one output port (7) in FIG. ing. In the figure, the cell is an ATM
When output from the output line (2) of the switch (3) and arrives at the cell separation circuit (5), each ATM switch module (3
1) By looking at the destination of the cell, if the output port (7) matches, the cell is written to the buffer (32). The buffer (32) has a write speed of 1.2 Gb / s, but reads 155.52 Mb / s. Therefore, when a large number of cells to be written arrive continuously, the amount of the buffer (32) is reduced. Since it is finite, the buffer (32) overflows with probability and cell discarding occurs.

[Problem to be Solved by the Invention] Since the conventional cell switching device is configured as described above, a sufficient amount of the cell separation circuit (5) is required to reduce the discard rate in the cell separation circuit (5). In order to prepare the buffers (32), it is necessary to install a large number of buffers (32) corresponding to each output port (7). As a result, it is necessary to install a large number of buffers whose use efficiency is low in the entire system. And it is difficult to realize.

The present invention has been made in order to solve the above-described problems.When reading cells from an ATM switch to a cell separation circuit, the capacity of each output port is taken into consideration so that the capacity does not exceed the capacity of each output port. The purpose of this buffer is to share the buffer in the ATM switch between each output port, improve the buffer utilization efficiency, and reduce the total buffer capacity of the entire system by absorbing the time variation of the ATM switch buffer. And

[Means for Solving the Problems] A cell switching apparatus according to the present invention has a plurality of incoming lines to which cells composed of a data section and a header section including destination information thereof are inputted, and converts a cell inputted from the incoming line to the cell. Output to the outgoing line that accommodates the output port specified in the header section of
An ATM switch, a cell multiplexing circuit that multiplexes cells in a plurality of input ports into which the cells are input in cell units, and outputs the cells to the input line, and a cell in the output line specified in the header unit in cell units. A cell switching device having a cell separation circuit for selecting and outputting an output port, wherein the ATM switch includes a header processing circuit for detecting a destination output port from a header portion of a cell input from an input line, and an address. One or a plurality of buffer memories capable of reading the cells irrespective of the order of writing by specifying the address, and writing the cells by specifying an address; And a cell write circuit for writing cells to the buffer memory by connecting the buffer memory to a predetermined output line. A cell read circuit for reading cells from the memory and a cell write circuit are controlled to select a buffer memory to which the cells are written, and the addresses of the written cells in the buffer memory are managed for each destination output port of the cells. The cell readout circuit is controlled based on the address managed for each destination to read out the cell in accordance with the speed of the output port, and the read out cell is placed on an output line accommodating the output port specified by the header portion. And a buffer control circuit for outputting in order.

[Operation] The cell exchange device according to the present invention manages the storage address of the cell in the buffer memory for each output port in the ATM switch, and does not exceed the capacity of the output port when reading the cell from the buffer memory. ATM eliminates cell waste in separation circuits and absorbs cell fluctuations
By using the buffer memory in the switch, the buffer memory can be shared and used by all output ports, and a lower cell discard rate can be realized with a smaller number of buffer memories in the entire system.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is an overall configuration diagram showing a cell switching device according to the present embodiment. This cell switching device (8) exchanges cells between 32 input ports (6) of 155.52 Mb / s for inputting cells and 32 output ports (7) of 155.52 Mb / s for outputting cells. Is what you do. In addition, this cell switching device (8)
Connects the 155.52Mb / s input port (6) to one 622.08Mb / s
ATM switch (3) that accommodates eight incoming lines (1) and eight outgoing lines (2) with 622.08 Mb / s interface and eight cell multiplexing circuits (4) that multiplex cells into incoming line (1) And 1
Eight cell separation circuits (5) for separating cells from the 622.08 Mb / s output line (2) to five 155.52 Mb / s output ports (7) are provided.

FIG. 2 shows an embodiment of the ATM switch (3). In the figure, (1) is n (n ≧ 2) input lines in which input ports to which cells composed of a header part and a data part including an output port number as destination information are input are multiplexed, and (2) is the cell Accommodates an output port to be output according to the destination specified in the header section.
(M ≧ 2) outgoing lines, which are equivalent to conventional ones. Reference numeral (10) denotes a header processing circuit provided corresponding to each of the input lines (1) and detecting a destination output port (7) from a header portion of a cell input from the input line (1). Also, (11) stores p (p ≧ 1) p (p ≧ 1) cells in which the cells can be stored at a specified address and the stored cells can be read by specifying the address, regardless of the order at the time of writing. It is a buffer memory. (12) is provided corresponding to each of the buffer memories (11),
For example, it is a storage control circuit that manages free addresses using a FIFO type memory and gives a read address and a write address to the associated buffer memory (11). (13) a cell write circuit for selectively connecting the header processing circuit (10) to a predetermined buffer memory (11), which is realized by a space switch in this embodiment. (14) is a cell readout circuit for selectively connecting each buffer memory (11) to a predetermined output line (2), and is realized by a space switch in this embodiment. (15) controls the switching of the cell write circuit (13) to select the buffer memory (11) in which the cells are stored, and to change the address of the stored cells in the buffer memory (11) into each cell. The output port is controlled for each output port, and controls the switching of the cell readout circuit (14) based on the address managed for each destination. This is a buffer control circuit for outputting the signal to the line (2) in a predetermined order.

In the buffer control circuit (15), (1
6) When a cell arrives at the incoming line (1), the incoming line (1)
Receiving the outgoing line number of the cell detected by the header processing circuit (10) provided correspondingly to the buffer memory (11) for storing the cell, and selecting the buffer memory (11) for the corresponding header processing circuit (10). And a write buffer selection circuit for controlling the switching of the cell write circuit (13). (17) refers to the output port number detected by the write buffer selection circuit (16), classifies the arriving cell by destination output port, and determines the write address in the buffer memory (11) where the cell has been written. An address exchange circuit which is obtained from a storage control circuit (12) corresponding to the buffer memory (11) and writes it to an address queue described later. (18) is an address queue, which is constituted by a FIFO type memory, and is provided corresponding to an output port accommodated in each of the outgoing lines (2). In the address queue (18), for each output port associated with the address queue, a write address in the buffer memory (11) in which cells destined for the output port are stored is stored in the order of arrival. Switching circuit (17)
Written by (19) determines the cell to be read from the buffer memory (11) by referring to the address queue (18), and stores the address read from the address queue (18) as a read address in the corresponding buffer memory (11). A read buffer selection circuit that sends the data to the associated storage control circuit (12), controls the switching of the cell read circuit (14), and connects the buffer memory (11) to the corresponding outgoing line (2). .

FIG. 3 shows an example of the internal circuit of the cell multiplexing circuit. In FIG. 1, four 155.52 Mb / s input ports (6) are connected to one 622.08.
This is an example in which cells are multiplexed on the incoming line (1) of Mb / s. In the figure, a cell speed adjusting buffer (21) composed of one FIFO type memory is used corresponding to the input port (6), and writing is performed at 155.52 Mb / s and reading is performed at 622.08 Mb / s sequentially. I have.

FIG. 5 shows an example of the internal circuit of the cell separation circuit. In FIG. 1, one 622.08 Mb / s output line (2) is separated into four 155.52 Mb / s output ports (7). is there. In the figure, a cell rate adjusting buffer (23) and an address filter (22) each composed of one FIFO type memory corresponding to the output port (7) are used, and the writing is 622.08 Mb / s and the reading is 155.52 Mb. / s. Cell rate adjustment buffer (2
1) and (23) are for speed adjustment only and do not expect the statistical multiplexing effect of cells, so their capacity is at most 2
About a cell is sufficient.

Next, the operation of the cell multiplexing circuit will be described. The cell length handled here is a fixed length and is randomly input. The cell input phase is adjusted before inputting to the input port (6), and the cell input from all lines is supplied with the same phase. Shall be. FIG. 4 is a timing chart of this circuit example, in which the input port (6) in FIG.
And B are shown in cell units. In the ATM communication system, a significant cell may come in a certain time slot, or an idle cell (empty cell) having no information may come. In the figure, significant cells are indicated by “cells” and the like, and idle cells (empty cells) are specified as “idle cells”. One cell transfer time at 622.08 Mb / s is 155.52 Mb / s
And has a capacity to accommodate all cells input from the input port (6) in the input line (1). Here, one cell time at 155.52 Mb / s is used as a unit, and 622.08
In this method, four Mb / s cells are fixedly assigned to the input port (6) at the time position. For example, a cell input from the input port (6) of # 1 has 62 cells at the position of # 1 in the figure.
Output as 2.08Mb / s.

Next, the operation of the ATM switch will be described with reference to FIG. Here, it is assumed that the input phase of the cell at each input line (1) input to the switch is adjusted and the same. When a cell is input to the incoming line (1), a header processing circuit (10) provided corresponding to each incoming line (1) detects an output port and an outgoing line number for accommodating the output port from the header portion of the input cell. . The write buffer selection circuit (16) in the buffer control circuit (15) refers to the header processing circuit (10) and sends the header processing circuit (10) and the cell where the cell has arrived to the cell writing circuit (13). An instruction is given to individually connect the buffer memory (11) selected for storage.
The write address used at this time is obtained by referring to the storage control circuit (12). This write address is sent to the address exchange circuit (17) and is divided according to the destination output port (7) of the cell arriving at each incoming line (1). An address queue (18) is provided for each output port, and the write address and buffer memory number of the cell are written at the end thereof. The read buffer selection circuit (19) takes out the address stored in the address queue (18), sends it to the storage control circuit (12) corresponding to the buffer memory (11), and reads the cell. Buffer memory (1
An instruction is given to connect 1) and the outgoing line (2) individually.
In general, the capacity of the outgoing line (2) is different from the capacity of the output port (7). However, since the reading of the address queue (18) is performed for each output port, the output is performed by reading according to the speed of the output port. Do not exceed the capacity of port (7). The cell readout circuit (14) connects the buffer memory (11) and the outgoing line (2) in this time slot. Each storage control circuit (12) sends the received address to the associated buffer memory (11) as a read address, and thereafter manages that address as a free address. The cells read from each buffer memory (11) are output to the outgoing line (2) accommodating the destination output port (7) specified in each header section.

Here, FIGS. 7 and 8 are examples showing in detail the reading of the address queue (18) for the outgoing line # 1 (2). Outgoing line # 1 (2) is 155.52 Mb / s output port # 1
# 4 (7), so it has a speed of 622.08 Mb / s. FIG. 7 shows an example of an address queue (18) corresponding to the output ports # 1 to # 4 (7) in a certain time slot. The stored buffer memory number and address are written. FIG. 8 shows the rules for reading the address queue (18) in the present invention. This figure shows the timing at the outgoing line (2), which is different from the prior art in that cells destined for the output ports # 1 to # 4 (7) are fixedly assigned in units of four cells. For example, in the figure, time slots 1 to 4 are assigned to output ports # 1 to # 4 (7), respectively, and this is repeated. Therefore, only the speed adjustment needs to be performed regularly in the cell separation circuit (5), and cell loss due to buffer overflow in the cell separation circuit (5) does not occur. For example,
In FIG. 7, a cell 11 is destined for output port # 1, a cell 21 is destined for # 2, and a cell 41 is destined for # 4. Therefore, they are read out regularly in time slots 1, 2, and 4. In time slot 3, since no cell addressed to output port # 3 has arrived, an idle cell (specified as "empty cell" in the figure) is transmitted. In the example of the present invention, the address queue (18) is provided corresponding to the output port (7), but in the conventional example, it is considered that there is one large queue for the outgoing line (2). If this example is applied, other significant cells are output in time slot 3, so that no empty cells are output, and output ports # 1, # 2,
Any one of # 4 will be duplicated and needs to be buffered in the cell separation circuit (5). That is, in the conventional example, a statistical fluctuation occurs in the arrival of cells with respect to one output port (7), and a large amount of buffers is required in the cell separation circuit (5).

Next, the operation of the cell separation circuit will be described. FIG. 6 is a timing chart in this circuit example, in which the outgoing line (2) in FIG. 5 is C and the output port (7) is D, and each is shown in cell units. In the figure, similar to FIG. 4, significant cells are indicated by “cells” and the like, and idle cells (empty cells) are specified as “idle cells”. One cell transfer time at 622.08 Mb / s is one quarter that of 155.52 Mb / s. ATM
Outgoing line (2) transmitted from switch (3) is 622.08 Mb / s
Where 1 cell time at 155.52 Mb / s is the unit,
Since four cells of 622.08 Mb / s are fixedly assigned to the output port (7) at the time position, the cell input to the cell separation circuit (5) must be the output port (7) to be output and the time slot. Is guaranteed so that buffer overflow does not occur here. The cell input to the cell separation circuit (5) is first broadcast to an address filter (22) provided corresponding to the output port (7), and the address filter (22) corresponding to the corresponding output port (7). Only pass through the cell and adjust the speed buffer (2
Write in 3). The other address filter (22) discards the cell. The cell speed adjustment buffer (23) adjusts the speed by performing writing at 622.08 Mb / s and performing reading at 155.52 Mb / s. Since the cell rate adjustment buffer (23) is intended only for rate adjustment and does not expect the effect of statistical multiplexing of cells, a capacity of at most about two cells is sufficient.

In the above-described embodiment, a single cell switching device is shown. However, the cell switching devices may be connected in a link and sequentially connected in multiple stages for expansion.

Although the output port number is directly given as the destination information of the header part of the cell corresponding to the output port of the cell switching device, some conversion processing such as giving a coded number to the destination information of the header part is performed. May go.

Further, in the above-described embodiment, the case where one cell is output to only one output port has been described, but it is also possible to output to a plurality of output ports depending on the way of specifying an address. An information function can be added.

Alternatively, the header section and the data section may be separated from each other and transmitted using circuits of different speeds, and the header section and the data section may be respectively assigned to a plurality of signal lines arranged in parallel.

Further, in the above embodiment, the link speed of the incoming line was set to be the same, but traffic focusing is possible by making the reading speed from the buffer memory faster than the link speed of the incoming line. It is also possible to make it faster than the speed. Further, when the cell switching devices are linked, by setting the speed between the stages higher than the speed of the incoming line, the cell loss rate between the cell switching device stages can be further reduced.

In the above embodiment, one address queue is provided for each output port of the cell switching device.
A plurality of address queues are provided for each output port for each priority, and a cell having a higher priority is first read out from the buffer memory based on a code indicating the priority added to the header of the cell other than the destination outgoing line. It is also possible.

Further, when a restriction on the operation speed is required, a serial / parallel conversion circuit and a parallel / serial conversion circuit may be provided at the front and rear stages of the switch to process the signals as parallel signals.

[Effects of the Invention] As described above, according to the present invention, a plurality of cells input from a plurality of input ports are multiplexed by a cell multiplexing circuit.
When the cells are exchanged by the ATM switch and the cells are output to the outgoing line, the time slots output by the cells are fixedly assigned to the output ports, and the cells are not discarded due to buffer overflow in the cell separation circuit. When outputting cells from the ATM switch to the cell separation circuit, it is possible to prevent the capacity of each output port from being exceeded, and to absorb the time variation of cell arrival by the buffer of the ATM switch, There is an effect that a buffer in the ATM switch is shared between the output ports and used, so that the buffer use efficiency is improved, and a cell switching device capable of realizing a low discard rate with a small total buffer amount in the entire system is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an entire cell switching device according to an embodiment of the invention, FIG. 2 is a block diagram showing an ATM switch thereof, FIG. 3 is a diagram showing an example of an internal circuit of a cell multiplexing circuit, FIG.
FIG. 5 is a timing diagram of each unit, FIG. 5 is a diagram showing an example of an internal circuit of the cell separation circuit, FIG. 6 is a timing diagram of each unit, FIG. 7 is a diagram showing an example of an address queue in the ATM switch. FIG. 8 is a timing diagram of the outgoing line, FIG. 9 is a system configuration diagram using a conventional cell switching device, FIG. 10 is a block diagram showing a configuration of an ATM switch module in a conventional example, and FIG. 11 is a conventional example. And FIG. 12 is a block diagram showing a configuration of a conventional cell separation circuit. (1) is incoming line, (2) is outgoing line, (3) is ATM switch,
(4) is a cell multiplexing circuit, (5) is a cell separation circuit, (6)
Is an input port, (7) is an output port, (8) is a cell switching device, (10) is a header processing circuit, (11) is a buffer memory, (12) is a storage control circuit, (13) is a cell writing circuit, (14) a cell readout circuit, (15) a buffer control circuit, (16) a write buffer selection circuit, (17) an address exchange circuit, (18) an address queue, (19) a read buffer selection circuit, (21) and (23) are cell rate adjustment buffers, and (22) is an address filter. In the drawings, the same reference numerals indicate the same or corresponding parts.

 ──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-2-113750 (JP, A) JP-A-4-98938 (JP, A) JP-A-63-67848 (JP, A) JP-A-61-67 189098 (JP, A) IEICE technical report SS E90-35

Claims (1)

(57) [Claims] 1. A cell comprising a data portion and a header portion including destination information thereof has a plurality of input lines, and a cell input from the input line accommodates an output port specified by a header portion of the cell. An ATM switch for outputting to an outgoing line, a cell multiplexing circuit for multiplexing cells in a plurality of input ports into which the cells are input in cell units and outputting to the incoming line, A cell separation device for selecting and outputting an output port specified by a header part, wherein the ATM switch detects a destination output port from a header part of a cell input from an incoming line. Circuit and
By designating an address, the cell is written. By designating an address, one or a plurality of buffer memories from which cells can be read irrespective of the order of writing, Controlling a cell writing circuit connected to a buffer memory and writing cells to the buffer memory; a cell reading circuit connecting the buffer memory to a predetermined output line and reading cells from the buffer memory; and a cell writing circuit. The buffer memory in which the cell is written is selected, the address of the written cell in the buffer memory is managed for each destination output port of the cell, and the cell readout circuit is controlled based on the address managed for each destination to store the cell. Reads data according to the output port speed, and reads the read cells Cell switching apparatus characterized by comprising a buffer control circuit for outputting in a predetermined order to output lines to accommodate the output ports specified by the reader unit.