JP2699831B2 - Clock distribution circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock distribution circuit capable of adjusting clock skew (clock time lag) and clock propagation delay time in a clock circuit system such as a semiconductor integrated circuit.

[0002]

2. Description of the Related Art Conventionally, as this kind of technique, there has been a technique described in, for example, "Clock Distribution Circuit" (Japanese Patent Laid-Open No. 4-326411). In this method, as shown in FIG. 2, one clock driver 41-1 to 41-n is allocated to each circuit block 50-1 to 50-n, and a metal wiring 61 from each clock driver to a corresponding circuit block. The clock skew was adjusted only by adjusting the wiring width in -1 to 61-n.

[0003]

However, the above-described clock distribution circuit has the following problems.

In a current LSI, a plurality of synchronous circuits are provided in a circuit block connected to one clock output circuit, and are often supplied with the same clock. In this case, as shown in FIG. 3, the metal wiring 61-1 branches inside the circuit block 50-1, and a plurality of synchronous circuits 65-1
-1, 65-2,. . . Connected to. At that time, there is a problem that a difference in propagation delay time in a circuit block occurs due to a difference in a wiring length, a wiring width after branching, and a load capacitance in a connected clock input element, and it is impossible to finely adjust a clock skew. Further, the above-described clock distribution circuit has a problem that the clock propagation delay time of the entire clock distribution circuit cannot be finely adjusted. Therefore, a clock distribution circuit which is technically satisfactory has not been provided yet.

An object of the present invention is to provide a clock distribution circuit which solves the problem of the prior art that the fine adjustment of clock skew and clock propagation delay time cannot be performed.

[0006]

A clock distribution circuit according to the present invention distributes a clock signal output from a clock output circuit to two synchronous circuits via a plurality of metal wirings and one wiring branch point. In the circuit, the meta
The wiring included in the clock output circuit is determined.
Characteristics of the slave, load capacity of the synchronous circuit,
Clock propagation delay time and wiring capacitance of the metal wiring
Clock skew is adjusted based on
The wiring branch point so as to minimize the lock propagation delay time
And simultaneously adjust the width of the metal wiring.
It is characterized by having done. Further, the clock distribution circuit according to the present invention is a clock distribution circuit which distributes a clock signal output from a clock output circuit to a plurality of synchronization circuits via a plurality of metal wirings and a plurality of wiring branch points. select two synchronization circuits from the metal
An element which determines a wiring position and is included in the clock output circuit
Characteristics, load capacity of the synchronous circuit,
Clock propagation delay time and the wiring capacitance of the metal wiring
The clock skew is adjusted based on the wiring resistance,
And the wiring branch point so as to minimize the clock propagation delay time.
And the wiring width of the metal wiring are adjusted at the same time.
Group of synchronous circuits as one synchronous circuit
By repeating the adjustment for the
Determine the position of the wiring branch point and the wiring width of the metal wiring
It is characterized by having such a configuration .

[0007]

FIG. 4 shows an example in which the internal clock skew has been adjusted.
5 shows a clock distribution circuit according to the present invention in a case where the number of synchronization circuits is one. When the clock is output from the clock output circuit 60, the clock is distributed to the synchronization circuits 65 and 66 via the metal wirings 61, 62 and 63 and the wiring branch point 64. Thus, each synchronization circuit executes a predetermined operation synchronized with the clock.

In this case, the metal wirings 61, 62, and 63 are determined based on the wiring capacitance and wiring resistance of the metal wirings 61, 62, and 63, the characteristics of the elements in the clock output circuit 60, and the load capacitance of the elements in the synchronization circuits 65 and 66. The propagation delay time is obtained, and the propagation delay time of the metal wiring 62 and the synchronization circuit 65 are determined.
The sum of the internal clock propagation delay times is equal to the sum of the propagation delay time of the metal wiring 63 and the clock propagation delay time inside the synchronization circuit 66, and the clock propagation delay time in the entire clock distribution circuit is shortened. Wiring branch point 64
Skew and clock propagation delay time in the entire clock distribution circuit including the synchronous circuit can be finely adjusted by adjusting the position of the metal wiring 61, 62, 63, the wiring length and the wiring width. Becomes

Here, the characteristics of the elements in the clock output circuit are β, the power supply voltage is VDD, and the clock output circuit includes a synchronous circuit of load capacitance C and internal clock propagation delay time t whose clock skew has been adjusted. The delay time td of the entire clock distribution circuit when connected is represented by parameter a
Using 1, a2 and a3,

[0010]

(Equation 1)

The estimation is as follows. At this time, the unit wiring capacitance of the metal wirings 61, 62, 63 is c, the unit wiring resistance is r, the characteristics of the elements in the clock output circuit 60 are β, the load capacitances of the elements in the synchronization circuits 65, 66 are C1, C
2. The internal clock propagation delay times are t1, t2,
The minimum wiring width that can be used is wmin, and the synchronization circuits 65 and 66
When the distance between the clock input terminal positions is 1, the clock widths w1 and w2 of the metal wirings 62 and 63 that eliminate clock skew and shorten the clock propagation delay time of the entire clock distribution circuit are determined by using a parameter R.

[0012]

(Equation 2)

And the wiring lengths l1 and l2 at that time
Is

[0014]

(Equation 3)

## EQU1 ##

When there are three or more synchronous circuits, the clock distribution circuit having two synchronous circuits is used repeatedly. Here, consider the clock output circuit 60 and n synchronous circuits whose internal clock skew has been adjusted. FIG.
Is a diagram showing a case where n = 8, and eight synchronous circuits 65-.
1 to 65-8. At this time, the position of the wiring branch point, the position of the metal wiring, and the position of each of the metal wirings are determined by using the above-described method having two synchronization circuits for two of the n synchronization circuits. The wiring length and the wiring width for are determined. In the example of FIG. 5, two synchronous circuits 65-1, 65-2
, The position of the wiring branch point 64-1, the metal wiring 62-
1, 62-2, the wiring length and the wiring width for each metal wiring are determined.

At this time, the metal wirings 62-1, 62-
2. Circuit 65-9 including synchronization circuits 65-1 and 65-2
Is a synchronous circuit whose clock skew has been adjusted using the wiring branch point 64-1 as a clock input. Two synchronous circuits 6
By considering the synchronization circuit 65-9 as one new synchronization circuit instead of 5-1 and 65-2, FIG. 5 shows that the clock output circuit 60 and the internal clock skew are adjusted as shown in FIG. There are (n-1) synchronized circuits. Therefore,
By repeating this operation, the clock output circuit 60 and the two synchronous circuits are finally obtained, and the entire clock distribution circuit is obtained by using the method in the case of having two synchronous circuits. Various clock distribution circuits can be realized from the same clock output circuit and the plurality of synchronization circuits according to the order of selecting two synchronization circuits from the plurality of synchronization circuits. However, in any case, the clock skew and the clock propagation delay time in the entire clock distribution circuit including the synchronization circuit can be finely adjusted. FIG. 1 shows an example of the clock distribution circuit of the present invention obtained from the clock output circuit 60 and eight synchronous circuits shown in FIG.

As described above, the clock distribution circuit of the present invention can finely adjust the clock skew and the clock propagation delay time in the entire clock distribution circuit including the synchronous circuit, and can reduce the timing margin for the malfunction of the LSI. Improvement can be achieved. Therefore, the above problem can be solved.

[0019]

FIG. 7 shows a first embodiment of the present invention.

In the example of FIG. 7, a clock output circuit 60,
Two flip-flops 85 and 86 are provided as synchronization circuits. First, the flip-flops 85 and 86 are connected by the metal wiring 69. When the wiring branch 64 is determined on the metal wiring 69, the metal wiring 69 is connected to the metal wiring 62 connecting the flip-flop 85 and the wiring branch 64, and the flip-flop 86 and the wiring branch 64.
Are divided into metal wirings 63 connecting the lines, and the lengths of the respective wirings are determined.

At this time, from the characteristics of the elements in the clock output circuit 60, the wiring capacitance and the wiring resistance of the metal wirings 62 and 63, and the load capacitance of the flip-flops 85 and 86, the propagation delay time of the metal wiring 62 and the metal wiring 63 The wiring width of the metal wirings 62 and 63 can be determined so that the propagation delay time becomes equal. FIG. 8 shows a metal wiring 62,
FIG. 14 is a diagram showing an example of the dependence of the propagation delay time, which is important when determining the wiring width of 63, on the wiring width. The wiring capacitance is proportional to the wiring width, and the wiring resistance is inversely proportional. Since the propagation delay time is an increasing function for both the wiring capacitance and the wiring resistance, the optimum value of the wiring width is determined. In the example of this figure, when the wiring width of the metal wiring 62 is 1 μm and the wiring width of the metal wiring 63 is 2 μm, the propagation delay time can be equalized, the clock skew can be eliminated, and the propagation delay time can be minimized. can do.

This propagation delay time depends on the position of the wiring branch point 64 on the metal wiring 69. FIG. 9 is a diagram illustrating an example of a change in the propagation delay time when the wiring branch point 64 moves on the metal wiring 69 from the flip-flop 85 to the flip-flop 86. Since the propagation delay time increases in proportion to the square of the wiring length, the point where the wiring length is distributed to the metal wirings 62 and 63 in a well-balanced manner minimizes the propagation delay time. Therefore, there is an optimum position on the metal wiring 69 so as to minimize the propagation delay time. In the example of this figure, the wiring branch point 64 is
When placed at a position of μm, the propagation delay time can be minimized.

Further, the propagation delay time depends on the length of the metal wiring 69. The length of the metal wiring 69 that can be realized is limited by the conditions such as the positional relationship between the two flip-flops 85 and 86, the wiring method, and obstacles on the LSI.
FIG. 10 shows an example of the dependence of the propagation delay time on the length of the metal wiring 69. Since the propagation delay time is an increasing function with respect to the wiring length, the shortest achievable wiring length is the wiring length that minimizes the propagation delay time. In the example of FIG. 10, the propagation delay time can be minimized by setting the length of the metal wiring 69 to 30 μm.

The method for realizing the metal wiring 69 having a certain length is not generally one. FIG. 11 shows wiring examples 69-1, 69-2, 69-3 of metal wiring having the same length in a wiring method using only horizontal and vertical lines, and the position 64- of the wiring branch point 64 in each case. 1,64-2,6
4-3 is shown. The propagation delay time is minimized when the wiring branch point 64 is set to be closest to the clock output circuit 60. In the case of FIG. 11, 64-1 is an example, and the metal wiring 69 is set at the position of 69-1. Thereby, the wiring length of the metal wiring 61 connecting the clock output circuit 60 and the wiring branch point 64 is determined.

Finally, the wiring width of the metal wiring 61 is determined. Since the propagation delay time and the wiring width have a relationship as shown in FIG. 8, the wiring width of the metal wiring 61 can be selected so as to minimize the propagation delay time.

As described above, in the first embodiment, the clock skew and the clock propagation delay time are adjusted by adjusting the position of the wiring branch point 64, the positions of the metal wirings 61, 62 and 63, the wiring length and the wiring width. It can be finely adjusted. Therefore, it is possible to improve the timing margin with respect to the malfunction of the LSI.
I can be speeded up.

FIG. 12 shows a second embodiment of the present invention.
In the second embodiment, instead of the two flip-flops 85 and 86 in the first embodiment, two synchronous circuits 65 and 66 are used which are connected to two clock drivers and whose internal clock skew is adjusted. In the first embodiment, the clock skew can be eliminated by making the propagation delay times of the metal wirings 62 and 63 equal, but in the second embodiment, the propagation delay time of the metal wiring 62 and the synchronization circuit 65 are eliminated. The clock skew can be eliminated by making the sum of the clock propagation delay time and the sum of the propagation delay time of the metal wiring 63 and the clock propagation delay time of the synchronization circuit 66 equal. Therefore, it is easy to extend the method of the first embodiment to the second embodiment.

FIG. 13 shows a third embodiment of the present invention.
In the third embodiment, two synchronous circuits 65 and 66 whose internal clock skew has been adjusted are used instead of the two flip-flops 85 and 86 in the first embodiment. This synchronization circuit is the most general concept including the flip-flop in the first embodiment and the synchronization circuit connected to the clock driver in the second embodiment. Third
In this embodiment, the clock skew and the clock propagation delay time can be finely adjusted by the same method as in the second embodiment.

FIG. 1 shows a fourth embodiment of the present invention. In the fourth embodiment, n synchronization circuits are provided.
8, and has synchronization circuits 65-1 to 65-8. In this case, a method similar to that of the third embodiment is repeatedly used. In the example of FIG. 1, first, two synchronization circuits 65-
The metal wires 69-1 connecting the wires 1 and 65-2 are drawn, and the wire lengths and wire widths of the metal wires 62-1 and 62-2 are determined according to the procedure of the above embodiment. At this time, the metal wiring 69-
1. The position of the wiring branch point 64-1 is not unique, but they are not determined here but will be determined later. here,
Metal wirings 62-1, 62-2, synchronization circuits 65-1, 6
The circuit composed of 5-2 is regarded as a synchronization circuit 65-9 that newly receives the wiring branch point 64-1.

In the example shown in FIG. 1, the synchronization circuits 65-9, 6
The metal wiring 69-2 connecting 5-3 is drawn, and the metal wiring 6
The wiring length and the wiring width of 2-3 and 62-4 are determined according to the procedure of the above embodiment. At this time, the positions of the metal wiring 69-1 and the wiring branch point 64-1 are determined such that the wiring branch point 64-1 comes closest to the synchronization circuit 65-3.

The above operation is repeated (n-1) times to determine the wiring length and wiring width of the metal wirings 62- (2n-3) and 62- (2n-2). Then, the wiring branch point 64- (n-
The metal wiring 69- (n-1) is determined so that 1) is closest to the clock output circuit 60, and the metal wiring 61 connecting the clock output circuit 60 and the wiring branch point 64- (n-1) as in the above embodiment. Wiring length and wiring width are determined. As described above, even when three or more synchronous circuits exist, the positions of the wiring branch points 64-1 to 64- (n-1) and the metal wiring 6
The clock skew and the clock propagation delay time can be finely adjusted by adjusting the positions of 1, 62-1 to 62- (2n-2), the wiring length, and the wiring width.
Therefore, the timing margin can be improved with respect to the malfunction of the LSI, and the speed of the LSI can be increased.

[0032]

As described above in detail, according to the present invention, the characteristics of the elements included in the clock output circuit, the load capacitance in the synchronous circuit, the clock propagation delay time in the synchronous circuit, and the wiring capacitance of the metal wiring And adjusting the clock skew and the clock propagation delay time by changing the positions of the plurality of metal wirings, the positions of the plurality of wiring branch points, and the wiring length and width of each metal wiring based on the propagation delay time obtained from the wiring resistance. With the configuration, the clock propagation delay time is made equal among all the synchronous circuits in the clock distribution circuit,
In addition, by adjusting the position of the metal wiring, the position of the wiring branch point, and the wiring length and width of each metal wiring so as to shorten the clock propagation delay time, the clock skew and the clock propagation delay time can be finely adjusted. Therefore, unlike the related art, it is possible to solve the disadvantage that the clock skew cannot be finely adjusted between the synchronous elements and the clock propagation delay time cannot be adjusted, and the timing margin can be improved with respect to the malfunction of the LSI. Higher speed can be achieved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of a clock distribution circuit according to the present invention when there are eight synchronous circuits.

FIG. 2 is a configuration block diagram showing a conventional clock distribution circuit.

FIG. 3 is a diagram showing the inside of a circuit block in FIG. 2;

FIG. 4 is a configuration block diagram of a clock distribution circuit of the present invention when there are two synchronization circuits.

FIG. 5 is a diagram showing a clock output circuit and eight synchronization circuits.

FIG. 6 is a diagram showing a connection of two synchronous circuits in FIG. 5;

FIG. 7 is a block diagram showing a configuration of a clock distribution circuit according to the first embodiment of the present invention.

FIG. 8 is a diagram showing the propagation delay time and the wiring width dependency in FIG. 7;

9 is a diagram showing the propagation delay time and the wiring branch point position dependence in FIG. 7;

FIG. 10 is a diagram showing the propagation delay time and the wiring length dependency in FIG. 7;

FIG. 11 is a diagram illustrating an example of a wiring having an equal starting point and an equal wiring length.

FIG. 12 is a block diagram showing a configuration of a clock distribution circuit according to a second embodiment of the present invention.

FIG. 13 is a block diagram showing a configuration of a clock distribution circuit according to a third embodiment of the present invention.

[Explanation of symbols]

 41-1 to 41-n Clock Driver 50-1 to 50-n Circuit Block 60 Clock Output Circuit 61, 61-1 to 61-n Metal Wiring 62, 62-1 to 62- (2n-2) Metal Wiring 63 Metal Wiring 64, 64-1 to 64- (n-1) Wiring branch point 65, 65-1 to 65- (2n-1), 66 Synchronous circuit 69, 69-1 to 69- (n-1) Metal wiring 85 , 86 flip-flop

Claims (2)

(57) [Claims] 1. A clock distribution circuit for distributing a clock signal output from a clock output circuit to two synchronous circuits via a plurality of metal wirings and one wiring branch point, wherein said metal wiring position is determined, Included in output circuit
Characteristics of the device, load capacitance of the synchronization circuit,
Clock propagation delay time inside the circuit and the metal wiring
Clock skew is adjusted based on wiring capacitance and wiring resistance
And the above-mentioned arrangement so as to minimize the clock propagation delay time.
Simultaneously adjust the line branch point and the wiring width of the metal wiring
A clock distribution circuit having a configuration as described above . 2. A clock distribution circuit for distributing a clock signal output from a clock output circuit to a plurality of synchronization circuits via a plurality of metal wirings and a plurality of wiring branch points, wherein the plurality of synchronization circuits include two synchronization circuits. Select the above
Determine the metal wiring position and include it in the clock output circuit.
Characteristics of the element, the load capacitance of the synchronous circuit, the synchronous circuit
Internal clock propagation delay time and wiring of the metal wiring
Clock skew is adjusted based on capacitance and wiring resistance
The wiring so as to minimize the clock propagation delay time.
Adjust the wiring width of the branch point and the metal wiring at the same time,
The set of synchronized circuits after the adjustment is regarded as one synchronized circuit.
By repeating the adjustment for all synchronous circuits
The positions of the plurality of wiring branch points and the wiring of the metal wiring.
A clock distribution circuit characterized in that the width is determined .