JP2679394B2 - Schottky junction diode and manufacturing method thereof - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a structure of a Schottky junction diode, and in particular, to an electrode portion suitable for connecting the surface electrode and wiring by ultrasonic bonding after formation. It is about structure.

[Conventional technology]

Conventionally, after forming a Schottky junction diode, when the Al wiring is directly connected by ultrasonic bonding to the bonding metal layer forming the Schottky junction on the semiconductor, deterioration of the bonding metal layer due to ultrasonic bonding vibration There is a problem in that the characteristics of the Schottky junction diode deteriorate due to the above.

Therefore, as shown in FIG. 3, there is a case where an Al metal plate 11 is bonded onto the bonding metal layer 3 on the semiconductor substrate 1 with solder 10 and ultrasonic bonding is performed on the metal plate 11. . However, in this method, since it is necessary to solder a small metal plate 11 for each Schottky junction diode before ultrasonic bonding, double labor is required and the manufacturing cost is increased.

The structure proposed to solve the problem of the Schottky junction diode is such that a polycrystalline silicon layer 9 is formed on the junction metal layer 3 on the semiconductor substrate 1 as shown in FIG. The crystalline silicon layer 9 is partially removed to provide the opening 8 and the metal layer 5 is further formed thereon. Here, 2 is an insulating layer, and 6 is a back electrode. According to this structure, the polycrystalline silicon layer 9 serves as a cushioning material against the impact of ultrasonic bonding, so that deterioration of the bonding metal 3 can be prevented.

[Problems to be solved by the invention]

However, the conventional Schottky junction diode described above has the following problems.

That is, in the structure shown in FIG. 4, the opening 8 is provided in the polycrystalline silicon layer 9 in order to maintain good conductive contact between the metal layer 5 and the bonding metal layer 3. If the area is large, the impact of ultrasonic bonding cannot be sufficiently mitigated, while if the opening area is too small, the conductive contact of the opening 8 becomes unstable and the conductivity varies, and the polycrystalline The contribution of the resistance component of the silicon layer increases, and the series resistance of the diode increases as a whole.

Further, in order to produce the structure shown in FIG. 4, it is necessary to remove the surrounding metal layer and the polycrystalline silicon layer by etching after forming the metal layer 5. In this etching,
In particular, there has been a problem that a large side etching occurs in the polycrystalline silicon layer 9 formed as the thickest shock absorbing layer and the cross-sectional shape of the Schottky junction diode is impaired.

Therefore, the present invention is to solve the above problems,
The problem is that while having conductivity in the portion functioning as a buffer layer and having a structure including this buffer layer, while having a shock relaxation structure for ultrasonic bonding,
It is an object of the present invention to provide a Schottky junction diode which can ensure good and stable conductive contact and can be formed without impairing the cross-sectional shape.

[Means for solving the problem]

In order to solve the above-mentioned problems, in a Schottky junction diode provided with a junction metal layer that forms a Schottky junction with the surface of a semiconductor substrate, the means taken by the present invention includes a conductive impurity on the junction metal layer. A silicon layer and a surface metal layer are provided on the silicon layer, the silicon layer is formed so that its outer periphery is located inside the outer periphery of the surface on which the bonding metal layer is formed, and the surface metal layer is formed on the outer periphery of the silicon layer. Is connected to the bonding metal layer and the silicon layer is enclosed by the bonding metal layer and the surface metal layer.

Here, the silicon layer may be formed of polycrystalline silicon, or may be formed of amorphous silicon.

Further, as a manufacturing method, a step of depositing a bonding metal layer on the surface of the semiconductor substrate to form a Schottky junction, and then a silicon layer containing a conductive impurity is selectively formed on the bonding metal layer. A step, and thereafter, a step of forming a surface metal layer on the silicon layer and the bonding metal layer to bring the silicon layer into an inclusion state, and thereafter, a step of removing the surrounding bonding metal layer and the surface metal layer. It is provided.

[Action]

According to such means, the silicon layer containing the conductive impurities has the function as the buffer layer as in the conventional case, and further has the conductivity. Therefore, since it is not necessary to provide an opening in the silicon layer, problems such as a decrease in the buffer function or instability or increase in series resistance caused by the size of the opening do not occur.

Further, since it is not necessary to provide an opening in the silicon layer, the etching time for forming the opening becomes unnecessary,
The manufacturing process can be shortened. This effect becomes particularly remarkable when the silicon layer is formed thick in order to obtain a sufficient buffering effect.

Furthermore, since the silicon layer is included in the bonding metal layer and the surface metal layer, side etching of the silicon layer does not occur in the etching process. In addition, since only the joining metal layer and the surface metal layer are finally removed by etching, the etching process can be completed in a short time regardless of the thickness of the silicon layer.

Here, as the silicon layer, not only single crystal silicon but also a polycrystalline silicon layer or an amorphous silicon layer can be used. When the amorphous silicon layer is formed, the layer can be formed at a low temperature. Therefore, it is possible to prevent thermal deterioration of the Schottky junction without giving thermal stress to the joining metal layer or the like.

[Embodiment] Next, an embodiment of the present invention will be described with reference to the accompanying drawings.

<First Embodiment> FIGS. 1A to 1G show a manufacturing process and a structure of a Schottky junction diode as a first embodiment.

As a method of manufacturing a Schottky junction diode according to the present invention, first, an oxide film 12 is selectively formed on the front surface of an n-type silicon substrate 11 having an electrode 16 on the back surface (first
(A)), and a bonding metal layer 13 is deposited on the entire surface by sputtering or the like (FIG. 1 (b)). next,
A polycrystalline silicon layer 14 is deposited on the entire surface of the bonding metal layer 13 at a temperature of about 600 ° C. by a CVD method using SiH ₄ gas mixed with B ₂ H ₆ gas (see FIG. )). This B ₂ H ₆
By mixing the gas, the resistivity of the polycrystalline silicon layer 14 is reduced to 10
It can be lowered to about ^-3 Ω · cm. Then, the polycrystalline silicon layer 14 above the Schottky junction surface surrounded by the oxide film 12 is left, and the polycrystalline silicon in other regions is selectively etched and removed (FIG. 1 (d)). In this state, the surface metal layer 15 is formed on the entire exposed surfaces of the polycrystalline silicon layer 14 and the bonding metal layer 13 by the sputtering method (FIG. 1 (e)). After that, the joining metal layer 13 and the surface metal layer 15 formed on the oxide film 12 are removed by etching (FIG. 1 (f)), and as shown in FIG. 1 (g), a polycrystalline silicon layer is formed. 14 is a bonding metal layer 13 and a surface metal layer 15
The Schottky junction diode included in is completed.

According to this example, since the polycrystalline silicon layer was made conductive by containing conductive impurities, the opening for ensuring the conductive contact between the bonding metal layer and the surface metal layer was formed as in the conventional case. Since it is not necessary to provide the diode, the series resistance of the diode can be reduced by only the contact portion between the junction metal layer 13 and the surface metal layer 15 around the polycrystalline silicon layer. Can be reduced.

Further, conventionally, the trade-off that has existed between the instability of conductive contact and the increase in series resistance and the decrease in shock absorption of ultrasonic bonding due to the extent of the opening area of the polycrystalline silicon layer is also eliminated. A low series resistance value can be set with good reproducibility while maintaining shock absorption.

Furthermore, since the final etching step (step shown in FIG. 1 (f)) is performed while the polycrystalline silicon layer 14 is included in the surface metal layer 15 and the bonding metal layer 13, the impact on ultrasonic bonding is increased. No matter how thick the polycrystalline silicon layer 14 is formed for the purpose of improving the absorptivity, since the objects to be etched are only the surface metal layer 15 and the bonding metal layer 13, it is possible to significantly reduce the etching time. In addition, there is no room for the conventional problem that side etching occurs in the polycrystalline silicon layer 14 and the cross-sectional shape is impaired.

The bonding metal layer 13 and the surface metal layer 15 can use Al or another metal, and various elements serving as donors or acceptors can be used as the conductive impurities introduced into the polycrystalline silicon layer.

<Second Embodiment> Next, a second embodiment of the present invention will be described with reference to FIG.

Also in this embodiment, the oxide film 22 is formed on the surface of the silicon substrate 21 (FIG. 2 (a)), and the bonding metal layer 23 is further formed thereon (FIG. 2), similarly to the first embodiment. (B))
However, an amorphous silicon layer 27 is formed on the bonding metal layer 23 by a glow discharge method using SiH ₄ gas. Since this amorphous silicon layer 27 can be formed at a low temperature of about 300 ° C., there is no risk of applying thermal stress to the junction surface or the like during layer formation, and the deterioration of the characteristics of the diode can be suppressed. The amorphous silicon layer 27 is doped with a conductive type impurity like the polycrystalline silicon layer 14 formed in the first embodiment.
The specific resistance is 10 ³ Ω · cm, which is relatively large, so Fig. 2 (e)
In order to lower the resistance value between the surface metal layer 25 and the bonding metal layer 23 formed in the step shown in FIG. 2, if the portion formed above the oxide film is removed by etching as shown in FIG. 2 (d). At the same time, the opening 28 is formed.

The subsequent steps are the same as in the first embodiment, except that the surface metal layer 25
(FIG. 2 (e)) and an etching process (FIG. 2 (f)), the Schottky junction diode is completed (FIG. 2 (g)).

Also in this embodiment, it is needless to say that if the amorphous silicon layer has a sufficiently low resistivity, it is not necessary to form the opening 28.

〔The invention's effect〕

As described above, the present invention has a structure in which conductive impurities are introduced into a silicon layer for shock absorption to form a conductive layer, and the silicon layer is enclosed by a bonding metal layer and a surface metal layer. Since it has the characteristics, it has the following effects.

Since it is not necessary to form an opening in the silicon layer for achieving low series resistance, it is possible to reduce the number of steps, and it is possible to achieve both stability of resistance value, low resistance, and shock absorption. Become.

Since the silicon layer is included in the bonding metal layer and the surface metal layer, the final etching step can be shortened and the silicon layer can be shortened regardless of how thick the silicon layer is formed. There is no possibility that side etching will damage the cross-sectional shape.

When the silicon layer is made of amorphous silicon, it can be formed at a relatively low temperature, so that thermal stress can be reduced and deterioration of diode characteristics can be prevented.

[Brief description of the drawings]

FIGS. 1A to 1G are process cross-sectional views showing a manufacturing method and a final structure of a first embodiment of a Schottky junction diode according to the present invention. FIGS. 2A to 2G are process cross-sectional views showing a manufacturing method and a final structure of a second embodiment of the Schottky junction diode according to the present invention. FIG. 3 is a sectional view showing an example of a conventional Schottky junction diode. FIG. 4 is a sectional view showing another example of a conventional Schottky junction diode. [Explanation of symbols] 11,21 …… Silicon substrate 13,23 …… Joining metal layer 14 …… Polycrystalline silicon layer 15,25 …… Surface metal layer 27 …… Amorphous silicon layer.

Claims (4)

(57) [Claims] 1. A Schottky junction diode having a junction metal layer forming a Schottky junction with a surface of a semiconductor substrate, wherein a silicon layer containing a conductive impurity formed on the junction metal layer and the silicon layer. And a surface metal layer formed above, the outer periphery of the silicon layer is located inside the outer periphery of the formation surface of the bonding metal layer, the surface metal layer is outside the outer periphery of the silicon layer A Schottky junction diode connected to a junction metal layer, wherein the silicon layer is included in the junction metal layer and the surface metal layer. 2. The Schottky junction diode according to claim 1, wherein the silicon layer is made of polycrystalline silicon. 3. The Schottky junction diode according to claim 1, wherein the silicon layer is made of amorphous silicon. 4. A step of depositing a bonding metal layer on the surface of a semiconductor substrate to form a Schottky junction, and then, selectively forming a silicon layer containing a conductivity type impurity on the bonding metal layer. And a step of forming a surface metal layer on the silicon layer and the bonding metal layer to bring the silicon layer into an encapsulated state, and thereafter, the bonding metal layer and the surface metal formed on the periphery. A method of manufacturing a Schottky junction diode, comprising: a step of removing a layer.