JP2676826B2 - Clock distribution circuit - Google Patents

Description

The present invention relates to a clock distribution circuit in a large scale integrated circuit.

(Prior Art) A conventional clock distribution circuit in an integrated circuit uses a normal gate array cell and is realized by automatic placement / wiring or forced placement / wiring.

(Problems to be Solved by the Invention) In the conventional method for realizing a clock distribution circuit, since a normal gate such as a gate array is used in this way, a clock distribution gate having an arbitrary driving capability cannot be made. However, there is a drawback that the delay time of the clock and the variation of the delay time are large.

Further, when the clocks are distributed, the clock drivers are arranged in a distributed manner, and the clock wiring is bypassed and connected to the clock driver, so that a distributed constant system circuit is formed and the clock between the gate arrays is formed. However, there is a drawback in that there is a difference in the delay time.

Further, since the equal length clock wiring has to be performed based on the position of the clock distribution gate, it is necessary to make the detour clock wiring, and it is difficult to make the equal length clock wiring.

An object of the present invention is to solve the above-mentioned drawbacks by providing a clock distribution circuit having an arbitrary driving capability capable of reducing the delay time and variations in the clocks supplied to each gate array and easily forming the clock wiring. To provide.

(Means for Solving the Problems) In order to achieve the above object, a clock distribution circuit according to the present invention is an integrated circuit composed of a plurality of gate arrays partitioned by a plurality of buses in the X and Y directions. A first clock distribution gate group for distributing clocks to the flip flops in each gate array is provided in the gate array, and at the intersection of the X-direction and Y-direction buses, a first clock distribution gate group of four adjacent gate arrays is provided. A second clock distribution gate group for allocating the clock is provided to each of the first clock distribution gate groups, the second clock distribution gate groups being arranged at the same distance to the clock distribution gate group.

Hereinafter, the present invention will be described in more detail with reference to the drawings.

FIG. 1 is an external view showing an embodiment of a clock distribution circuit according to the present invention. FIG. 2 is a circuit diagram of the clock distribution circuit having the configuration of FIG. Regarding the symbols used in FIGS. 1 and 2, the same components are denoted by the same symbols.

The integrated circuit 1 is composed of gate arrays 2-1 to 2-16 separated by a bus 6 composed of a plurality of power supply wirings.

Flip flops 21-11, 21 in the gate array 2-1
-12 is distributed from the first clock distribution gate group 21 provided in the gate array 2-1 by the clock wiring 21-1. Similarly, the first clock distribution gate groups 22 to 24 are provided in the other gate arrays 2 to 2 to 4 and the clocks are distributed to the flip flops in the respective gate arrays 2-1 to 2-4. To be done.

A second clock distribution gate group 31 is arranged at the intersections of the buses 6 that partition the four gate arrays 2-1 to 2-4, and each first clock distribution gate group 21 to 24 has an equal-length clock wiring 31-. Distribute the clock by 1-31-4. Second clock distribution gate groups 32 to 34 are similarly provided for the other sets of four adjacent gate arrays.

Then, a third clock distribution gate group 41 is arranged under the bus 6 in the center of the second clock distribution gate groups 31 to 34, and clock wirings of the same length up to the second clock distribution gate groups 31 to 34, respectively. Distribute the clock by 41-1 to 41-4.

The clock is supplied to the third clock distribution gate group 41 by the clock wiring 51-1 connected to the clock input terminal 51 of the integrated circuit 1.

By adopting such a configuration, each gate array 2
Since the clocks are distributed by the first clock distribution gates 21 to 24 to the flip flops in -1 to 2-4 through the clock wiring having a short line length, the delay time of the clock can be shortened and the clock delay between the gate arrays can be reduced. The difference in the delay time can be reduced.

Since the distances from the second group of clock distribution gates 31 to 34 to the respective first clock distribution gates 21 to 24 are equal, the equal-length clock wirings 31-1 to 31-4 can be easily formed and serve as load gates. Since the first clock distribution gate groups 21 to 24 are arranged in a concentrated manner, the distance between the load gates of each group becomes short and the difference in delay time does not occur.

Similarly, since the distances from the third clock distribution gate group 41 to the respective second clock distribution gates 31 to 34 are equal, the clock wirings 41-1 to 41 to 4 of equal length can be easily formed and serve as load gates. Since the two clock distribution gates 31 to 34 are centrally arranged, the distance between the load gates of each group is short and the difference in delay time does not occur.

Furthermore, since the third clock distribution gate group 41 is also composed of concentrated load gates, the distance between the loads is short and there is no difference in delay time.

In this embodiment, the arrangement of the first to third clock distribution gate groups is under the bus, but it may be a part of the closest gate array.

Since the positions of the first to third clock distribution gate groups are fixed, a gate having a large driving ability can be incorporated in the integrated circuit.

(Effects of the Invention) As described above, according to the present invention, clock wiring of equal length can be realized for each gate array, and load gates are centralized. The effect is that there is no difference in delay time between clocks.

Further, since a gate having a high driving capability can be used, there is an effect that a delay time for clock distribution and variation can be reduced.

[Brief description of the drawings]

FIG. 1 is an external view showing an embodiment of the clock distribution circuit according to the present invention, and FIG. 2 is a circuit diagram showing an embodiment of the circuit of FIG. 1 ... Integrated circuit 2-1 to 2-4 ... Gate array 6 ... Bus 21-11 to 21-12 ... Flip flop 21-1, 31-1 to 31-4, 41-1 to 41-4, 51-1 ...... Clock wiring 21 to 24 ...... First clock distribution gate group 31 to 34 ...... Second clock distribution gate group 41 ...... Third clock distribution gate 51 ...... Clock input terminal

Claims (2)

(57) [Claims] 1. An integrated circuit composed of a plurality of gate arrays partitioned by a plurality of X-direction and Y-direction buses, wherein a clock is distributed to each gate array flip-flop in each gate array. A clock distribution gate group is provided and arranged at the intersections of the X-direction and Y-direction buses at the same distance to the first clock distribution gate groups of each of the four adjacent gate arrays. A clock distribution circuit characterized in that a second clock distribution gate group for distributing clocks is provided to one clock distribution gate group. 2. The clock according to claim 1, which is arranged under a bus located at the center of the plurality of second clock distribution gate groups and distributes the clock to each of the second clock distribution gate groups. A clock distribution circuit comprising a third clock distribution gate group.