JP2674516B2 - Active matrix substrate and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix substrate having a channel protection type thin film transistor used in a liquid crystal display device and the like, and a method of manufacturing the same, and more particularly to a structure of a thin film transistor and a method of manufacturing the thin film transistor. Is.

[0002]

2. Description of the Related Art A thin film transistor used in an active matrix type liquid crystal display device is classified into a channel protection type and a channel etching type. In the conventional method of manufacturing a channel protection transistor, as shown in FIG. 5, first, a first metal film 3 made of Cr, Mo, W or the like is first formed on a transparent glass substrate 1.
And is patterned to form the gate electrode 4 [FIG. 5 (a)]. Next, the gate insulating film 6 made of SiN _x , the non-doped a-Si (amorphous silicon) film 7, and the channel protective film 8 made of SiN _x are continuously grown by the plasma CVD method to form the channel protective film 8. Pattern into a predetermined shape [Fig. 5
(B)].

Next, after the n ⁺ -type a-Si film 10 heavily doped with phosphorus is formed, the non-doped a-Si film 7 is formed.
Is patterned into an island shape [FIG. 5 (c)]. Next, the gate insulating film 6 is patterned to selectively remove only the gate insulating film 6 on the peripheral contact portion 9 made of the first metal film 3 [FIG. 5 (d)]. Next, Cr, Mo, W
A second metal film 11 made of, for example, is deposited and patterned to form a drain electrode 12 and a source electrode 13,
After that, the n ⁺ type a-Si film 10 on the channel portion is removed by etching using the drain electrode and the source electrode as a mask [FIG. 5 (e)].

Further, a transparent conductive film 2 such as indium tin oxide (ITO) is deposited and patterned to form a pixel electrode 5 [FIG. 5 (f)]. Finally, an insulating film such as SiN _x is grown, and patterning is performed to remove portions on the pixel electrodes and the like to form the passivation film 15 [FIG. 5 (g)], and the fabrication of the channel protection type thin film transistor is completed.

As described above, in the conventional method of manufacturing a channel protection type thin film transistor, the patterning process is performed as shown in FIG.
From (a) to FIG. Photoresist process for forming gate electrode (hereinafter referred to as PR) ,. PR for channel protective film ,. PR for island formation ,.
PR for forming contact holes ,. Drain electrode forming PR ,. PR for forming pixel electrodes ,. It is 7 times of PR for the passivation film.

On the other hand, in the method of manufacturing the channel-etch type thin film transistor, as shown in FIG. 6, the gate electrode 4 made of the first metal film 3 is formed on the transparent glass substrate 1 [FIG.
(A)] After that, the gate insulating film 6, the non-doped a-Si film 7, and the n ⁺ -type a-Si film 10 are continuously formed by the CVD method to form the non-doped a-Si film 7 and the n ⁺ -type a-Si. The film 10 is patterned into an island shape [FIG.
(B)].

Next, the portion where the gate electrode potential is obtained, that is, the gate insulating film on the peripheral contact portion 9 of the first metal film 3 is removed [FIG. 6 (c)], and then the second metal film 11 is deposited. This is patterned to form the drain electrode 12 and the source electrode 13, and then the n ⁺ -type a-Si film 10 in the channel portion is etched using the drain electrode 12 and the source electrode 13 as a mask [FIG.
(D)]. Further, the transparent conductive film 2 is patterned to form the pixel electrode 5 [FIG. 6 (e)], and finally the passivation film 15 is formed to complete the fabrication of the channel-etch type thin film transistor [FIG. 6 (f)]. )].

Therefore, in the channel-etch type thin film transistor, the patterning process is shortened to 6 times because there is no PR process for the channel protective film. However, in this type of transistor, the n ⁺ -type a-Si film 10 in the channel portion is used.
When etching is performed, since there is no channel protection film (8 in FIG. 5) as in the case of the channel protection type thin film transistor, the surface (back interface) 18 of the non-doped a-Si film 7 is removed.
Are engraved, and therefore it is necessary to form the non-doped semiconductor layer thick. As a result, the leak current increases, the on / off current ratio decreases, and the photo-induced current increases, resulting in inferior characteristics to the channel protection transistor.

That is, the channel protection type transistor is easier to control in the etching process of the n ⁺ type a-Si film and superior in characteristics than the channel etching type thin film transistor, but on the other hand, as described above, the patterning process is performed. However, there is a problem that the yield decreases and the manufacturing cost increases.

In order to solve these problems in the channel protection type thin film transistor, JP-A-4-269837 discloses a first prior art as shown in FIG. In this prior art, the patterning of the channel protective film 8 is performed by using the back surface exposure using the gate electrode 4 as a mask, thereby reducing the mask for patterning the channel protective film 8. Below, JP-A-4-2698
The method disclosed in Japanese Patent No. 37 will be described.

First, a metal film is deposited on the transparent glass substrate 1 and patterned to form a gate electrode 4.
After that, a gate insulating film 6, a non-doped a-Si film 7, and a channel protective film 8 are continuously formed by a plasma CVD method or the like, and then a positive type photoresist film 16b is applied on the channel protective film 8 to form a gate. Back surface exposure is performed from the back surface of the glass substrate 1 as shown by an arrow using the electrode 4 as a mask [FIG. 7 (a)]. After the exposed portion of the photoresist film 16b is removed by dissolution [FIG. 7 (b)], the channel protective film 8 is etched using the insoluble portion as a mask,
The patterned channel protective film 8 is obtained as shown in FIG.

Next, as shown in FIG. 7D, P ⁺ (phosphorus ion) is implanted from above the channel protective film 8 to lower the resistance of a part of the non-doped a-Si film 7 to form the contact layer 7a. Form. After that, like the conventional method,
PR for island formation, PR for contact hole formation,
A channel protection type thin film transistor is formed through the steps of PR for forming a drain electrode, PR for forming a pixel electrode, and PR for a passivation film.

Further, in Japanese Patent Laid-Open No. 4-75350,
A second prior art relating to channel protected transistors is disclosed. In this prior art, the patterning of the channel protection film is performed by backside exposure using the gate electrode as a mask, and the patterning of the drain and source electrodes made of a transparent conductive film is performed on the backside of the image reversal photoresist using the gate electrode as a mask. This is performed by using exposure, which reduces the number of masks. The method disclosed in JP-A-4-75350 will be described below with reference to FIG.

First, a metal film is deposited on the transparent glass substrate 1 and patterned to form a gate electrode 4 [FIG. 8 (a)]. Next, a gate insulating film 6 made of SiN _x or the like, a non-doped a-Si film 7, and a channel protective film 8 made of SiN _x are continuously grown by a plasma CVD method, and a back surface exposure using the gate electrode 4 is performed. Patterning of the channel protective film 8 is performed [FIG. 8 (b)].

Next, an n ⁺ type a-Si film 10 is deposited, and a transparent conductive film 2 such as ITO is further deposited. Subsequently, an image reversal photoresist 19 is applied to define the outer shapes of the source electrode 13 and the drain electrode 12,
Perform normal exposure and development using a photomask. next,
The back surface is exposed using the gate electrode 4 as a mask, and the photoresist pattern shown in FIG. 8C is obtained by the reversal bake development of the image reversal photoresist 19. Using it as a mask, the transparent conductive film 2 and the n ⁺ type a-Si film 1
0 and the non-doped a-Si film 7 are patterned to form the drain electrode 12 and the source electrode 13, and the a-Si film 7 is formed into an island.

In this method, the apparent number of steps required is
. PR for gate electrode formation ,. P for channel protection film
R ,. Drain electrode forming PR ,. Although there are four steps of PR for forming the pixel electrode, in reality, the contact hole forming PR for removing the gate insulating film for extracting the gate electrode potential and forming the data line only with the ITO layer have a high resistance. PR for data line formation because it becomes too much
Therefore, 6 steps are required in practice, and 7 steps are required if a passivation step is further performed.

[0017]

The method of manufacturing the conventional channel protection type thin film transistor shown in FIG. 5 requires 7PR steps as described above, and the steps are complicated and the number of steps is greater than that of the channel etching type thin film transistor. As a result, the yield is decreased and the manufacturing cost is increased.

Further, in the method of the first prior art (JP-A-4-269837) shown in FIG. 7, the back surface exposure using the gate electrode 4 as a mask is used to form the channel protective film 8. Although the number of patterning masks is 6, the number of patterning steps itself is not reduced to 7 steps, and the number of ion implantation steps is increased. Therefore, the yield is decreased due to the large number of patterning steps. The problem of has not been solved.

This situation is the same in the method of the second prior art (Japanese Unexamined Patent Publication No. 4-75350) shown in FIG. 8 as well as the exposure using a normal photomask using an image reversal photoresist. Since the process complexity of using the backside exposure together is added, manufacturing with high yield becomes difficult. The present invention has been made in view of this point, and an object thereof is to solve the above-described problems of the conventional technology, to truly reduce the number of exposure steps, and to reduce the manufacturing cost and the high yield. It is an object of the present invention to provide an active matrix substrate that can be manufactured in and a manufacturing method thereof.

[0020]

In order to achieve the above object, according to the present invention, a gate electrode and a pixel electrode are formed on a transparent substrate, and an island shape is formed on the gate electrode via a gate insulating film. A high resistance semiconductor layer is formed, a channel protection film having openings on the drain extraction region and the source extraction region on the high resistance semiconductor layer is formed on the high resistance semiconductor layer and the gate insulating film, and the high resistance semiconductor layer is formed. A drain electrode and a source electrode made of a composite film of a low resistance semiconductor layer and a metal film are drawn out from above the resistive semiconductor layer through the opening, and the source electrode is the composite electrode.
A film connected to the pixel electrode ,
The gate insulating film is a region where the high resistance semiconductor layer is formed.
The pattern of the channel protective film is the same as that of the channel protective film except the region.
An active matrix substrate is provided which is characterized in that it is patterned .

Further, according to the present invention, (1) a step of forming a gate electrode on a transparent substrate, (2) a step of continuously growing a gate insulating film and a high resistance semiconductor layer on the entire surface, (3) ) Patterning the high resistance semiconductor layer; (4) Forming a channel protective film on the entire surface; (5) Forming the channel protective film and the gate insulating film in the same manner.
At times, patterning is performed to expose the drain extraction region and the source extraction region of the high resistance semiconductor layer.
Both the step of exposing the electrode lead-out portion on the transparent substrate , (6) the step of depositing a composite film comprising a low resistance semiconductor layer and a metal film on the entire surface, (7) the step of patterning the composite film And a step of forming a drain electrode drawn from the drain extraction region and a source electrode drawn from the source extraction region and connected to the pixel electrode. .

[0022]

Since the active matrix substrate according to the present invention is constructed as described above ,. Gate electrode forming P
R ,. PR for island formation ,. PR for channel protective film ,. Drain electrode forming PR ,. In the five PR steps of PR for passivation film, or. PR for gate electrode formation ,. PR for forming pixel electrodes ,.
Exposure process for island formation ,. P for channel protection film
R ,. Drain electrode forming PR ,. Since the channel protection type thin film transistor can be formed by the six PR steps of the passivation film PR, it is possible to provide a simplified manufacturing method as compared with the conventional manufacturing method.

[0023]

Next, embodiments of the present invention will be described with reference to the drawings. [First Embodiment] A manufacturing method of a first embodiment of the present invention will be described with reference to FIGS. First, on the transparent glass substrate 1, indium tin oxide (I
The transparent conductive film 2 such as TO) is continuously deposited to a thickness of 100 to 500Å, and the first metal film 3 made of Cr, Mo, W, Ta or the like is continuously deposited to a thickness of 1000 to 3000Å, and the photolithography method is used. Patterning is performed to form the gate electrode 4 and the pixel electrode 5 in the pixel region and the peripheral contact portion 9 [see FIG. 1 (c)] in the peripheral portion of the substrate [FIG. 1 (a)].

Next, SiN is formed by a plasma CVD method or the like.
_The gate insulating film 6 made of _x or the like is 2000 to 4000 Å
Of the non-doped a-Si film 7 to 100 to 1000
A film having a thickness of Å is continuously formed, and the non-doped a-Si film 7 is patterned into an island shape by a photolithography method [FIG. 1 (b)]. Next, a channel protective film 8 made of SiN _x , SiO _x, etc. is deposited by plasma CVD to a film thickness of 1000 to 3000 Å, and is formed on the drain extraction region and the source extraction region of the non-doped a-Si film 7 by photolithography. The channel protection film 8 is selectively removed. In this step, the gate insulating film 6 on the pixel electrode 5 and the peripheral contact portion 9 is simultaneously removed [FIG. 1 (c)].

Next, the n ⁺ type a-Si film 10 is formed by plasma CVD or the like, and then Cr, by sputtering or the like.
The second metal film 11 made of Mo, W, Ta, etc.
A film having a thickness of up to 3000 Å, and patterning this two-layer film by photolithography to form the drain electrode 12,
Upper wiring 14 connected to source electrode 13 and peripheral contact portion 9 is formed. Since the first metal film 3 on the pixel electrode 5 is removed in this step, the pixel electrode 5 is formed only by the transparent conductive film 2 [FIG.
(A)]. Next, by plasma CVD method, SiN _x , S
forming a passivation film 15 made of iO _x ,
Patterning is performed by a photolithography method or the like [FIG. 2 (b)].

The number of masks required in this first embodiment is as follows according to FIGS. 1 (a) and 2 (b). PR for gate electrode formation ,. PR for island formation ,. PR for channel protective film ,. Drain electrode forming PR ,. There will be 5 sheets of PR for the passivation film, and the required PR will also be 5 steps.

[Second Embodiment] Next, a manufacturing method according to a second embodiment of the present invention will be described with reference to FIGS. First, on the transparent glass substrate 1, Cr, Mo, W, Ta
To form the first metal film 3 by sputtering a metal material such as
This is patterned by the photolithography method to form the gate electrode 4 and the peripheral contact portion 9 [see FIG. 4 (a)] in the peripheral portion of the substrate [FIG.
(A)].

Next, a transparent conductive material such as ITO is sputtered to form the transparent conductive film 2, and the transparent conductive film 2 is similarly patterned to form the pixel electrode 5 [FIG. 3 (b)]. Next, the gate insulating film 6 made of SiN _x , SiO _x, etc.
Then, the non-doped a-Si film 7 is continuously formed. Then, a photoresist film 16a is formed on the non-doped a-Si film 7.
Is applied to expose the back surface of the transparent glass substrate 1 from the back surface using the gate electrode 4 as a mask. The exposure is performed by the transparent glass substrate 1, the pixel electrode 5, the gate insulating film 6, and the non-doped a-
It is necessary to increase the amount of light so as to pass through the Si film 7 [FIG. 3 (c)].

After patterning the photoresist film 16a in the shape of the gate electrode 4 as described above, the non-doped a-S is subsequently formed by, for example, a dry etching method.
The i film 7 is patterned [FIG. 3 (d)]. Next, the first
The channel protective film 8 is formed in the same manner as in the embodiment of
The channel protection film 8 is patterned by using a photolithography method or the like, and at the same time, the gate insulating film 6 on the pixel electrode 5 and the peripheral contact portion 9 is removed [FIG.
(A)].

Next, the n ⁺ type a-Si film 10 and Cr,
A second metal film 11 made of W, Mo or the like is formed and patterned to form a drain electrode 12 and a source electrode 13, and an upper layer wiring 14 connected to the peripheral contact portion 9 [FIG. b)]. At this time, the unnecessary non-doped a-Si film 7 left on the gate wiring due to the back surface exposure used in the island PR process has the channel protection film 8 above the channel protection film PR [FIG.
It can be removed at the same time by removing in (a)].

Next, SiN is formed by a plasma CVD method or the like.
_A light-shielding film 1 including a passivation film 15 made of _{X 2} , SiO _X or the like, and a resin layer on which a metal material such as Cr or carbon or an organic pigment is dispersed.
7 is deposited, and then patterned by photolithography or the like [FIG. 4 (c)].

As described above, the PR required in the second embodiment
The process is. PR for gate electrode formation ,. PR for island formation ,. PR for forming pixel electrodes ,. PR for channel protective film ,. Drain electrode forming PR ,. There are 6 steps of the passivation film PR, and the required mask is 5 because the back surface exposure using the gate electrode is performed in the island PR. In this embodiment, the pixel electrode 5 is formed in the step immediately after the gate electrode 4 is formed, but of course, the pixel electrode forming PR may be performed in another step such as before and after the drain electrode forming PR.

[0033]

As described above, in the active matrix substrate according to the present invention, the high resistance semiconductor layer is formed on the gate electrode via the gate insulating film, and the channel covering the semiconductor layer from the high resistance semiconductor layer is formed. According to the present invention, a thin film transistor having a drain electrode and a source electrode formed of a composite film of a low resistance semiconductor layer and a metal film is drawn out through an opening formed in the protective film. It becomes possible to form an active matrix substrate having a channel protection type thin film transistor with a small number of masks and a small number of photoresist steps, and as a result, it is possible to manufacture a product with excellent characteristics at a high yield and at a low manufacturing cost. Is possible.

[Brief description of the drawings]

FIG. 1 is a part of a process order sectional view for explaining a manufacturing method according to a first embodiment of the present invention.

FIG. 2 is a part of a process order sectional view for explaining the manufacturing method of the first embodiment of the present invention, following the process of FIG. 1;

FIG. 3 is a part of a process cross-sectional view for explaining a manufacturing method according to a second embodiment of the present invention.

FIG. 4 is a part of a sectional view in order of the processes, for explaining the manufacturing method of the second embodiment of the present invention, which follows the process of FIG.

5A to 5C are cross-sectional views in order of the processes, for illustrating a conventional method for manufacturing an active matrix substrate having a channel protection type thin film transistor.

6A to 6C are cross-sectional views in order of the processes, for illustrating a conventional method for manufacturing an active matrix substrate having a channel-etch type thin film transistor.

7A to 7C are cross-sectional views in order of the processes, for illustrating a manufacturing method of an active matrix substrate having a channel protection type thin film transistor according to a first prior art.

8A to 8C are cross-sectional views in order of the processes, for explaining a manufacturing method of an active matrix substrate having a channel protection type thin film transistor according to a second prior art.

[Description of Reference Signs] 1 transparent glass substrate 2 transparent conductive film 3 first metal film 4 gate electrode 5 pixel electrode 6 gate insulating film 7 non-doped a-Si film 7a contact layer 8 channel protective film 9 peripheral contact portion 10 n ⁺ type a -Si film 11 Second metal film 12 Drain electrode 13 Source electrode 14 Upper layer wiring 15 Passivation film 16a, 16b Photoresist film 17 Light-shielding film 18 Back interface 19 Image reversal photoresist

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-3-96021 (JP, A) JP-A-6-118445 (JP, A) JP-A-5-323378 (JP, A) JP-A-6- 82830 (JP, A) JP 4-97136 (JP, A) JP 2-196222 (JP, A)

Claims (6)

(57) [Claims] 1. A gate electrode and a pixel electrode are formed on a transparent substrate, and a high resistance semiconductor layer is formed in an island shape on the gate electrode via a gate insulating film, and the high resistance semiconductor layer and the gate are formed. A channel protection film having openings on the drain extraction region and the source extraction region on the high resistance semiconductor layer is formed on the insulating film, and the low resistance semiconductor layer and the metal are formed on the high resistance semiconductor layer through the opening. A drain electrode and a source electrode made of a composite film of films are drawn out, and the source electrode is made by the composite film.
The be one that is connected to the pixel electrode Ri, the gate
The gate insulating film excludes the region where the high resistance semiconductor layer is formed.
And an active matrix substrate characterized by being patterned in the same shape as the channel protective film . 2. The active matrix substrate according to claim 1, wherein the gate electrode is composed of a composite film of a transparent conductive film and a metal film. 3. The active matrix substrate according to claim 1, wherein a passivation film or a passivation film having an opening on the pixel electrode and a light shielding film are formed on the drain electrode and the source electrode. 4. A step of (1) forming a gate electrode on a transparent substrate, (2) a step of continuously growing a gate insulating film and a high resistance semiconductor layer on the entire surface, (3) the high resistance semiconductor layer And (4) forming a channel protective film on the entire surface, and (5) forming the channel protective film and the gate insulating film in the same manner.
At times, patterning is performed to expose the drain extraction region and the source extraction region of the high resistance semiconductor layer.
Both the step of exposing the electrode lead-out portion on the transparent substrate , (6) the step of depositing a composite film comprising a low resistance semiconductor layer and a metal film on the entire surface, (7) the step of patterning the composite film A method of manufacturing an active matrix substrate, comprising: forming a drain electrode drawn from a drain extraction region and a source electrode drawn from the source extraction region and connected to a pixel electrode. 5. A step of (1) forming a transparent conductive film and a first metal film on a transparent glass substrate, and (2) patterning the first metal film and the transparent conductive film to form a gate electrode and a pixel electrode. And (3) a step of continuously growing a gate insulating film and a high resistance semiconductor layer on the entire surface, and (4) patterning the high resistance semiconductor layer to form an island shape on the gate electrode. A step of forming a high resistance semiconductor layer; (5) a step of forming a channel protective film on the entire surface; and (6) selectively forming the channel protective film on the drain extraction region and the source extraction region of the high resistance semiconductor layer. Etching away and selectively removing the channel protection film and the gate insulating film on the pixel electrode by etching (7) low resistance semiconductor layer and second metal over the entire surface Depositing a composite film including a film, and (8) patterning the composite film to form a drain electrode extracted from the drain extraction region and a source electrode extracted from the source extraction region and connected to the pixel electrode. And a step of etching and removing the first metal film on the pixel electrode, the method of manufacturing an active matrix substrate. 6. (1) A step of forming a gate electrode made of a first metal film on a transparent substrate, (2) A step of continuously growing a gate insulating film and a high resistance semiconductor layer on the entire surface, (3) ) Patterning the high resistance semiconductor layer by a photolithography method using exposure from the back surface of the substrate, (4) forming a channel protective film on the entire surface, (5) the channel protective film and the gate insulating film The same
Sometimes it is patterned prior to expose the surface of the surface and unnecessary portions of the high resistance semiconductor layer drain lead region and source extension region of the high resistance semiconductor layer
The step of exposing the electrode lead-out portion on the transparent substrate , and (5) selectively etching the channel protective film to form the surface of the drain lead-out region and the source lead-out region of the high-resistance semiconductor layer and the high-resistance semiconductor layer. Exposing a surface of an unnecessary portion; (6) depositing a composite film composed of a low resistance semiconductor layer and a second metal film on the entire surface; (7) patterning the composite film to extract the drain Forming a drain electrode drawn from the region and a source electrode drawn from the source drawing region and connected to the pixel electrode, and etching away the unnecessary portion of the high resistance semiconductor layer. And a method for manufacturing an active matrix substrate.