JP2674218B2 - Semiconductor storage device - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to the upper and lower parts of a MOS field effect transistor,
The present invention relates to a semiconductor memory device in which a columnar or ring-shaped capacitor is provided on both the upper and lower parts, and in particular, has a large storage capacity and high area efficiency.

2. Description of the Related Art Conventionally, in order to obtain a large-capacity semiconductor memory device, a stack type in which plate electrodes and insulating films are alternately stacked on top of a semiconductor substrate, or a groove is formed in the semiconductor substrate and plate electrodes are provided through the insulating film A trench type semiconductor memory device in which a buried layer is provided and a diffusion layer is provided on the side surface of the groove to form a capacitor has been researched and developed.

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention In a method of forming a capacitor in which plate electrodes and insulating films are stacked alternately in a plane in a stack type semiconductor memory device, the number of manufacturing steps is large and control is difficult. Further, in the capacitor forming method of digging a groove in a semiconductor substrate in a trench type semiconductor memory device and simply burying a plate, it is necessary to reduce an area occupied by a mask and a groove upper surface in order to obtain a large capacity. It is easily affected by crystal defects. The present invention has been made in view of the above problems, and an object of the present invention is to provide a highly reliable semiconductor memory device which has a small number of manufacturing steps and has a large capacity and high integration.

Means for Solving the Problems In order to achieve the above object, a semiconductor memory device of the present invention has a groove formed in a first conductivity type semiconductor substrate and a fourth groove formed in an inner side wall portion of the groove. A first capacitor having a plate electrode, a fourth plate electrode and a third plate electrode interposed by a first capacitive insulating film, and a first conductivity type epitaxial layer formed on the groove. Forming a MOS transistor, and contacting the second plate electrode and a part of the fourth plate electrode through an insulating film above the gate electrode of the MOS transistor;
The second capacitor is in contact with the diffusion layer of the MOS transistor and has the second capacitor having the second plate electrode and the first plate electrode interposed by the second insulating film.

The present invention has the above-described structure, and by providing the plate electrode and the insulating film in a columnar shape, the electric charges are accumulated on all side surfaces of the plate electrode for accumulating the capacitance, and moreover, a large area is not required, so that a large capacitance and a high capacitance are achieved. A highly reliable semiconductor memory device with high integration can be obtained.

EXAMPLE FIG. 1A shows an n-type diffusion layer 4 formed by ion implantation using a polysilicon gate (word line) 3 provided on a P-type conductivity type semiconductor substrate 1 via a gate oxide film 2 as a mask. After that, a second plate 6 made of a conductor is piled up in a column shape on the polysilicon gate 3 with the capacitive insulating film 10 interposed therebetween, and a first plate made of a conductor is further provided with the second plate 6 and the capacitive insulating film 10 interposed therebetween. A plate 5 is formed so as to contact one of the n-type diffusion layers 4 to form a capacitor, a polysilicon electrode 8 that contacts the other of the n-type diffusion layer 4 is provided, and the plate electrode 5 is contacted with an aluminum electrode (bit line) 9. Aluminum electrode 9
An insulating layer 7 is provided to insulate the first plate 5 and the polysilicon electrode 8 from each other. FIG. 1 (b) shows the first
It is the pattern figure which looked at figure (a) from the upper part. The first plate 5, the second plate 6, and the polysilicon gate 3 have a structure that can be pulled out to any place, and the second plate 6 sandwiches the first plate 5. Also 11a, 11b
Are a first contact between the diffusion layer 4 and the polysilicon electrode, and a second contact between the diffusion layer 4 and the first plate 5, respectively. FIG. 2 (a) shows an ion implantation process using the polysilicon gate (word line) 3a and the polysilicon gate (dummy word line) 3b provided on the P-type conductivity type semiconductor substrate 1 with the gate oxide film 2 interposed therebetween. After the n-type diffusion layer 4 is formed, a plurality of columnar second plates 6 made of a conductor are provided on the polysilicon gates 3a and 3b with an insulating film 10 interposed therebetween, and the second plate 6 and the second plate 6 are capacitively insulated. A first plate 5 made of a conductor is formed in a columnar shape via the film 10 so as to be in contact with one of the n-type diffusion layers 4 to form a capacitor, and a poly-silicon plate contacting the other of the n-type diffusion layers 4 is formed. An insulating layer 7 is provided to provide a silicon electrode 8 and to contact the aluminum electrode (bit line) 9 and to insulate the aluminum electrode 9 from the first plate 5 and the polysilicon electrode 8.
Is provided. 2 (b) corresponds to FIG. 1 (a).
It is a sectional view when it cuts in the horizontal direction along the line a '. In FIG. 3, a groove 16 is dug in a direction perpendicular to the substrate 1 from above the P-type conductivity type semiconductor substrate 1, a fourth plate 13 made of a conductor is provided on an inner side wall portion of the groove 16, and a capacitive insulating film 14 is provided therebetween. The third plate 12 made of a conductor into the groove 16 and further,
After the epitaxial layer 15 of the same conductivity type as the substrate 1 is provided on the substrate, the polysilicon gate (word line) 3 provided on the epitaxial layer 15 via the gate oxide film 2 is used as a mask to perform n-type diffusion by ion implantation. Forming a layer 4a and an n-type second diffusion layer 4b in contact with the fourth plate 13;
A second plate 6 made of a conductor is stacked in a column shape on the upper part of the polysilicon gate 3 with a capacitive insulating film 10 interposed therebetween, and further a first plate 5 made of a conductor is provided with the second plate 6 and the capacitive insulating film 10 interposed therebetween. Capacitors are formed on both the lower and upper portions of the substrate 1 so as to be in contact with the n-type second diffusion layer 4b, a polysilicon electrode 8 is provided which is in contact with the n-type diffusion layer 4a, and an aluminum electrode (bit line) 9 is provided. Aluminum electrode 9
An insulating layer 7 is provided to insulate the first plate 5 and the polysilicon electrode 8 from each other. FIG. 4 shows that a groove 16 is dug in a direction perpendicular to the substrate 1 from above the P-type conductivity type semiconductor substrate 1, and a plurality of columnar fourth plate electrodes 13 are formed from the central portion of the groove 16, Of the third plate electrode 12 via the capacitive insulating film 14 so as to surround the plate electrode 13 of
And an epitaxial layer 15 of the same conductivity type as the substrate 1.
Of polysilicon gate (word line) provided on the epitaxial layer 15 through the gate oxide film 2 after the formation of
3a and polysilicon gate (dummy word line) 3b
The n-type diffusion layer 4a and the fourth
The n-type second diffusion layer 4b is formed so as to contact the plate 13 and the aluminum electrode (bit line) 9 is formed so as to contact the n-type diffusion layer 4a. The aluminum electrode 9 and the polysilicon gates 3a, 3
An insulating layer 7 is provided for insulation from b. or,
A view obtained by cutting FIG. 4 in the horizontal direction along the line bb 'is as shown in FIG. 2 (b).

EFFECTS OF THE INVENTION As is apparent from the above description, the present invention utilizes the provision of columnar or columnar plate electrodes and insulating films on the upper and lower portions of a polysilicon gate electrode and a dummy polysilicon gate electrode. By forming an electric charge, an extremely large amount of electric charge can be stored, which is resistant to soft error. Further, as the gate length increases, hot carrier deterioration is prevented.

[Brief description of the drawings]

1A is a sectional view of a semiconductor memory device according to a reference example of the present invention, FIG. 1B is a pattern diagram thereof, and FIG. 2A is a sectional view of a semiconductor memory device according to another reference example. ,
2B is a horizontal sectional view of FIG. 2A, FIG. 3 is a sectional view of a semiconductor memory device according to an embodiment of the present invention, and FIG. 4 is a sectional view of a semiconductor memory device according to another reference example. It is a figure. 1 ... semiconductor substrate, 2 ... gate oxide film, 3,3a ... polysilicon gate, 3b ... dummy polysilicon gate, 4,
4a ... diffusion layer, 4b ... second diffusion layer, 5 ... first plate, 6 ... second plate, 7 ... insulating layer, 8 ... polysilicon electrode, 9 ... aluminum electrode, 10 , 14 ... Capacitive insulating film, 12 ... Third plate, 13 ... Fourth plate, 15
…… Epitaxial layer, 16 …… Groove.

Claims (1)

(57) [Claims] 1. A groove formed in a first conductive type semiconductor substrate, a fourth plate electrode formed on an inner side wall of the groove, a fourth plate electrode and a first capacitive insulating film. A first capacitor having a third plate electrode interposed between the first capacitor and a first conductivity type epitaxial layer formed above the groove, and a MOS transistor is formed on the gate electrode of the MOS transistor via an insulating film. Contact the second plate electrode and the diffusion layer of the MOS transistor that contacts a part of the fourth plate electrode,
A semiconductor memory device comprising a second capacitor having a plate electrode of 1) and a first plate electrode interposed by a second insulating film.