JP2671325B2 - Data processing device - Google Patents

Description

The present invention relates to a data processing device that constitutes an office computer, a personal computer, or the like. [Prior Art] Conventionally, a central processing unit constituting an office computer or the like is configured to perform processing such as transfer and calculation in fixed-length 1-byte units with one instruction. By the way, a file is input / output with one record as a minimum unit, and one record is composed of a plurality of fields. Usually, a field is composed of a plurality of bytes, and the data in the record is updated with the field as a minimum unit. Therefore, in file data processing, processing is often performed in units of a plurality of bytes. [Problems to be Solved by the Invention] As described above, since the conventional central processing unit can perform processing only in a unit of 1 byte having a fixed length by one instruction, in filing, it is performed in units of fields or records. When performing data processing, a subroutine program consisting of a plurality of instructions had to be created and processed. Therefore, there is a drawback that the work time for creating the program becomes long and the processing speed becomes slow. An object of the present invention is to process data of an arbitrary length with one instruction, thereby significantly improving the processing speed. [Means for Solving Problems] Means of the present invention are as follows. Data storage means 1 (see the functional block diagram of FIG. 1,
The same shall apply hereinafter) stores a plurality of types of delimiters that indicate data and delimiters of this data, and indicate weighting according to the priority of processing. The address generation means 2 generates an address for the data storage means 1. The command word storage unit 3 stores a command word and one specified delimiter indicating a weight corresponding to the command word and designated according to the priority order of processing according to the command word. The control means 4 decodes the instruction word stored in the instruction word storage means 3 and processes the data sequentially read from the data storage means 1 according to the address designation of the address generation means 2 according to the instruction word. The detection means 5 compares the delimiter read from the data storage means 1 by the address designation of the address generation means 2 with the designated delimiter stored in the instruction word storage means 3 and read from the data storage means 1. When the delimiter has a higher priority than the designated delimiter or the same priority, the detection signal is output to the control means 4. Then, the control means 4 continues the processing according to the command word when the detection signal is not input, and ends the processing according to the command word when the detection signal is input. [Operation] The operation of the means of the present invention is as follows. First, the data storage unit 1 stores a plurality of types of delimiters that indicate the data and the delimiters of the data, and also indicate the weighting according to the priority order of processing, and the command word storage unit 3 stores the command word and this command word. One designated delimiter indicating the weighting correspondingly designated and according to the priority of the processing according to this command is stored. In this state, the control means 4 controls the instruction word storage means 3
The address generation means 2 decodes the instruction word stored in
The data sequentially read from the data storage means 1 by the address designation of
Performs processing such as calculation. Further, the detection means 5 compares the delimiter read from the data storage means 1 by the address designation of the address generation means 2 with the designated delimiter stored in the instruction word storage means 3 and read from the data storage means 1. When the delimiter has a higher priority than the designated delimiter or the same priority, the detection signal is output to the control means 4. In this case, the control means 4 continues the processing according to the command word when the detection signal is not input, and ends the processing according to the command word when the detection signal is input. Therefore, one instruction enables data processing of an arbitrary length, and the processing speed can be greatly improved. [First Embodiment] A first embodiment will be described below with reference to FIGS. 2 to 4. Structure FIG. 2 is a block circuit diagram of a central processing unit that constitutes an office computer, etc. The instruction register 11 is read from a program memory (not shown) connected via an address bus AB and a data bus DB. The instruction code stored in the instruction register 11 is supplied to the instruction decoder 12, the address change direction is supplied to the address generation circuit 13, and the designated delimiter is supplied to the delimiter detection circuit 14. It The instruction decoder 12 decodes an input operation code and outputs an output signal based on the decoding result to a control circuit.
Give to 15. The control circuit 15 outputs a control signal c necessary for executing the instruction decoded by the instruction decoder 12 to the address generation circuit 13 and the like. The address generation circuit 13 responds to the control signal output from the control circuit 15 and increments or decrements the read address and the write address according to the address update direction from the instruction register 11 for each execution cycle. Address is supplied to the main memory device through an address bus AB. In this case, when the data designated by the read address of the address generation circuit 13 is read from the main storage device, it is stored in the read buffer 16 via the data bus DB. Further, when the data designated by the write address of the address generation circuit 13 is read from the main memory,
It is stored in the read buffer 17 via the data bus DB.
If the operation code stored in the instruction register 11 is an instruction that performs an operation on the operand data such as an arithmetic logic operation instruction, the operand data is set in the read buffer 16 and the operand data is set in the read buffer 17. To be done. In this case, the operation data and operation data in the read buffers 16 and 17 are ALU (logical operation circuit) 18
ALU 18 performs an operation according to the operation instruction from the instruction decoder 12, and the operation result is fetched in the data bus buffer 19 and then supplied to the main memory device via the data bus DB, and the address generation circuit 13 Is written in the address area specified by the write address of. On the other hand, when the instruction designated by the operation code of the instruction register 11 is a transfer instruction, the data designated by the read address of the address generation circuit 13 is read from the main storage device and set in the read buffer 16. Then, when the write address is output from the next address generation circuit 13 and the data set in the read buffer 16 is supplied to the main storage device via the ALU 18 and the data buffer 19, the data is designated by the write address. Are written in the address area. The delimiter detection circuit 14 is an instruction register 11
The specified delimiter stored in or the setting delimiter preset in the delimiter specification register 20 is compared with the data (delimiter) set in the read buffer 16, and the comparison result (when both delimiters match, etc. )
The detection signal a is output in accordance with the above, and is supplied to the control circuit 15. When the detection signal a is input from the delimiter detection circuit 14, the control circuit 15 terminates the output of the control signal for executing the instruction and outputs the termination signal b to specify the reading of the next instruction word from the program memory. I do. FIG. 3 shows a specific configuration of the delimiter detection circuit 14. First, the delimiter handled in this embodiment will be described. The delimiter indicates the delimiter of data in the main storage device and also indicates the weighting of the priority of processing, and there are the following four types. (... record start 9 _N ... word end (for numerical value) 9 ... word end (for character) In addition, each delimiter consists of 1 byte and is expressed by a hexadecimal code. The track end is "FF" and the record end is " FE ", the word end for numerical values corresponds to" FD ", and the word end for characters corresponds to" 0 ". In addition to these four types of fixed delimiters, in the present embodiment, an arbitrary delimiter setting register 20 is set. A delimiter can be set, and there are 5 types of delimiters in addition to this setting delimiter, and these 5 types of delimiters are given the following priority order: from the highest priority order (1) This is a fixed order in the order of track end, (2) record start, (3) two types of word end, and (4) setting delimiter in delimiter setting register 20. The numerical word end and the character word end have the same priority, and the code set in the designated delimiter of the instruction register 11 is expressed by a binary code of 2 bits, where "11" is the track end and " 10 "indicates the record start," 01 "indicates the word end (for numerical value)," 00 "indicates the word end (for character), and is represented by a 1-byte hexadecimal code indicating the data delimiter in the main memory. It is associated with the delimiters “FF”, “FE”, “FD”, and “00.” The delimiter detection circuit 14 is supplied with four delimiters from the instruction register 11 as shown in FIG. Matching circuits 14-1 to 14-4 and read buffer 16
5 matching circuits 14 supplied with read delimiters from
-5 to 14-9 are provided. The four matching circuits 14-1 to 14-4 are supplied with corresponding fixed delimiters of "00" to "11", and each fixed delimiter is represented by a binary code having a 2-bit structure. Therefore, the coincidence circuits 14-1 to 14-5 use the designated delimiters (binary codes “00”, “01”, 1 and 1 from the instruction register 11).
"0", "11" and outputs any one of signals of the coincidence signal c ₁ to c ₄ when the coincidence has been detected with the specified code) of the, and supplies the comparison circuit 14-10. In this case, the matching circuit 14-
The outputs of 1 and 14-2 are wired or. Also,
The comparator circuit 14-10 has a delimiter setting register when an arbitrary delimiter is set in the delimiter setting register 20.
The setting signal c ₀ output from 20 is input, and the matching circuit
It is input as 4-bit data B together with the outputs of 14-1 to 14-4. It should be noted that each digit of the 4-bit data B is given a weight of "1, 2, 4, 8" corresponding to the priority, and the set signal c ₀ has a weight of "1" and c ₁ orc ₂ has a weight of " ₁ ". 2 ",
c ₃ corresponds to the weight “4”, and c ₄ corresponds to the weight “8”. In addition, 1 is input to the other of the five matching circuits 14-5 to 14-9 to which the read delimiter from the read buffer 16 is input.
A code for matching detection, which is expressed in hexadecimal code in byte structure, is input. That is, the matching circuit 14-5 includes the set delimiter code in the delimiter setting register 20 and the matching circuit.
14-6 shows a "00" code indicating a character word end, and a matching circuit 14-7 shows "F" indicating a numerical word end.
The D "code, the" FE "code indicating the record start, and the" FF "code indicating the track end are input to the matching circuit 14-8 and the matching circuit 14-9, respectively.
5-14-9 output coincidence signals d ₀ , d ₁ ... D ₄ when detecting coincidence with the read delimiter from the read buffer 16 and give them to the comparison circuit 14-10. In this case, the matching circuit 14-
The outputs of 6 and 14-7 are wired-OR. Therefore, the outputs of the coincidence circuits 14-5 to 14-9 are input to the comparison circuit 14-10 as 4-bit data A. In addition,
Each digit of the 4-bit data A is weighted with "1, 2, 4, 8" corresponding to the order of presence of the delimiter, and the coincidence signal d ₀
Corresponds to weight “1”, d ₁ ord ₂ corresponds to weight “2”, d ₃ corresponds to weight “4”, and d ₄ corresponds to weight “8”. The comparison circuit 14-10 compares the data A and the data B, and as a result, when AB ≧ 0, outputs the detection signal a. Operation Now, as shown in FIG. 4, various delimiters (word end for character, record start) are stored in the data d (d is represented by a hexadecimal code in 1-byte structure) stored in the main memory MM. , Track end) and stored in the main memory MM in a predetermined unit. In the following description, it is assumed that the instruction designated by the operation code set in the instruction register 11 is a transfer instruction. In this case, the data in the main memory device MM read by the read address from the address generation circuit 13 is set in the read buffer 16. Next, address generation circuit
The write address is output from 13 and the data in the read buffer 16 is read and written in the designated address area of the main memory MM. At this time, the data in the read buffer 16 is also sent to the delimiter detection circuit 14, but if the data is not the delimiter, the delimiter detection circuit 14 outputs the detection signal a.
Is not output, the control circuit 15 outputs the control signal for executing the transfer instruction again, updates each address of the address generation circuit 13, and the next data in the main memory MM is set in the read buffer 16. It In the state where the delimiter read from the main storage device MM is set in the read buffer 16 during the execution of such data transfer, the delimiter detection circuit 14 specifies the delimiter from the instruction register 11 or the delimiter setting register 20 from the delimiter setting register 20. The set delimiter is compared with the delimiter set in the read buffer 16, and as a result, when the delimiter having a higher priority than the designated delimiter or the set delimiter or the same priority is set in the read buffer 16, the detection signal a is output. Output. Now, it is assumed that the designated delimiter in the instruction register 11 is the delimiter "00" corresponding to the character word end "9", and the same delimiter "9" is read into the read buffer 16. In this case, in the delimiter detection circuit 14, the matching circuit 14-1,
Since the coincidence signals c ₁ and d ₁ are respectively output from 14-6, the data A and B become “2”, respectively, and the comparison circuit 14-10 outputs the detection signal a. When the detection signal a is given to the control circuit 15, the control circuit 15 ends the execution of the transfer instruction and outputs the end signal b. As a result, the next operation code is set in the instruction register 11. When the designated delimiter is the word end for characters in this way, as shown in FIG.
Since the execution of the transfer instruction is completed when the delimiter is first set in the read buffer 16 read from the MM,
Data is transferred in units of the data length separated by this delimiter. In addition, the read buffer 16 has a delimiter "(" or a delimiter "(" or a Even when is read, the detection signal a is output from the comparison circuit 14-10 and the execution of the transfer instruction is completed. Next, the designated delimiter in the instruction register 11 is the delimiter "10" corresponding to the record start "(".
In this case, even if the character word end delimiter “9” is read from the main memory MM, in the delimiter detection circuit 14, the match signals c ₃ and d _{1 are} received from the match circuits 14-3 and 14-6. Is output, the data A becomes “2” and the data B becomes “4”. That is, since the delimiter set in the read buffer 16 has a lower priority than the designated delimiter, the detection signal a is not output from the comparison circuit 14-10, and as a result, the data transfer process is repeatedly executed. .
Then, when the delimiter "(" indicating the first record start is read from the main memory MM and set in the read buffer 16, the delimiter detection circuit 14 matches from the matching circuits 14-3 and 14-8. Since the signals c ₃ and d ₃ are output, the data A and B respectively become “4”, and the comparison circuit 14-10
Outputs a detection signal a. Therefore, if the designated delimiter is the record start, the execution of the transfer instruction ends when the delimiter indicating the record start is first read from the main memory MM as shown in FIG. 4B. Data transfer is performed in units of the data length delimited by the delimiter. Also, the delimiter with a higher priority than the delimiter "(" Is also read into the read buffer 16, the execution of the transfer instruction is completed. Similarly, the designated delimiter in the instruction register 11 is the track end. If the delimiter "11" corresponding to
From its delimiter Is read out, the match signals c ₄ and d ₄ are output from the match circuits 14-4 and 14-9 in the delimiter detection circuit 14,
The data A and B respectively become "8", and the detection signal a is output from the comparison circuit 14-10. Therefore, data transfer is performed in units of the data length with the delimiter at the track end delimited (FIG. 4). In this way, if any one of the four types of fixed delimiters is designated corresponding to the instruction word in the instruction register 11, one instruction word (transfer instruction)
This enables data transfer in units of data of arbitrary length. In addition, the delimiter establishment register 20 can be
When any delimiter is set to, the type of delimiter can be increased to 5 including fixed delimiter, and since the setting delimiter has the lowest priority, the data delimited by the word end delimiter can be used. It can be further divided into a plurality of blocks, and data transfer can be performed in units of this block. Furthermore, by distinguishing the word end delimiter for numeric value and character and setting the same priority order, it is possible to determine the type of data only by determining the delimiter code, and the data in which numeric value and character are mixed. However, since the priorities are the same, they can be processed in the same processing unit. When the operation code is an operation instruction or a logical operation instruction, the operation is executed based on the operation data and the operated data stored in consecutive addresses of the main storage device. Processing in delimiter units is the same as in the case of data transfer. Second Embodiment FIG. 5 is a block diagram of the delimiter detection circuit 31 showing the second embodiment. In this embodiment, four kinds of delimiters can be set by arbitrary codes, and their priority can be set arbitrarily. That is, the delimiter setting registers 31-1 to 31-4 are registers in which four kinds of delimiters are set, and the set delimiters are supplied to the corresponding coincidence circuits 31-5 to 31-8. This matching circuit 31-
Reference numerals 5 to 31-8 output coincidence signals when the coincidence with the delimiter from the read buffer 16 shown in FIG. 2 is detected, and the coincidence signals are given to the comparison circuit 31-13. Each digit of this 4-bit data A is
Weights of "1, 2, 4, 8" are assigned according to the priority order, and the output of the matching circuit 31-5 is weighted "1".
The output of 8 corresponds to the weight “8”. In addition, the instruction register 11 shown in FIG.
Matching circuit to which the specified delimiters "00" to "11" are supplied from
31-9 to 31-12 are the same as those in the first embodiment, but in this embodiment, each digit of the 4-bit data B from the coincidence circuits 31-9 to 31-12 corresponds to the priority order. "1, 2, 3,
The output of the coincidence circuit 31-9 is weighted by "1".
The output of the coincidence circuit 31-12 corresponds to the weight "8" and is supplied to the comparison circuit 31-13. Further, the comparator circuit 31-13 compares the data A and B, and outputs the detection signal a when AB ≧ 0, as in the above embodiment. With this configuration, the four types of delimiters can be set by arbitrary codes, and their priorities can also be set arbitrarily. The code of the designated delimiter in the instruction word and the code of the delimiter in the data may or may not use the same code. If the same code is not used, the code of the delimiter used for the specified delimiter and the code of the delimiter used in the data are made to correspond in advance,
When the delimiter detection circuit 14 detects, both delimiters are detected based on the above correspondence. [Effects of the Invention] According to the present invention, it is possible to perform processing such as transfer and operation of data of arbitrary length delimited by a single command word, improving the data processing speed and Since programs for processing can be easily created and data can be processed according to the priority of the delimiter, if the data is divided into blocks at the level corresponding to the priority in advance, various levels can be set. The processing in block units can be performed with one instruction word.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a functional block diagram of the present invention, FIGS. 2-5 show a first embodiment, FIG. 2 is an overall block circuit diagram, and FIG. 3 is FIG. 4 is a diagram showing a specific configuration of the delimiter detection circuit 14 shown in FIG. 4, FIG. 4 is a diagram for explaining a data unit to be processed corresponding to a designated delimiter, and FIG. 5 is a second embodiment. It is the figure which showed the concrete structure of the delimiter detection circuit. 11 …… instruction register, 12 …… instruction decoder, 13 …… address generation circuit, 14,31 …… delimiter detection circuit, 15 …… control circuit, 16 …… read buffer, 18 ……
ALU, 20 ... Delimiter setting register, MM ... Main memory.

Claims (1)

(57) [Claims] Data storage means for storing data and a plurality of types of delimiters for indicating the division of the data and weighting according to the priority of processing, address generation means for generating an address for the data storage means, command word and this command An instruction word storage unit that stores one designated delimiter that is designated corresponding to a word and indicates weighting according to the priority of processing according to this instruction word, and an instruction word stored in this instruction word storage unit. Decipher,
Control means for processing data sequentially read from the data storage means according to the instruction word by the address designation of the address generation means; delimiter read from the data storage means by the address designation of the address generation means and the instruction The designated delimiter stored in the word storage means is compared, and when the delimiter read from the data storage means has a higher priority than the designated delimiter or the same priority, a detection signal is sent to the control means. Detecting means for outputting, and the control means continues the processing according to the command word when the detection signal is not input, and the processing according to the command word when the detection signal is input A data processing device characterized by terminating.