JP2667673B2 - Integrator circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrating circuit, and more particularly, to an integrating circuit suitably implemented for controlling exposure of a camera.

2. Description of the Related Art For example, in a camera having a focal plane shutter, in order to obtain a proper exposure, a photodiode receives light reflected from a shutter surface or a film surface of light incident through a lens, and integrates an output photocurrent of the photodiode. A method of controlling the shutter speed by using a camera has been put to practical use, and an integrating circuit for this purpose is incorporated in a camera.

FIG. 2 is an electric circuit diagram of a shutter control circuit 11 using an integrating circuit according to the prior art. In FIG. 2, the first magnet coil 12 is a first switching transistor.
The shutter (not shown) is opened by turning on / off Q16, and the second magnet coil 13 is turned on / off by turning on / off the second switching transistor Q17 to close the shutter. The first and second switching transistors Q16 and Q17 are of the NPN type and have base resistors R14 and R14, respectively.
The output voltage v14, v15 of the first operational amplifier 14 and the second operational amplifier 15 input via R15 controls the conduction / cutoff, and thus controls the opening / closing of a shutter (not shown).

A first reference voltage e11 and a second reference voltage e12 are individually applied to the non-inverting input terminals of the first and second operational amplifiers 14 and 15 in advance, respectively. The output voltage v16 from the amplifier 16 is level-discriminated based on the first reference voltage e11 and the second reference voltage e12. Here, the first and second reference voltages e11 and e12 are determined in a relationship of Vcc>e11>e12> GND (1). Where Vcc is the power supply voltage, for example, 3
V and GND are ground potentials, for example, 0V, and the first reference voltage e11 can be set to different values depending on film sensitivity, for example, 2V, and the second reference voltage e12 is, for example, 1V.

Between the inverting and non-inverting input terminals of the third operational amplifier 16, a photodiode 17 is connected in parallel with the anode side as the non-inverting terminal side.
A parallel circuit of an integrating capacitor 18 and a release switch 19 is connected between them. The release switch 19 conducts between its contacts a and b until the shutter release is turned on, and the integrating capacitor 18 is short-circuited.

A current mirror circuit 21 is formed by the plurality of PNP transistors Q11 to Q13 and the constant current element 20, and the constant current element 20 is, for example, a high-impedance element.
21 is activated, and a current i13 equal to the constant current i20 determined by the element constant flows through the transistor Q13 in the direction of the line l12 which is the ground potential GND.

On the other hand, the transistor Q11 functions as a switching element.
The emitter is short-circuited to deactivate the current mirror circuit 21 and cut off the constant current i13. The conduction / cutoff of the transistor Q11 is controlled by a drive circuit 22 including a plurality of resistors R11 to R13 and NPN transistors Q14 and Q15.

When the shutter release is turned on and the release switch 19 is shut off, the constant current i13 flowing to the line l12 via the release switch 19 charges the integration capacitor 18, so that the output voltage v16 of the third operational amplifier 16 becomes To rise. When the output voltage v16 reaches the second reference voltage e12, the output voltage v15 of the second operational amplifier 15 is inverted to a low level "L", the second switching transistor Q17 is cut off, and the second magnet coil 13 is demagnetized. , A shutter (not shown) opens.

Therefore, the photodiode 17 is activated by the incident light L from the subject, and the photocurrent id flows in a direction to charge the integrating capacitor 18. At the same time, the base of the transistor Q15 of the drive circuit 22 becomes "L" from the line l13 via the resistor R16, so that the transistor Q15 is turned off and the transistor Q14 is turned on.
As a result, the transistor 1 becomes conductive and short-circuits the transistor Q12 forming the current mirror circuit 21. As a result, the constant current i13 is cut off. Therefore, thereafter, the integrating capacitor 18 is charged by the photocurrent id.

When the charging with the photocurrent id advances and the output voltage v16 of the third operational amplifier 16 further rises and reaches the first reference voltage e11,
The output voltage v14 of the first operational amplifier 14 is inverted, and the first switching transistor Q16 is shut off. Therefore the first
The magnet coil 12 is demagnetized, a shutter (not shown) closes, and the shutter operation ends. The flash operation accompanying the opening and closing of the shutter is performed simultaneously.

What regulates the shutter time in the above-described conventional shutter control is a constant current i13 that flows into the integrating capacitor 18 via the transistor Q13 of the current mirror circuit 21 and charges the integrating capacitor 18. Even if the transistor Q11 serving as the switching element is turned on, the current mirror circuit 21 is not immediately deactivated. This is the transistor
The conduction of Q11 raises the base potential of the transistor Q13 to the power supply voltage Vcc side.
This is because charges flow into the integration capacitor 18 due to the influence of the parasitic capacitance Cbc interposed between the collectors.

For this reason, the prior art has a problem that an error occurs in the exposure time. Therefore, solving such a problem has been a technical problem.

The present invention has been made in view of the above technical problem, and an object of the present invention is to provide a high-precision integration circuit that prevents an integration time error due to movement of electric charge or the like.

Means for Solving the Problems The present invention provides a power storage means for discharging or charging a charge, a current mirror circuit for supplying a constant charging current to the power storage means and charging the power storage means, Until the value reaches the value, the output current of the current mirror circuit is supplied to the power storage means, and after the charge stored in the power storage means reaches a predetermined value, the output current of the current mirror circuit is bypassed to store the power. An integration circuit comprising: switching means for stopping supply to the means; and backflow prevention means disposed between the output of the current mirror circuit and the power storage means to prevent backflow from the power storage means. .

The integration circuit according to the present invention charges the power storage means by a current mirror circuit that supplies and charges a constant current to the power storage means, and drives the switching means when the charge amount reaches a predetermined level to drive the current mirror circuit. Invalidate. Undesirable movement of the charges at that time is prevented by the bypass to the ground potential by the switching means and the backflow prevention means arranged between the current mirror circuit and the power storage means to prevent the backflow from the power storage means side.

Embodiment FIG. 1 is an electric circuit diagram of a shutter control circuit 1 using an integrating circuit according to an embodiment of the present invention. In FIG.
The integrating circuit 2 includes an integrating capacitor C that is a power storage unit that discharges or charges the electric charge, a current mirror circuit 3 that is a charging unit that supplies a constant charging current i2 to the integrating capacitor C, and charges the current mirror circuit 3. It includes a plurality of NPN transistors Q3 and Q4 as switching means for controlling active / inactive, and a PNP transistor Q5 as backflow preventing means for preventing backflow from the power storage means side to the charging means side. The operation of the integration circuit 2 will be described later.

The first magnet coil 4 is excited / demagnetized by the conduction / interruption of the first switching transistor Q6 and opens a shutter (not shown), and the second magnet coil 5 is excited / demagnetized by the conduction / interception of the second switching transistor Q7. Close the shutter. The first and second switching transistors Q6, Q7 are both NPN types, and the first operational amplifier 6, which is input via respective base resistors R2, R3,
The on / off of the second operational amplifier 7 is controlled by the output voltages v6 and v7. Therefore, the opening and closing of a shutter (not shown) is controlled.

A first reference voltage e1 and a second reference voltage e2 are individually supplied in advance to the non-inverting input terminals of the first and second operational amplifiers 6 and 7, respectively. The output voltage v8 from the three operational amplifier 8 is level-discriminated by the first reference voltage e1 and the second reference voltage e2. Here, the first and second reference voltages e1 and e2 are determined in a relationship of Vcc>e1>e2> GND (2). Where Vcc is the power supply voltage, for example, 3
V and GND are ground potentials, for example, 0V, and the first reference voltage e1 can be set to different values depending on film sensitivity, for example, 2V, and the second reference voltage e2 is set, for example, to 1V.

Between the inverting and non-inverting input terminals of the third operational amplifier 8, a photodiode D is connected in parallel with the anode side to the non-inverting terminal side, and an integrating capacitor C is connected between the non-inverting terminal and the line l2 which is the ground potential GND. A parallel circuit of the release switch S is connected. The release switch S conducts between its contacts a and b until a shutter release (not shown) is turned on.
The integration capacitor C is short-circuited during this time.

The current mirror circuit 3 includes a plurality of PNP transistor Qs.
The constant current element 9 is formed of, for example, a high impedance element, drives the current mirror circuit 3, and outputs a constant current i1 equal to the constant current i2 determined by the element constant from the transistor Q2. Output, and flows in a direction to charge the integration capacitor C via the transistor Q5.

On the other hand, the switching means for controlling the current mirror circuit 3 to be active / inactive is constituted by a plurality of transistors Q3 and Q4, and the transistor Q3 is provided with an output voltage v7 of the second operational amplifier 7 supplied from a line l3 via a resistor R4. The conduction / interruption is controlled by.

When the transistor Q3 is conducting, the connection point between its collector and the collector resistor R1, that is, the base of the transistor Q4 is "L".
Therefore, the transistor Q4 is turned off. In the opposite case,
That is, when the transistor Q3 is cut off,
Q4 conducts and the collector of transistor Q2 is at approximately the same potential as line l2. Therefore, the bypass current indicated by the broken line
Although i3 flows out to the line l2, the bypass current i3 does not contribute to the charging of the integrating capacitor C at all. In this state, the current mirror circuit 3 viewed from the integrating capacitor C side is equal to inactivated.

When a shutter release (not shown) is turned on, the release switch S is interlocked, and the contact between a and b is cut off. Therefore, the constant current i1, which has been flowing to the line l2 through the release switch S, charges the integrating capacitor C. As the charging progresses, the output voltage v8 of the third operational amplifier 8 increases, and when the output voltage v8 reaches the second reference voltage e2, the output voltage v7 of the second operational amplifier 7 is inverted to a low level "L". , The second switching transistor Q7 is shut off, the second magnet coil 5 is demagnetized, and a shutter (not shown) opens.

Therefore, the photodiode D is activated by the incident light L from the subject, and the photocurrent id flows in a direction to charge the integrating capacitor C. At the same time, the base of the transistor Q3 becomes "L" from the line l3 via the resistor R4, so that the transistor Q3 is turned off and the transistor Q4 is turned on. Therefore, the constant current from the transistor Q2 forming the current mirror circuit 3 is as described above. The current becomes the bypass current i3.
The battery is charged by id, and the integration time by this is naturally different from that by the constant current i1.

When the charging by the photocurrent id advances and the output voltage v8 of the third operational amplifier 8 further rises and reaches the first reference voltage e1, the output voltage v6 of the first operational amplifier 6 is inverted to "L",
The first switching transistor Q6 is cut off. Therefore, the first magnet coil 4 is demagnetized, the shutter (not shown) closes, and the shutter operation ends. The flash operation accompanying the opening and closing of the shutter is performed simultaneously.

Referring again to FIG. 2, as described above, in the conventional technique, the active / inactive state of the current mirror circuit 21 involved in the integration operation is determined.
Deactivate the switching element Q11
It was done by shutting off / conducting. Although the current mirror circuit 21 is deactivated by the conduction of the transistor Q11, the base potential of the transistor Q13 rises at that time, and the charge flows into the integrating capacitor 18 due to the influence of the base-collector capacitance Cbc indicated by the broken line. However, it is unavoidable that an error occurs in the integration time.

On the other hand, according to the present invention, as shown in FIG. 1, the transistor Q4 is turned on and the emitter of the transistor Q5 is dropped to the ground potential, so that the charging by the constant current i1 is stopped. At this time, the charge from the current mirror circuit 3 is bypassed to the ground potential by the transistor Q4, and the voltage Vbc between the base and the collector of the transistor Q5 does not change, so that the charge on the integration capacitor C does not move. Therefore, there is no problem caused by the movement of charges as in the prior art.

Effect of the Invention As described above, the integration circuit according to the present invention prevents the transfer of electric charge when the charging of the integration capacitor from the constant current circuit side is stopped, so that a stable and highly accurate integration operation is performed. Run. Therefore, when the present invention is applied to, for example, exposure control of a camera, a highly accurate control operation can be realized.

[Brief description of the drawings]

FIG. 1 is an electric circuit diagram of a shutter control circuit using an integration circuit according to one embodiment of the present invention, and FIG. 2 is an electric circuit diagram of a shutter control circuit using an integration circuit according to the prior art. 1 shutter control circuit, 2 integration circuit, 3 current mirror circuit, 4, 5 magnet coil, 6 to 8
Calculation circuit 9, Constant current element D, Photodiode, e1, e2 Reference voltage, Q1 to Q5 Transistor Q6,
Q7: Switching transistor, R1 to R4: Resistance, S
...... Release switch

Claims (1)

(57) [Claims] An electric power storage means for discharging or charging the electric charge; a current mirror circuit for supplying a constant charge current to the electric power storage means for charging; The output current of the current mirror circuit is supplied to the power storage means, and after the stored charge of the power storage means reaches a predetermined value,
Bypassing the output current of the current mirror circuit,
Switching means for stopping supply to the power storage means; and backflow prevention means disposed between the output of the current mirror circuit and the power storage means for preventing backflow from the power storage means. Integrator circuit.