JP2667644B2 - Method of manufacturing heterojunction bipolar transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a high-speed bipolar transistor useful for a high-speed information processing system such as a computer and a communication device, and more particularly, to a base parasitic resistance utilizing a metallic thin film (metallic silicide). (Base parasitic re
The present invention relates to a method for manufacturing a heterojunction bipolar transistor with greatly reduced stability.

[0002]

2. Description of the Related Art The degree of integration has been improved or the size of devices has been reduced by scaling.
g down), the operating speed of the device is improved, but its operating characteristics are limited.

The reason is that the impurity concentrations of the emitter and the base increase.

In order to improve the operation characteristics, a heterojunction bipolar transistor has recently been proposed in which the Si-based material is substituted for SiGe and the energy band gap is reduced and the characteristics of the gradient are utilized by adding Ge.

Recently, in order to improve the performance of such a heterojunction bipolar transistor, that is, to reduce the parasitic capacitance between the base and the emitter / base existing on the active region, a thin film for the base electrode is formed of a poly-electrode. Research on a process of using a metal silicide, for example, TiSi ₂ instead of silicon, has been actively conducted.

FIG. 1 shows a method of using a selective epitaxy-grown SiGe as a base 5 and forming a metal silicide which is a heat treatment compound with the SiGe as a base electrode thin film 9.
2 illustrates the structure of a heterojunction bipolar transistor manufactured by using the above.

With reference to FIG. 1, the transistor manufacturing process will be briefly observed.

On the semiconductor substrate 1 on which the collector 2, the collector sinker 4 and the oxide film 3 are formed, a SiGe base layer 5 is grown by a selective epitaxial growth method. Subsequently, after forming an insulating film pattern 7 to define an emitter region, an emitter 9 and a sidewall oxide film 8 are formed.
A metal is selectively deposited only on the inactive region of the base layer, and then heat-treated to form a base electrode thin film 6 made of a metallic silicide. The wiring electrode 11 is formed by exposing a part of the base electrode thin film 6 to complete the fabrication.

According to this method, the injection efficiency of the emitter is increased by using SiGe as the intrinsic base 5 as described above, and the parasitic resistance of the base is increased by using metallic silicide as the thin film 6 for the base electrode. The operating characteristics of the element are improved by reducing the resistance of the silicide 6 and the combined resistance of the contact resistance between the silicide 6 and the wiring electrode 11).

[0010]

However, the metallic silicide forming the base electrode thin film 6 is formed through a heat treatment process of the semiconductor material forming the base layer 5 and the metal deposited thereon. Therefore, a loss of the thickness of the base layer 5 is caused. As a result, the thickness of the metallic silicide 6 for reducing the parasitic resistance of the base can only be reduced to a thin film.

In addition, when considering that the region that reacts with the metal to form the silicide is an ultra-thin base layer 5 having a thickness of about 500 angstroms, The thickness of silicide 6 can only be more limited.

Accordingly, the sheet resistance of the silicide 6 is increased, and the decrease in the base parasitic resistance is limited by the thickness of the metallic silicide which is the base electrode thin film 6.

The present invention has been made in view of such a technical background, and an object of the present invention is to provide a method for forming a metal silicide as a thin film for a base electrode without losing the thickness of the base. To reduce the parasitic resistance of the base.

Another object of the present invention is to provide a heterojunction bipolar transistor in which the thickness of the metallic silicide thin film can be arbitrarily varied according to the characteristics of the transistor to improve the operation characteristics from a high frequency band and simplify the process. It is to provide a manufacturing method of.

The features of the present invention for achieving the above object are as follows: a) A conductive buried collector is formed by ion-implanting a high-concentration impurity into a silicon substrate, and a collector is provided above the buried collector for device isolation. Forming an oxide film and a collector sinker; b) growing a thin conductive base layer on the entire surface of the substrate by using an epitaxial growth technique; c) using a predetermined oxide film pattern as a mask. Implanting high-concentration impurities only into the extrinsic base region of said base; and d) metallic silicide using an alloy compound source above said extrinsic base region into which said high-concentration ions are implanted. E) a step of forming a capping oxide film on top of the metallic silicide thin film by chemical vapor deposition; / An oxide film for the base isolated from the deposition, in order to open the collector sinker, the oxide layer utilizing a predetermined photosensitive film as a mask,
Patterning a capping oxide film, a thin film for a base electrode, and a base layer to form a sidewall oxide film on sidewalls of the pattern portion; And h) a metal wiring step of forming an electrode after forming a protective film and opening a contact hole.

In the step (e), the capping oxide film can be formed, for example, to a thickness of about 500 angstroms. Further, in the step (f), the oxide film is formed to have a thickness of, for example, about 2000 to 4000 angstrom.
It can be formed to a film thickness.

Other features of the present invention will become more apparent from the embodiments described in detail with reference to the accompanying drawings.

[0018]

FIG. 2 shows a cross-sectional structure of a heterojunction bipolar transistor manufactured according to the present invention.
5A to 5H are process cross-sectional views illustrating a method for manufacturing the transistor of FIG. 2 for each step.

For the sake of simplicity, each element constituting the element is denoted by the same reference numeral as in FIG.

FIG. 3 shows a preferred embodiment of the present invention.
This will be described in detail with reference to (A) to FIG.

Referring to FIG. 3A, a conductive buried collector 21 is formed by ion-implanting a high-concentration impurity into a semiconductor substrate (not shown), and the semiconductor buried collector 21 is formed in-situ.
u) After growing the doped collector epitaxial layer 22 in a single crystal, an oxide film 23 for element isolation is formed, and a high concentration impurity is ion-implanted to form a collector sinker 24.

Subsequently, molecular beam epitaxy (MBE) or ultra-high vacuum chemical vapor deposition (UHD /
A thin SiGe base layer 25 is grown by using an epitaxial growth technique such as CVD, etc.
Approximately 1000 angstrom thick oxide film 13 by LPC
Deposited by VD or PECVD.

At this time, as a material of the conductive base layer 25, a single-layer single-crystal SiGe and a two-layer SiGe / S
i, or 3 layers of Si / SiGe / Si can be used.

In the case of the single-layer SiGe base 25, an impurity concentration is added to a high concentration of 1 × 10 ¹⁸ cm ⁻³ or more in order to increase conductivity.

The Si / SiGe two-layer structure base 25
Cases, can grow by adding to 1 × 10 ¹⁸ cm ^-3 or more high density only on contact with the emitter below the impurity concentration of the SiGe.

Also, the germanium (Ge) content distribution in the SiGe base 25 can be changed linearly.

For example, the Ge content distribution is kept constant at 30% or less, from the lower part to the upper part linearly changes from 30% to 0%, or from the lower part to the upper part from 30% or less to a certain part. After that, germanium (Ge) is changed by a method of linearly changing to 0% again or a method of linearly increasing from 0% to 30% or less and then linearly decreasing again from 30% or less to 0%. ) Can be grown while changing the content distribution.

Referring to FIG. 3B, the oxide film 13 is patterned to expose an extrinsic base region, and then the energy of 30 KeV is applied using the patterned oxide film 13 as a mask. 6 × 10 ¹⁵ cm
^The masking oxide film 13 is removed after ion implantation with a dose of ^-2 or more.

The implanted dopant is applied to the base layer 25.
Is implanted only in the extrinsic base region.

Referring to FIG. 3C, a metal silicide 26 which is a thin film for a base electrode is formed using an alloy compound source only on the external base region into which high-concentration ions have been implanted through the above process. The film is formed by sputtering.

For example, a hot-compressed composite target (hot-pre) of TiSi _2.x (x is a number from 0 to 9 below the decimal point)
Amorphous TiSi _2.x (x = 0 to 9) 26 is deposited using a sintered composite target.

That is, unlike the prior art by heat treatment, the base electrode thin film 26 for determining the base parasitic resistance is formed by sputtering deposition using a metal silicide having high conductivity to reduce the thickness thereof. 500 ~
It can be variously adjusted within the range of 4,000 angstroms.

Subsequently, a capping oxide film 14 having a thickness of about 500 Å is deposited on the base electrode thin film 26 by using LPCVD.

Referring to FIG. 4D, an oxide film 27 for emitter / base isolation is formed on the entire surface of the substrate for about 2000-4.
Then, the oxide film 27, the capping oxide film 14, the base electrode thin film 26, and the base layer are formed by using a predetermined photosensitive film as a mask so as to open the collector sinker 24 after being deposited to a thickness of 2,000 angstroms. 25 is patterned.

Then, a sidewall oxide film 28 is formed on the sidewall of the pattern portion.

Referring to FIG. 4E, a portion of the oxide film 27 for isolating the emitter / base is etched to define an emitter region.

Subsequently, as shown in FIG. 4F, dopant ions, for example, A
A 2000 angstrom thick polysilicon into which s ions are implanted is deposited by LPCVD from a temperature of 650 ° C. and then patterned to form an emitter layer 29.

At this time, the emitter layer 29 is formed as shown in FIG.
As shown in -1), a lower layer 29a made of single crystal silicon of 10 ¹⁸ cm ^-3 or less is ion-implanted at a high concentration for ohmic contact with an electrode by using a selective crystal thin film growth method. It can be grown on the upper layer 29b made of polycrystalline silicon containing the impurity concentration of 1 × 10 ²⁰ cm ⁻³ or more.

Referring to FIGS. 5G and 5H, a protective film 30 is formed on the entire surface of the substrate, contact holes are opened, and electrodes 31 are wired to complete the fabrication of the device. .

As described in the above embodiments, the present invention is merely illustrative, and those skilled in the technical field to which the present invention pertains without departing from the spirit and scope of the present invention. It will be appreciated that various variations and modifications are possible.

[0041]

As described above, according to the present invention, the conventional silicide process which involves a high-temperature heat treatment process for forming a metal silicide which is a thin film for a base electrode is eliminated, and the process is simplified. By providing a method of forming metallic silicide without loss of base thickness, productivity and parasitic resistance of the base can be reduced.

In addition, the thickness of the metallic silicide thin film is arbitrarily varied depending on the characteristics of the transistor, thereby exhibiting the effect of improving the operating characteristics of the device from a high frequency band.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a heterojunction bipolar transistor manufactured according to a conventional technique.

FIG. 2 is a cross-sectional view of a heterojunction bipolar transistor manufactured according to the present invention.

3A to 3C are process cross-sectional views illustrating respective steps (A) to (C) of a method for manufacturing the transistor of FIG. 2;

FIG. 4 is a process cross-sectional view showing each of steps (D) to (F) in the method for manufacturing the transistor of FIG. 2;

FIG. 5 is a process cross-sectional view showing each of steps (F-1) to (H) in the method for manufacturing the transistor in FIG. 2;

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Han Tae-hyun 161 Kejeong-dong, Yuseong-gu, Daejeon, Republic of Korea Inside the Electronic Communication Research Institute of Korea (72) Inventor Lee Shu- ▲ min ▼ 161 Dong Cave, Korea Electronic Communication Research Institute (72) Inventor Go-Gun 161 Kejeong-dong, Yuseong-gu, Daejeon, Republic of Korea In-house Korea Electronics Communication Research Institute (56) References JP-A-63-155664 (JP) JP-A-5-109751 (JP, A) JP-A-1-214161 (JP, A)

Claims (15)

(57) [Claims] 1. A method for manufacturing a bipolar transistor, comprising the steps of: a) forming a conductive buried collector by ion-implanting a high-concentration impurity into a silicon substrate; and forming a collector (22) above the buried collector (21). B) forming an oxide film 23 for device isolation and a collector sinker 24; b) growing a thin conductive base layer 25 over the entire surface of the substrate by using an epitaxial growth technique C) ion-implanting high-concentration impurities only in the extrinsic base region of the base (25) using a predetermined oxide film pattern (13) as a mask; Above the implanted extrinsic base region, a metal silicide (2
E) forming a capping oxide film (14) on the metallic silicide thin film (26) by a chemical vapor deposition method; f) forming an emitter / electrode on the entire surface of the substrate. After forming an oxide film (27) for isolating the base, the collector sinker (24)
The oxide film (27) and the capping oxide film (1) are formed by using a predetermined photosensitive film as a mask for opening.
4), base electrode thin film (26) and base layer (2)
5) patterning to form a side wall oxide film (28) on the side wall of the pattern portion; g) a part of the oxide film (27) is etched to form a conductive emitter layer (29) in a defined emitter region. And h) forming a protective film (30), opening a contact hole, and then forming a metal wiring step of forming an electrode (31). 2. The heterojunction bipolar transistor according to claim 1, wherein in the step (e), the capping oxide film is formed to a thickness of about 500 Å.
A method for manufacturing a transistor. 3. An oxide film (2) in the step (f).
3. The method for manufacturing a heterojunction bipolar transistor according to claim 2, wherein said step (7) is formed to a thickness of about 2000 to 4000 angstroms. 4. The conductive base (25) of the step (b).
2. The method for manufacturing a heterojunction bipolar transistor according to claim 1, wherein said material is made of a single single-crystal SiGe having a high impurity concentration of 1 × 10 ¹⁸ cm ⁻³ or more. 5. The conductive base (25) of the step (b).
2. The method for manufacturing a heterojunction bipolar transistor according to claim 1, wherein said material has a multilayer structure of SiGe / Si or Si / SiGe / Si. 6. The method as claimed in claim 1, wherein the germanium (Ge) content distribution in the SiGe base (25) is changed linearly. 7. The method for manufacturing a heterojunction bipolar transistor according to claim 6, wherein the Ge content distribution in the SiGe base (25) is constantly changed to 30% or less. 8. The heterojunction bipolar transistor according to claim 6, wherein the Ge content distribution in the SiGe base (25) is linearly changed from 30% to 0% from the bottom to the top. Production method. 9. The Ge content distribution in the SiGe base (25) is changed from 30% or less from a lower portion to an upper portion to a certain portion, and then linearly changed to 0% again. The method for manufacturing a heterojunction bipolar transistor according to claim 6. 10. Ge in said SiGe base (25).
The content distribution of germanium (Ge) is changed by linearly increasing the content distribution from 0% to 30% or less and then linearly decreasing the content distribution from 30% or less to 0% again. Item 7. A method for manufacturing a heterojunction bipolar transistor according to Item 6. 11. The method for manufacturing a heterojunction bipolar transistor according to claim 1, wherein the conditions of the ion implantation in the step (c) are an energy of 30 KeV and a dose of 6 × 10 ¹⁵ cm ⁻² or more. 12. The metallic silicide (2) of the step (d).
6) TiSi as sputtering conditions for formation
_2.x hot-pressed composite (x is a number after the decimal point)
2. The method for manufacturing a heterojunction bipolar transistor according to claim 1, wherein a target is used. 13. The composition ratio of TiSi _2.x , x = 0 to
13. The method for manufacturing a heterojunction bipolar transistor according to claim 12, wherein the thickness of the film is in the range of 500 to 4,000 angstroms. 14. The conductive emitter layer (29) of the step (g) is formed by low pressure chemical vapor deposition (LPCVD) of 2000 Å thick polysilicon into which dopant ions of a predetermined conductivity type are implanted. The method for manufacturing a heterojunction bipolar transistor according to claim 3, wherein the bipolar transistor is formed. 15. The method according to claim 15, wherein the conductive emitter layer (29) in the step (g) is selectively formed by a crystal thin film growth method (selective).
v epitaxy growth)
Single crystal silicon (29a) containing an impurity concentration of ¹⁸ cm ^-3 or less and 1 × 10 ²⁰ c ion-implanted at a high concentration
polycrystalline silicon containing an impurity concentration of m ^-3 or more (29
2. The method according to claim 1, wherein b) is grown as a stacked structure.