JP2664204B2 - Wiring method between MOS transistors - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a wiring method between terminals of a transistor.

[Conventional technology]

Conventionally, a wiring method in a cell in which a distance between a power supply line and a ground line of the cell is fixed is discussed in IPSJ Design Automation Study Group Material 22-4 (1984), pp. 1-9. I have.

[Problems to be solved by the invention]

In the above prior art, in the wiring using the feedthrough, at the stage of the MOS transistor arrangement processing, the passing position and the number of the feedthrough are estimated and secured in advance, and only the feedthrough is used in the wiring processing between the MOS transistors. . For this reason, there is a problem that wiring that cannot be completed due to insufficient feedthrough occurs, even if the wiring is largely detoured, an unused feedthrough is searched and selected, and an unused feedthrough remains and the cell area increases. Atsuta.

An object of the present invention is to solve the above-described problem by considering the generation of feedthrough in wiring processing between MOS transistors instead of the processing of arranging MOS transistors, and selecting a wiring selection criterion and a feedthrough to be performed in each wiring region. An object of the present invention is to provide a wiring method between MOS transistors, which sets a reference to be generated and minimizes an area of a used wiring region in a cell.

[Means for solving the problem]

The problems concerning the feedthrough described above are as follows: (a) the given net is divided into nets to be wired in the upper and lower rows of channels and nets to be wired in the other channels, and (b) the given nets are to be wired in the upper and lower rows of the channels. 1 net to be wired
(C) With respect to the nets to be wired in the other channels in (a), the channels to which these are to be wired are determined according to the following criteria. Nets that connect only the gate terminals are routed in the upper channel, nets that connect only the gate terminals of the lower transistors are wired in the lower channel, and nets other than, are created as feedthroughs in the upper or lower channel. (D) For each net belonging to (c), create a feedthrough at the following two selectable positions (i) and (ii) according to the criteria of (iii); (i) A diffusion layer is separated because adjacent diffusion terminals of adjacent transistors have different potentials, and a position through which a feedthrough can pass through this gap; and (ii) an adjacent transistor The diffusion layer is shared because the adjacent diffusion terminals of the transistor are at the same potential, and the shared diffusion layer is separated to secure a position through which the feedthrough is passed. (Iii) The diffusion layer of (ii) is separated This is achieved by minimizing the sum of the increase in the horizontal length of the wiring area and the increase in the wiring length due to the feedthrough creation, and the increase in the number of horizontal wirings on each x coordinate for that purpose. Is done.

[Action]

Nets that connect only the gate terminal of the upper transistor are wired in the upper channel, nets that connect only the gate terminal of the lower transistor are wired in the lower channel, and other nets are fed through to create the top or Wire in the lower channel. As a result, the number of wirings requiring feedthrough can be minimized. Furthermore, in determining the feedthrough passage position, all gaps separated by the diffusion layer and all positions connected to the diffusion layer are considered as candidates, and the lateral length of the wiring area is increased by separating the diffusion layer. In addition, the sum of the wiring length, which is increased for creating the feedthrough, and the number of horizontal wirings on each x coordinate, which is also increased for that purpose, is minimized. Thereby, the increase in the area of the wiring region can be minimized.

〔Example〕

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 3 shows a layout model of a cell targeted in this embodiment. 1 is an outer frame of the cell, and 2 is a terminal (referred to as an external terminal) for connecting a signal line from outside the cell. Here, the cell is a functionally integrated unit, and is the minimum unit of the chip mounting design. Inside the cell, MOS transistors are arranged in two rows (these are referred to as element rows).
Wire between the gate, source, drain and external terminals of the MOS transistor. Here, 8 is a gate, 9 and 10 are diffusion layers, each of which is a source or a drain. These 8,
9 and 10 form one MOS transistor. here,
When adjacent diffusion layers of adjacent MOS transistors have different potentials, diffusion layers 10 and 14 are arranged separately. When these are at the same potential, MOS transistors are arranged sharing the diffusion layer 15 to reduce the cell area. In the wiring between the MOS transistors, after the position of the MOS transistor is determined, wiring is performed between the gate 8, the diffusion terminal 16, and the external terminal 2 using the two layers of the first aluminum layer 12 and the polysilicon layer 11. Here fixed wiring
17 and 18 are a ground line and a power supply line, respectively. In the present embodiment, it is assumed that the distance between these wirings is fixed. This is because, when the cells are arranged adjacent to each other, the power supply line and the ground line can be wired in a straight line between the cells. There are five wiring areas. The wiring regions 4 and 6 on the element row, the wiring area 5 sandwiched between the two element rows, and the upper and lower wiring areas of each element row are 3 and 7, respectively. Wiring areas 4 and 6
Is fixed in the vertical direction, that of the wiring regions 3 and 7 is variable, and is determined at the end of wiring. In the wiring regions 4 and 6, the first aluminum
Only the wiring layers can be used. This is because if a polysilicon layer is present on the diffusion layer, a MOS transistor is always generated there. Therefore, the feedthrough using the polysilicon layer must pass through a position without the diffusion layer. One is a position 13 where the diffusion layer is separated in advance, as shown in FIG. 4, and there is no change in the area of the cell even when the cell passes through the feedthrough 19. The other is the position 20 where the diffusion layer is connected as shown in FIG.
Is newly separated and passed through the feedthrough 19, and at this time, the lateral length of the cell increases by one lattice. Here, the wiring 12 is needed to connect the newly separated diffusion layers. In the embodiment described below, the feedthrough passable position is limited to the two cases shown in FIGS. 4 and 5, and the feedthrough pass position is determined so as to reduce the cell area.

FIGS. 9 and 10 show flowcharts of the processing of the conventional method and the present method. In the conventional method, after the relative wiring of the MOS transistors is determined 53, the number and the position thereof are estimated, and a feedthrough is inserted between the MOS transistors before the wiring processing 54. Next, in the wiring processing, nets are extracted 55, the wiring order is determined 56, and wiring routes are determined one by one net.
At this time, when there is a net that requires a feedthrough, the feedthrough inserted in advance is selected in a first-come-first-served order and the wiring route is determined 57,58. The above processing is performed based on the wiring grid. In the subsequent mask pattern generation processing, the result of the arrangement and wiring up to that time is converted into a mask pattern59. In this method, no feedthrough is inserted in the placement processing, and a feedthrough is generated in the wiring processing. After the nets are extracted, each net is sorted into channels 60, and the one-layer wiring in the on-column channels is completed 61.
Next, if feed-through is necessary for the remaining nets, all feed-throughs are generated at the same time instead of one by one, and wiring is performed in the inter-channel channel and in the upper and lower channels 63, 64 . The positioning of the mask pattern generation processing is the same as the conventional method65.

FIG. 2 shows the wiring requirements. Here, 5 wiring requirements, 2
Consider wiring 2,23,24,25,26. Here, the wiring request refers to a terminal from one terminal to another terminal. Therefore, there is a possibility that a plurality of wiring requests can be made in one net. First, the wiring request 24 to be closed on the element row is wired by the lower row upper channel. Figure 27. Wiring request 23 is assigned to the upper channel, 28 in FIG. With remaining wiring requirements 22
26 cannot be wired without using feedthrough. A feedthrough is assigned to these wiring requests to complete the wiring. The wiring request 25 can be wired as it is, 70 in FIG.

The feedthrough position determination method will be described. Wiring requirements 22 and 26 in FIG. 2 are designated as vertices 30 and 29 in FIG. 7 as necessary feedthrough positions. The cell of this embodiment is examined to extract feedthrough candidate positions 35 to 38 (FIG. 6). These are represented by vertices 31 to 34 in FIG. 7, respectively. Next, feedthrough candidate positions from which a certain feedthrough required position can be selected are represented by sides 39 to 43 in the graph of FIG. Here, the selectability means whether or not the wiring can be routed in the inter-column channel 5 without shorting. In FIG. 8, the necessary feedthrough position 30 is the feedthrough candidate position 35.
Is selected, and when feedthrough is generated, a short path (49) with the wiring path 70 in the inter-channel channel 5 is shown.
Therefore, no edge exists between vertices 30 and 31 in the graph of FIG. Next, an evaluation value is given to each side of FIG. According to the evaluation value calculation method of the present invention, these values correspond to an increase in the horizontal length of the cell due to the selection of the feedthrough position (the horizontal length increases by one pitch in FIG. 5) and an increase in the wiring length (FIG. 8, FIG.
The sum of the length of the wiring 52 and the wiring length of the portion 53) and the increase in congestion (for example, the number of wirings in the horizontal direction overlapping portions of the wirings 50 and 51 in FIG. 2, 2 tracks) are calculated as weighted sums. . After that, the seventh is set so that the sum of the evaluation values 44 to 48 is optimal.
Vertex 29 and vertex 31 out of edges 39 to 43 of the graph shown in the figure
32 and the vertex 30 and any of the vertices 32 to 34 may be selected without duplication. By solving this problem, for example, feedthrough candidate positions 37 and 36 are assigned to the necessary feedthrough positions 22 and 26 in FIG. 6, respectively, and the wiring paths 50 and 55 including the feedthroughs 54 and 55 in FIG.
52 is obtained. In the short wiring problem, the number of feedthrough candidate positions (the number of lower vertices in FIG. 7) is always larger than the number of necessary feedthrough positions (the number of upper vertices in FIG. 7).

〔The invention's effect〕

As is clear from the above description, according to the present invention, in the wiring between the MOS transistors in the cell in which the distance between the power supply line and the ground line is fixed, it is possible to prevent the wiring from becoming impossible due to insufficient feedthrough. It is possible to determine a feed-through equivalent to or better than that of a human by eliminating a large detour and selecting an unused feed-through and generating necessary and sufficient feed-through. The effect of the present invention on cell area reduction was about 25, 32, and 23% for the cell composed of 30, 68, and 100 transistors, respectively, compared to the conventional method.

The present invention described above has an effect of reducing the chip area and the chip design / manufacturing cost. This leads to high-performance complete automation of cell layout pattern generation, and also to a significant reduction in the man-hours for layout design of LSI chips.

[Brief description of the drawings]

FIG. 1 is a diagram showing one embodiment of the present invention, and shows the result of two wires generating a feedthrough and being wired. FIG. 2 shows a wiring request used in the present embodiment.
The figure shows a layout model of a CMOS logic cell.
FIG. 6 shows a feedthrough candidate position.
The wiring pattern immediately after the completion of the layer wiring is shown. FIG. 7 is a diagram showing a feed-through assignment problem using a graph. FIG. 8 shows an unrealizable feedthrough assignment. FIG. 9 and FIG. 10 are flow charts of the conventional method and the method of the present invention showing wiring processing in consideration of feedthrough. 1 ... cell frame, 2 ... external terminal, 3 ... upper channel,
4 ... upper row upper channel, 5 ... row row channel, 6 ... lower row upper channel, 7 ... lower channel, 8 ... gate, 9,
10 ... diffusion layer, 11 ... polysilicon layer, 12 ... aluminum first layer, 13, 20 ... candidate feedthrough position, 14, 15 ... diffusion layer, 16 ... diffusion terminal, 17 ... ground wire, 18 ... Power line.

Continuing from the front page (72) Inventor Kazuyuki Fukuda 1448 Kamimizu Honcho, Kodaira-shi, Tokyo Within Hitachi Ultra LSE Engineering Co., Ltd. (56) References JP-A-62-266850 (JP, A) JP-A-60-66447 (JP, A) JP-A-62-273751 (JP, A)

Claims (1)

(57) [Claims] 1. A plurality of MOS transistors each comprising a gate terminal and a diffusion terminal are arranged side by side in the horizontal direction to form at least two MOS transistor rows, and a first wiring region is formed on the MOS transistor rows. Then, a second wiring region sandwiched between the MOS transistor trains is formed, and a third wiring region is formed outside the MOS transistor trains. By connecting the terminals of the MOS transistors which cannot be connected only by the horizontal wirings in the first and third wiring regions by using the horizontal wirings and the vertical wirings traversing the MOS transistor row, MOS above
In a wiring method for wiring between terminals of a transistor, a diffusion layer of the MOS transistor has a different diffusion layer because a potential of a diffusion terminal of the adjacent MOS transistor is different as a position where a vertical wiring crossing the MOS transistor row passes. The position separated in advance and the position where the diffusion layer shared by the diffusion terminals shared by the adjacent MOS transistors and having the same potential to pass the vertical wiring must be separated because the potentials of the diffusion terminals of the adjacent MOS transistors are the same are extracted. Increasing the horizontal length of the first to third wiring regions when wiring is performed at all of the extracted positions, and increasing the horizontal wiring length of the second and third wiring regions; And the sum of the increasing number of horizontal wirings overlapping in the third wiring area is determined, a position where the sum is minimized is selected, and the vertical wiring is arranged at the selected position. Wiring between MOS transistors, characterized in that the interconnection between the MOS transistors with vertical wires which are location can not be combined in only the horizontal direction wirings.