JP2659941B2 - Semiconductor integrated circuit - Google Patents

Description

The present invention relates to a semiconductor integrated circuit, and more particularly to a high-voltage limiter circuit of a nonvolatile memory (EEPROM) capable of electrically writing and erasing.

(Prior art) Conventionally, in an EEPROM, a high electric field is applied to a thin oxide film between a floating gate and a drain of a memory cell to tunnel electrons, thereby changing a charge amount of the floating gate, and changing its “threshold value”. To realize non-volatile storage. Therefore, a high voltage (usually 20V) is required.

Recently, a 5V power supply voltage was applied from the outside, and a high voltage was generated by a booster circuit inside the chip. Therefore, the "threshold" of the memory cell was kept constant, and junction breakdown and oxide film breakdown were caused. Therefore, a limiter circuit for keeping the boosted potential constant is required. FIG. 2 shows a conventional example of connection between an internal booster circuit and a limiter circuit.

The limiter circuit has a transistor Su as shown in FIG.
Some use rface breakdown voltage. This is intended to limit the boosted potential by the Surface breakdown voltage by inputting the boosted potential to the n ⁺ region (32) on the P-type substrate (31) and setting the Polysi gate (33) to the ground potential. is there. However, in this structure, holes are trapped in the gate oxide film (34) after breakdown, and Walk
There is a disadvantage that the limiter potential changes due to out. Further, when the thickness of the gate oxide film varies, the limiter potential also changes, so that a stable boosted potential cannot be supplied. Another method uses a junction breakdown voltage shown in FIG. 4 for the limiter circuit.

This consists of an n ⁺ layer (42) and a p ^- layer (43) on a P-type substrate (41).
P By forming the ^- to optimize the concentration of the layer, n ⁺ layer and p ^-
The junction breakdown voltage of the layer is set to about 20 V, and the limiter potential is made to be constant. However, in this case, if the junction withstand voltage is set to 20 V as shown in FIG. 5, the amount of change in the junction withstand voltage is large with respect to the change in the heat process and the change in the p ^- concentration. There is a drawback that it is difficult. According to this, the p ^- concentration is 2.5 × 10 ¹⁶ cm ^-3
Withstand voltage from 30V to 40V just by changing from 1.5 × 10 ¹⁶ cm ^-3
And 10V also changes. Figure 5 shows the literature of SMSZE et al. (Appl.Phy
s. Lett., 8.111 (1966)).

(Problems to be Solved by the Invention) In view of the above drawbacks, the present invention provides a limiter circuit which is stable and has a large process margin and aims to supply a stable boosted potential.

[Configuration of the invention]

(Means for Solving the Problem) FIG. 1A shows a limiter circuit of the present invention. First, second, and third N-well layers (12, 13, and 13) are formed on a P-type semiconductor substrate (11).
14), forming p ⁺ layers (15, 16, 17) on each,
An n ⁺ layer (18, 19, 20) and an n ⁺ layer (21, 22, 23) for applying a potential to the N-well layer are formed in each p ⁺ layer, and a first N-well ( 12) Connect the n ⁺ layer (21,18) in the high voltage input terminal (2
4), the first p ⁺ layer (15) and the n ⁺ layer (19, 22) in the second N-well (13) are connected (25), and the second p ⁺ layer (16) is connected to the second p ⁺ layer (16). Connect the n ⁺ layer (20, 23) in the third N-well (14) (26)
Then, by setting the third p ⁺ layer (17) to the ground potential (27), a limiter circuit is formed.

(Operation) The operation will be described with reference to FIG. N-well layer (12, 13, 14), p ⁺ layer (15, 16, 17), n ⁺ layer (18, 19, 20, 21, ² )
2, 23) are formed in the same step, and therefore have the same concentration. Junction breakdown voltage is determined by the n ⁺ layer of p ⁺ layer and p ⁺ layer in, it is set so that each junction breakdown voltage is about 7V. As shown in Fig. 5, the junction breakdown voltage is 7V
In the case of FIG. 4, the variation in the junction breakdown voltage with respect to the change due to the heat process and the dose due to the ion implantation is 20 V in FIG.
It can be seen that it is much smaller and more stable than the variation due to the junction withstand voltage.

In addition, since the potential of the N-well and the potential of the n ⁺ layer are the same, there is no problem even if the n ⁺ and the N-well in the p ⁺ layer perform punch-through. Also, since the potentials are the same, there is no problem even if a bipolar transistor is formed.

Since the junction breakdown voltage per one is 7V, since these are connected in series in three stages, the limiter voltage is 7V × 3 = 21V
Becomes Therefore, when the boosted potential exceeds 21V, the DC path flows from the input terminal (24) to the ground potential (27), and the boosted potential is liwitted to 21V.

FIG. 1 (b) is a circuit diagram showing the connection between the limiter circuit and the booster circuit of FIG. 1 (a).

Embodiment An embodiment of the present invention will be described in detail with reference to FIG.

Phosphorus on N-well region (62) on 20Ω P-type substrate (61)
Ion implantation is performed at 150 KeV 7.9 × 10 ¹² cm ⁻² , and annealing is performed at 1190 ° C. for 200 minutes to form an N-well layer. Next, field oxidation is performed to perform element isolation (FIG. 2A). Next, boron ions are implanted into the p ⁺ region at 40 KeV2 × 10 ¹³ cm ⁻² , and further into the n ⁺ region at 40 KeV 5 × 10 ¹⁵ cm ^−2. Then, arsenic is ion-implanted, and annealing is performed at 900 ° C. for 37 minutes. This forms ap ⁺ layer (63) and an n ⁺ layer (64) (FIG. 2b). Further, an interlayer insulating film is deposited, and a contact hole is opened to form an Al layer (65) (FIG. 2). c) The final concentration of each is 3 × 10 ^{16 in the} N-well layer (62).
cm ^-3 p ⁺ layer (63) 2 × 10 ¹⁷ cm ^-3 , n ⁺ layer (64) 2 × 10 ²⁰ cm ^-3
It is. At this time, the junction withstand voltage of the p ⁺ layer (63) and the n ⁺ layer (64) is 7V. The output of the booster circuit is connected to the input Al layer (66), and the final p ⁺ potential is set to the ground potential by the Al layer (67).

Although Si was used as the substrate, the same applies to other materials such as Ge, GaAs, and GaP.

〔The invention's effect〕

With the limiter circuit of the present invention, a stable boosted potential having a margin in the process can be supplied.

[Brief description of the drawings]

1 (a) is a sectional view of a limiter circuit of the present invention, FIG. 1 (b) is a connection diagram of a booster circuit and a limiter circuit, FIG. 2 is a process sectional view of an embodiment of the present invention, FIG. 4 is a cross-sectional view of a conventional limiter circuit, and FIG. 5 is a junction breakdown.
FIG. 4 is a diagram illustrating a relationship between voltage and concentration. In the figure, 1-1 ... P-type substrate, 1-2,1-3,1-4 ... N-well,
1-5,1-6,1-7 ... p ⁺ layer, 1-8,1-9,1-10 ... n ⁺ layer in p ⁺ layer, 1-11,1-12,1-13 ... N ⁺ layer giving N-well potential, 1-14, 1-15, 1-16 ... Al wiring, 3-1 ... P
Mold substrate, 3-2 ... n ⁺ layer, 3-3 ... Polysi Gate, 3
_{-4 ...... Gate SiO 2, 4-1 ......} P -type substrate, 4-2 ...... n
⁺ Layer, 4-3 ... p ^- layer, 6-1 ... P-type substrate, 6-2 ...
... N-well layer, 6-3 ...... p ⁺ layer, 6-4 ...... n ⁺ layer, 6-
5 ... Al wiring, 6-6 ... Boost potential input section, 6-7 ...
Ground potential.

Claims (1)

(57) [Claims] A first conductivity type well is formed in a first conductivity type semiconductor substrate, a first conductivity type layer is formed in the well, and a first first conductivity type layer is formed in the first conductivity type layer. A second conductivity type layer is formed, a second second conductivity type layer is formed in the well outside the first conductivity type layer at a predetermined distance, and the first and second second conductivity type layers are formed. The mold layer is used as a high-voltage input terminal, and the first conductivity type layer is used as an output terminal.
A semiconductor integrated circuit, wherein the structure is connected in multiple stages in series by connecting the output terminal to the input terminals of the first and second second conductivity type layers at the next stage.