JP2652413B2 - Motion detection circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a motion detection circuit used in a high-definition television and a high-definition television using a frame memory.

(Prior Art) In recent years, with the enlargement of television receivers, high image quality technology has been introduced. Among them, the motion detection circuit
Many circuits have been proposed that determine the motion and play a large role in improving the image.

As a conventional technique, there is a technique in which a change amount between frames of each pixel is used as a motion signal, as shown in the proceedings S3-2 of the 1986 National Convention of the Institute of Television Engineers of Japan.

FIG. 7 shows a conventional motion detection circuit. Seventh
In the figure, 71 is a frame memory, 72 is a subtractor, and 73 is a core circuit.

Next, the operation of the conventional example will be described. Component signal C ₁ is input to the frame memory 71. Current component signal C ₁ and the one-frame delayed component signals
C ₂ is subtracted by the subtracter 72, the output C ₃ of the subtracter 72 is inputted to the core circuit 73, to prevent malfunction is output as a motion detection signal C _4.

(Problems to be Solved by the Invention) However, in the above-described conventional method, only the motion at each pixel is detected, so that a good image quality can be improved in a complete still image, but humans confirm the same resolution as the still image. There has been a problem that it is not possible to cope with a moving image to the extent possible and a sufficient image quality improvement effect cannot be obtained.

The present invention solves such a conventional problem. In order to perform the same processing as a still image on a moving image that moves slowly with respect to a component signal, a motion that focuses on the characteristics of the image is performed. A detection circuit is provided.

Means for Solving the Problems In order to achieve the above object, the present invention provides a motion detection circuit comprising: a frame memory circuit; a spectrum conversion circuit for converting an image signal from a time axis signal to a spectrum signal; It is provided with a delay circuit for producing a signal and a core circuit.

(Operation) Therefore, according to the present invention, in order to estimate the position one field before the pixel of interest at present, the spectra of the surrounding pixels including each of them are collated in the pattern matching area, If there is, a signal indicating a location where the spectrum pattern matches is output. In addition, when an appropriate pixel does not exist in the matching area because the movement and change of the pixel are so severe, that is, when the signal indicating the matching of the pattern matching circuit exceeds the threshold value of the core circuit, the output of the pattern matching circuit indicates a moving image. Output the code.

FIG. 1 is a block diagram of a motion detection circuit according to an embodiment of the present invention. In FIG. 1, 1 and 2 are field memories for delaying one field that is not input, 3 and 4 are spectrum conversion circuits, 5 is a pattern matching circuit, 6 is a core circuit, 7 is a multiplexer, and 8 is a setting switch.

FIG. 2 shows a partially detailed block composed of the spectrum conversion circuits 3 and 4 and the pattern matching circuit 5 in FIG. In FIG. 2, 21 to 27 are absolute value output subtraction circuits, 31 to 37 are adders, 38 is a minimum value part detection circuit, and 41 to 48 are Fast Fourier Transforms (Fast Fou
(Transformer) circuit (hereinafter, referred to as an FFT operation circuit).

FIG. 3 is a diagram showing an example of signals used in the pattern matching circuit of one embodiment of the present invention, and FIG. 4 is an output characteristic diagram of a core circuit of one embodiment of the present invention.

Next, the operation of the above embodiment will be described with reference to FIGS. The input signal a ₁ is input to the field memory 1 and is delayed by one field, and is delayed by one field.
a ₂ and a pattern matching circuit for a current signal group a ₃₁ ~a ₃₇ (a ₃₎
Is output. The one-field delay signal a ₂ is input to the field memory 2 and the pattern matching reference signal a ₄
Is output. The current signal group for pattern matching a ₃₁
Aa ₃₇ (a ₃ ) and the reference signal a ₄ for pattern matching are input to the spectrum conversion circuits 3 and 4, respectively, and output the spectrum signals a ₆ and a _{51 to} a ₅₇ (a ₅ ) of the input signal. The spectrum conversion circuit is, for example, the FFT operation circuits 41 to 48 shown in FIG.

Assuming that the image is a two-dimensional signal g (x, y), an area M pixels ×
The frequency spectrum at N pixels is Becomes Where Ω ₁ = 2x / MX ₀ , Ω ₂ = 2x / NY ₀ , w ₁ = e
^{−2πj / M} , w ₂ = e ^{−2πj / N} X ₀ , Y ₀ is a horizontal and vertical sampling interval 0 ≦ k ≦ M, 0 ≦ l ≦ N Assuming a 4 × 4 region, 16 spectra Occurs. For the sake of simplicity, in the present invention, a pattern matching operation in the horizontal direction when N = 4 and M = 1 will be described. Now, when the signals d _{0 to} d ₃ (a ₄ ) shown in FIG. ₃ are input to the spectrum conversion circuit 3, the frequency spectrum a ₆ of the input signal is output to the spectrum conversion circuit 3. If the signals one field before the signals d _{0 to} d ₃ are signals d ₁₃ to d ₁₆ and the pattern matching area is ± 3 pixels in the horizontal direction, the pattern matching reference signals are seven sets a _{31 to} a ₃₇ , respectively. FFT operation circuits 41 to 4
After being input to 7 and output as frequency spectrums a _{51 to} a ₅₇ , the current signal frequency spectrum a ₆ for pattern matching and the absolute value output subtraction circuits 21 to 27 are input to the corresponding spectrum subtraction circuits 21 to 27, respectively. Output as b _{21 to} b ₂₇ . In this case, for example, b ₂₁ is composed of four data signal b ₃₁ which is a measure of pattern matching by adding in all adder 31 data b ₂₁ is output. This operation is also adder 32-37 for the signal b ₂₂ ~b _27, the cord 9 and the minimum value becomes the determination value represents the minimum value becomes the signal portion in these sum output b ₃₁ ~b ₃₇ Output as a ₇ .

In an actual signal, an image may move beyond the pattern matching area. In this case, it must be determined that a pattern match cannot be obtained. A core circuit is provided to realize this processing. Figure 4 shows the characteristics of the core processing.
Shown in the figure. If the input value a ₇ core circuit 6 is smaller than the threshold Th, it is determined that there are pixels of interest in the pattern matching both the region, the output signal a ₈ is "0" next to the core circuit 6, the output of the multiplexer 7 _a10 signal a ₉ is designated. Also, when the input value a ₇ equal to or greater than the threshold value Th, it is determined that there is no pixel to pattern matching both the region of interest, the output signal a ₈ core circuit 6 configured as an output of "1", the multiplexer 7 code a ₁₁ representative of the "dynamic" has been set in the switch 8 is designated.

As described above, according to the present embodiment, the feature of an image is represented by a frequency spectrum and pattern matching processing is performed. A signal that causes the scan conversion circuit to perform the same processing as that described above can be output.

As described above, the matching pattern is 4 × 1 for simplicity of description, but the size is variable.

FIG. 5 shows another embodiment of the pattern matching circuit of the present invention. As shown in FIG. 5, the pattern matching circuit 5 includes touches 51 to 57 with a clear function, and a read-only memory (hereinafter, referred to as ROM) 60 can be used to change an adding section and change a spectrum to be added.

FIG. 6 is a detailed block diagram of the FFT operation circuits 41 and 48, the absolute value output subtraction circuit 21, the latch 51 with a clear function, the adder 31, and the ROM 60 in FIG.

Table 1 is an example of the output e ₂ to e ₅ to the input e ₁ of the ROM 60.

In the case of e ₁ = 0, in FIG. 6, the outputs b _{211 to} b ₂₁₄ (b ₂₁ ) of the absolute value output subtraction circuit 21 inputted to the latches 511 to 514 (51) with a clear function all pass through the rat and are added to the adder. Entered in 31. When e ₁ = 1, only the signal b ₂₁₄ is not output by the latch 514 with the clear function, and the adder 31 outputs the signal b _{214
221 to} b _{223 are} added. This processing is similarly performed in other blocks in FIG.

(Effect of the Invention) As is clear from the above embodiment, the present invention provides a spectrum conversion circuit for converting a time axis signal into a frequency spectrum,
By using the pattern matching circuit and the core circuit for motion detection, it is possible to output a signal for performing the same processing as a still image on a moving image that moves slowly.
By using M and a latch with a clear function, there is an effect that a plurality of types of pattern matching processing can be performed.

[Brief description of the drawings]

FIG. 1 is a block diagram of a motion detection circuit according to one embodiment of the present invention,
FIG. 2 is a detailed block diagram including the spectrum conversion circuit and the pattern matching circuit in FIG. 1, FIG. 3 is an example of a signal used in the pattern matching circuit of one embodiment of the present invention, and FIG. FIG. 5 is a block diagram of a pattern matching circuit according to another embodiment of the present invention;
FIG. 6 is a partial detailed view of FIG. 5, and FIG. 7 is a block diagram of a conventional motion detection circuit. 1,2 ... field memory, 3,4 ... spectral conversion circuit, 5 ... pattern matching circuit, 6,73 ... core circuit, 7 ... multiplexer, 21-27 ... absolute value output subtraction circuit, 31- 37 …… Adder, 38 …… Minimum value part detection circuit,
41 to 48: FFT operation circuit, 51 to 57, 511 to 514: Latch with clear function, 60: ROM, 71: Frame memory, 72
...... Subtractor.

Claims (3)

(57) [Claims] 1. A field memory for storing at least two fields of a digital component television signal, a spectrum conversion circuit for performing spectrum conversion of a current signal group and a reference signal group limited to an arbitrary area, and the spectrum conversion circuit. A pattern matching circuit that inputs a current signal group and a reference signal group that have been spectrally transformed by the above and outputs a factor indicating that a candidate of a reference signal group that matches the current signal group matches a signal representing that part, and the pattern matching circuit. A core circuit that outputs a control signal that selects a signal of a pattern matching circuit or a signal by a setting switch as an output of the motion detection circuit as an input of a match determination factor of
A setting switch for setting a signal different from the output of the pattern matching circuit, and a multiplexer for inputting the output of the core circuit and selecting whether the output of the motion detection circuit is an output of the pattern matching circuit or a signal from the setting switch. A motion detection circuit characterized in that: 2. A fast Fourier transform operation circuit is used as a spectrum conversion circuit, and a difference between a signal corresponding to a current signal and a signal corresponding to a reference signal group is obtained as a means of a pattern matching circuit, an absolute value is output, and the respective outputs are added. 3. The motion according to claim 1, further comprising: outputting a signal representing a part of the reference signal group that provides the minimum value by comparing the addition outputs and a minimum value of the addition output as a coincidence determination factor. Detection circuit. 3. A pattern matching circuit, comprising: a latch having a clear function provided between a subtractor circuit for outputting an absolute value and an adder; and a read controlling the output of the latch with a clear function by an output pattern changeable by an input signal. The motion detection circuit according to claim 2, further comprising a dedicated memory (ROM).