JP2648528B2 - LSI design method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION (Industrial application field) The present invention relates to an LSI design method for determining a layout by using information at the time of design for LSI testability.

(Prior Art) FIG. 5 shows a method of designing an LSI for determining a layout by using information at the time of a conventional design for testability of an LSI. This is the step of obtaining information. Step 502 is a step in which a test input is generated for the stuck-at fault of the logic-level circuit obtained in step 501, and information that replaces a register that hinders the fault detection rate with a scan register is obtained. Step 503 is to manually replace the register determined to replace the circuit designed in step 501 with the scan register by using the information obtained in step 502 to the scan register, and at the same time, the number of scan chains and the number of scan registers connected to the scan chain. This is a step of manually determining the order. Step 504 is a step of manually determining a layout based on the corrected circuit connection information in step 503.

(Problems to be Solved by the Invention) However, in the above-described conventional LSI design method, after a test input is generated, a register determined to be manually replaced with a scan register is replaced with a scan register, and the number of scan chains is determined. After deciding the order of the scan registers connected to the scan chain, inserting the scan chain, and correcting the LSI circuit diagram, the layout must be determined. There is a problem that the scan chain cannot be automatically inserted, and the development period of the LSI design becomes longer.

In addition, when the circuit is hierarchically designed and there are a plurality of the same functional blocks, if a register of a certain block is replaced with a scan register, the layout information must have a plurality of layout information. Cannot be processed at high speed.

Furthermore, since the layout is performed after manually inserting the scan register and the scan chain into the circuit diagram, an optimal scan chain may not be obtained in the layout, and the actual area may increase and the scanning operation may be slow. Have.

The present invention has been made in view of the above points, and an object of the present invention is to independently use register information to be replaced with a scan register obtained as a result of test input generation and hierarchical circuit connection information at the time of layout. It is possible to automatically insert scan registers and scan chains, and to save large amounts of memory by reducing the amount of storage because it has data of a plurality of identical functional blocks as data of one functional block. By optimally determining the number of scan chains and the order of scan registers connected to the scan chains, the circuit area can be reduced and the scan operation can be performed at high speed.After the scan registers and scan chains are inserted, circuit connection information and scan Change the test input as if a scan register and scan chain were inserted. By, scan register,
Logic for circuit connection information after scan chain insertion,
An object of the present invention is to provide an LSI design method for enabling execution of a fault simulation.

(Means for Solving the Problems) In order to achieve the above object, a solution means specifically taken by the invention of claim 1 is directed to an LSI design method,
Circuit connection information, and scan register information indicating that it has been determined that a specific register in a circuit obtained by expanding the circuit connection information at the gate level is determined to be replaced with a scan register. And the scan register information is used to determine a scan chain.

Specifically, according to the invention of claim (2), in the configuration of claim (1), the scan register information scans a specific register in a circuit developed at a gate level when a test input of an LSI design is generated. A configuration is added in which the information is determined to be replaced with a register.

Specifically, in the invention of claim (3), in the configuration of claim (1), the circuit connection information includes connection information between functional blocks in each layer of the LSI for which a hierarchical circuit is designed, Hierarchical circuit connection information composed of gate level connection information, and determines the layout of functional blocks and scan chains by using the hierarchical circuit connection information and the scan register information when laying out an LSI design. The configuration is added.

Further, in order to achieve the above object, a solution specifically taken by the invention of claim (4) is directed to an LSI design method, and when it is determined that a specific register in a circuit is replaced with a scan register, A test input pattern generating step of recognizing the specific register determined to be replaced with a scan register as a scan register, and generating a scan test input pattern for reading and writing the internal state of the specific register by scan-in and scan-out; And a scan chain determining step of determining the number of scan chains and the order of scan registers connected to the scan chains so that the scan chain wiring is shortened during the layout of the LSI design, and the test input pattern generating step. The scan input pattern for scanning is Was determined in down determining step, it is an arrangement and a test input pattern changing step of changing depending on the order of the scan register that connects the number of scan chains, and scan chains.

Specifically, the invention according to claim (5) has a configuration according to claim (4), wherein after the scan chain determining step,
A circuit connection information change step of changing the circuit connection information relating to the LSI as if a scan register and a scan chain are inserted; and a circuit connection information changed in the circuit connection information change step, the circuit connection information is changed in the test input pattern change step. Executing a logical simulation using a scan input pattern for scanning.

(Operation) According to the LSI design method of the present invention, the scan register information and the circuit connection information as the information of the register to be replaced with the scan register are independently used at the time of layout by the configuration of the present invention. Since the wiring area of the scan chain can be optimized, and the scan register and the scan chain can be inserted without changing the circuit connection information, the number of LSI design steps can be reduced.

According to the configuration of the invention of claim (2), since the scan register information can be obtained as a result of generation of a test input, a high fault detection rate can be obtained by inserting a small number of scan registers.

According to the configuration of the invention of claim (3), by storing data of a plurality of blocks having the same function as data of one functional block, the storage amount can be reduced and a large-scale circuit can be handled. In addition, when there are many function blocks having scan registers in each layer of the LSI, the function blocks can be laid out so that the scan chain wiring is shortened.

According to the configuration of the invention of claim (4), the number of scan chains and the order of the scan registers connected to the scan chains are determined so as to be optimal on the layout, so that the circuit area can be reduced and the scanning operation can be performed at high speed. be able to. Further, by inserting the scan register and the scan chain at the time of layout, the inspection input pattern for scanning can be changed according to the order of the scan registers connected to the scan chain. As a result, the changed test input pattern can be applied as a test input pattern for a tester in a test process of LSI manufacture.

According to the configuration of the invention of claim (5), the circuit connection information is changed as if a scan register and a scan chain are inserted, so that in addition to the operation of the invention of claim (4), the scan register and the scan chain are further added. It is possible to execute a logic simulation on the circuit connection information after the insertion.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a process chart used to show a first embodiment of the present invention. In this embodiment, first, Step 101
Then, a hierarchical circuit design showing connections between functional blocks in each layer of the LSI and gate level connections in the functional blocks is designed, and connection information of the hierarchical circuits is stored.

Next, in step 102, a test input is generated for a stuck-at fault of a circuit in which the hierarchical circuit is expanded to a logic level, and information for replacing a register that hinders fault detection with a scan register is obtained.

Next, in step 103, a layout based on the hierarchical circuit designed in step 101 is performed, and functional blocks having registers to be replaced with scan registers are arranged so as to be close to each other.

Further, in step 104, using the replacement information for the scan register obtained in step 102, the designated register of the circuit already laid out in step 103 is replaced with a scan register.

Finally, in step 105, the optimal number of scan chains in layout and the order of scan registers connected to the scan chains are determined from the already laid out circuits in step 103, and the scan chains are inserted.

FIG. 2 is a layout diagram showing concrete processing according to the LSI design method of the first embodiment, and FIG.
FIG. 2 is a layout diagram created using the hierarchical circuit connection information in FIG. FIG. 2B shows the layout of FIG. 2A replaced with a scan register by using the replacement information on the scan register obtained in step 102.
FIG. 4 is a layout diagram in which scan lines are inserted.

In FIG. 2, reference numeral 201 denotes an LSI, and reference numerals 202 to 207 denote respective functional blocks. 208 to 216 are registers to be replaced with scan registers, and 216 to 232 are registers. Reference numeral 238 denotes a first scan chain, and 239 denotes a second scan chain. Reference numeral 234 denotes a scan-in terminal of the first scan chain 238, and 235 denotes a scan-out terminal of the first scan chain 238. 286 is a scan-in terminal of the second scan chain 239, and 237 is a scan-out terminal of the second scan chain 239. 240 to 248 are scan registers.

2 (a) and 2 (b), when laying out an LSI design, hierarchical circuit connection information composed of connection information between function blocks in each layer of the LSI and gate level connection information in the function blocks. A functional block utilizing scan register information indicating that it has been determined that a specific register in a circuit obtained by expanding a hierarchical circuit to a gate level at the time of generation of a test input is determined to be replaced with a scan register. An LSI design method for automatically inserting a layout and a scan chain will be described.

FIG. 2A is a layout diagram created using the hierarchical circuit connection information of LSI and the scan register information.
Blocks 202 and 203 are the same functional block, and blocks 204 and 207 are the same functional block. Therefore, the blocks 202, 204, 205, and 206 may be stored as circuit information.

FIG. 2B is a diagram in which the registers 208 to 216 are replaced with scan registers by using the replacement information for the scan registers, and the scan chains 238 and 289 are inserted so as to be optimal in layout. 216 is automatically replaced with scan registers 240 to 248, and the first scan chain scan-in terminal 234, the first scan chain scan-out terminal 235, the second scan chain scan-in terminal 236, and the second scan chain The scan-out terminal 237, the first scan chain 238, and the second scan chain 239 are automatically inserted.

Therefore, according to this embodiment, the connection information between the functional blocks in each layer of the LSI, the hierarchical circuit connection information including the gate-level connection information in the functional block, and another layer circuit connection information, By providing scan register information indicating that a specific register in a circuit obtained by expanding a hierarchical circuit at a gate level at the time of generation of test input is determined to be replaced with a scan register, each information is separately used at the time of layout, The storage amount of the functional blocks can be reduced, and replacement with a scan register and insertion of a scan chain can be performed automatically.

FIG. 3 is a process chart used to show a second embodiment of the present invention. In FIG. 3, first, in step 301, a hierarchical circuit design or logic design showing connections between functional blocks in each layer of the LSI and gate-level connections in the functional blocks is performed. Record the connection information of

Next, in step 302, a test input is generated for a stuck-at fault in a circuit in which the hierarchical circuit is expanded to a logic level, and information for replacing a register hindering fault detection with a scan register is obtained. The test input pattern generated irrespective of the determined register and the register determined to be replaced with the scan register are recognized as the scan register, and a scan chain connecting the scan registers in an appropriate order is assumed, and scanning is performed by scanning in and out. A test input pattern for scanning generated so as to read and write the internal state of the register is separately stored.

Thereafter, in step 303, a layout is performed based on the hierarchical circuit or logic circuit designed in step 301 and the replacement information for the scan register.

Next, in step 304, using the replacement information for the scan register obtained in step 302, the designated register of the circuit already laid out in step 303 is replaced with a scan register.

Next, in step 305, the optimal number of scan chains in layout and the order of scan registers connected to the scan chains are determined from the already laid out circuits in step 303, and the scan chains are inserted.

Thereafter, in step 306, a process of rearranging the inspection input patterns for scanning created in step 302 according to the number of scan chains inserted in step 305 and the order of scan registers connected to the scan chains is performed.

In the last step 307, the circuit connection information designed in the step 301 is replaced with the scan register replacement performed in the step 304, and
Perform the change processing like the insertion of the scan chain performed in 05.

FIG. 4 is a layout diagram showing specific processing by the LSI design method of the second embodiment. FIG. 4A shows the step 302.
4 (b) is the layout diagram of the circuit designed in step 301, and FIG. 4 (c) is changed in step 307. The logic level circuits after the above are shown. In FIG. 4, reference numeral 401 denotes an external input, 402 denotes a combinational circuit portion, and 403 denotes a combinational circuit.
Is an external output. 404 to 407 are registers to be replaced with scan registers, and 408 to 410 are registers. Reference numeral 411 denotes a scan-in terminal assumed at the time of generating a test input,
Is a scan-out terminal assumed when generating a test input. A scan chain 413 is assumed at the time of generating the test input. 414 is an LSI. 415 is a scan-in terminal actually arranged in the layout, and 416 is a scan-out terminal actually arranged in the layout. 417 is a scan chain actually inserted in the layout. 418 to 421 are scan registers.

4 (a) to 4 (c), when it is determined that a specific register in a circuit developed at the gate level is to be replaced with a scan register at the time of generation of a test input of an LSI, it is determined to be replaced with a scan register. The test input pattern generated regardless of the registered register and the scan test pattern generated so that the register determined to be replaced with the scan register is recognized as the scan register, and the internal state of the register is read and written by scan-in and scan-out. Are stored separately, the number of scan chains and the order of scan registers connected to the scan chains are determined at the time of LSI layout, and the stored scan input pattern for scan is connected to the number of scan chains and scan chains Change the registers to match the order, and After the scan chain insertion, scan register, modify the circuit connection information as to insert the scan chain, to allow execution logic, fault simulation for the circuit connection information after the change LS
I The design method will be described.

The registers 404 to 407 in FIG. 4A are recognized as scan registers at the time of generating a test input. Assume. Assume that the scan inspection input for a certain failure is (0,1,1,0). FIG. 4B shows the result of the layout performed in step 303. When the scan chains are inserted in the order assumed in FIG. 4 (a), the scan chains become like the scan chains 413 in FIG. 4 (b), and the wiring becomes clearly longer, the circuit area increases, and the scanning operation becomes slower.
Since the scan chain 417 is optimal for the layout of FIG. 4B, the scan chain 417 is inserted into the layout diagram. Since the scan chain 417 connects the scan registers 404, 406, 407, and 405 in this order, in step 306, the test input pattern (0,1,1,0) for scanning a certain failure created in step 302 is changed to (1,0,1,0). change. Further, as shown in FIG. 4C, the circuit connection information is changed so that the logic and the failure simulation can be executed again for the changed circuit.

According to this embodiment, when the test input of the LSI is generated, when it is determined that the specific register in the circuit developed at the gate level is to be replaced with the scan register, the specific register is generated regardless of the register that is determined to be replaced with the scan register. A step 302 of separately recognizing the test input pattern and the register determined to be replaced with the scan register as a scan register, and separately storing the test input pattern for scanning generated so as to read and write the internal state of the register by scan-in and scan-out. And a step 305 of determining the number of scan chains and the order of scan registers connected to the scan chains during the layout of the LSI, and detecting the scan detection stored in the step 302 of storing the test input pattern for the scan during the layout. Change the input pattern to the scan determined in By allowing changes in accordance with the order of the scan register that connects to the number of chains and scan chains, the wiring short length of the scan chain, to reduce the circuit area, the scanning operation can be performed at high speed.

In addition, after the scan register and the scan chain are inserted, the circuit connection information is changed as if the scan register and the scan chain were inserted. Can be.

(Effects of the Invention) As described above, according to the LSI design method of the inventions of claims (1) to (3), it is possible to increase the scale of the LSI and the scan register which the conventional LSI design method has. By solving the problem of automatic insertion of scan chains, it is possible to handle large-scale LSIs, and it is possible to obtain the effect of automatically inserting scan registers and scan chains in a layout without changing the circuit. .

Also, according to the LSI design method of the invention of claims (4) and (5), the problems of the circuit area and the speed of the scan operation which the conventional LSI design method has are solved, and the circuit area is reduced. And the scanning operation can be performed at high speed. Further, a logic simulation can be executed by changing the test input pattern and the circuit connection information, and a failure simulation can be executed.

[Brief description of the drawings]

FIGS. 1 and 2 show a first embodiment of the present invention.
FIG. 2 is a process diagram of the LSI design method, and FIG. 2A is a layout diagram created using hierarchical circuit connection information. FIG. 2B is a layout diagram in which a scan line is inserted by replacing the scan register by using the replacement information in the scan register. FIGS. 3 and 4 show a second embodiment of the present invention. FIG. 3 is a process diagram, FIG. 4 (a) is a circuit diagram of a logic level which is a target when performing test input generation, FIG. 4B is a layout diagram of the designed circuit, and FIG. 4C is a circuit diagram of a logic level changed after the scan register and the scan chain are inserted. FIG. 5 is a process chart showing a conventional LSI design method for deciding a layout using information at the time of generating a test input of an LSI. 101: a step of storing connection information of the hierarchical circuit accompanying the hierarchical circuit design 102: a step of obtaining information for replacing a register that hinders failure detection with a scan register 104: a step of replacing a register with a scan register 105: scan Step of inserting a chain 302 Step of storing a test input pattern 304 Step of replacing a register with a scan register 305 Step of inserting a scan chain 306 Step of rearranging a scan input pattern for scanning

Continuation of the front page (56) References JP-A-1-302850 (JP, A) JP-A-2-178863 (JP, A) JP-A-64-83169 (JP, A) JP-A-59-145541 (JP) , A) JP-A-2-132253 (JP, A) JP-A-55-87457 (JP, A) JP-A-60-147135 (JP, A)

Claims (5)

(57) [Claims] At the time of laying out an LSI design, circuit connection information relating to an LSI and scan register information indicating that a specific register in a circuit obtained by expanding the circuit connection information at a gate level is determined to be replaced with a scan register. By using, the number of scan chains and the order of scan registers connected to the scan chains are determined so that the scan chain wiring is shortened.
LSI design method. 2. The scan register information according to claim 1, wherein at the time of generation of a test input for an LSI design, it is determined that a specific register in a circuit developed at a gate level is to be replaced with a scan register. The described LSI design method. 3. The circuit connection information is hierarchical circuit connection information comprising connection information between functional blocks in each layer of an LSI for which a hierarchical circuit is designed, and gate-level connection information in the functional blocks. The LSI design method according to claim 1, wherein the layout of the functional block is determined so as to shorten the wiring of the scan chain by using the hierarchical circuit connection information and the scan register information at the time of the layout. . 4. When a specific register in a circuit is determined to be replaced with a scan register, the specific register determined to be replaced with a scan register is recognized as a scan register, and the specific register is determined by scan-in and scan-out. A test input pattern generation process for generating a test input pattern for scanning for reading and writing the internal state, and the number of scan chains and scans connected to the scan chains so that the scan chain wiring is shortened during LSI design layout A scan chain determining step for determining the order of the registers; and a scan input pattern for the scan generated in the test input pattern generating step, the number of scan chains determined by the scan chain determining step, and a scan connected to the scan chain. LSI designing method which is characterized by comprising a test input pattern changing step of changing in response to the order of the register. 5. A circuit connection information changing step of changing circuit connection information relating to an LSI as if a scan register and a scan chain have been inserted after the scan chain determining step, and a circuit connection information changed in the circuit connection information changing step. The LSI design method according to claim 4, further comprising the step of: executing a logic simulation using the scan input pattern changed in the test input pattern changing step.