JP2646547B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a MOS semiconductor device.

[Conventional technology]

Conventionally, the channel has been shortened in order to attempt a high-density design of the MOS type semiconductor device. However, when the channel shortening is performed using an N-channel MOS transistor on a P-type substrate, an electric field between a source and a drain becomes strong. In addition, the impact ionization development near the drain is amplified and the current flows to the substrate, and the electrons flow to the gate electrode side and are trapped in the gate insulating film, causing the fluctuation of the threshold voltage and the deterioration of the withstand voltage of the gate insulating film. Is not preferable in terms of reliability.

Also, the substrate current increases the substrate potential, and the drain current increases due to the NPN transistor structure.
The so-called snap-back voltage is reduced, so that a high drain voltage cannot be applied. Also, since the margin for the power supply voltage is reduced, there is no room for noise, which is a problem in reliability.

Although the shortening of the channel has been improved accordingly, and high-speed operation has become possible, the above-mentioned problems have hindered technical improvement.

Therefore, conventionally, in order to solve the above problem, a method of increasing the snap-back voltage by relatively reducing the concentration of the diffusion layer near the drain of the MOS transistor has been adopted.

Hereinafter, description will be made with reference to FIG. Here, a P-type substrate
This figure shows a method of manufacturing an N-channel transistor using the N.301.
Transistors are described as meaning to exhibit similar functional characteristics. That is, it is well known that in a complementary device, the above-mentioned development causes latch-up development, which is very disadvantageous. Considering this point, an example of a method that has been conventionally studied will be described.

First, as shown in FIG.
1, a field insulating film 302 is formed by a normal selective oxidation method,
A gate insulating film 303 is provided in the activation region, and a gate electrode 304 is formed over the gate insulating film 303 by adding impurities such as phosphorus to polycrystalline silicon. Thereafter, the impurity concentration is relatively reduced by ion implantation, and the source / drain diffusion layers 305 and 306 are formed.
To form

Next, as shown in FIG. 3B, a photoresist 307 is formed to cover at least the vicinity of the gate electrode 304 and the drain, and diffusion layers 308 and 309 having a high impurity concentration are formed.

After that, as shown in FIG.
For example, growth is performed using a vapor phase growth method or the like, predetermined contact holes for connection are opened, and metal wirings 311 and 312 are provided.

In this manner, the cross-sectional structure of the conventional example is shown in FIG. 3 (c). The structure of this transistor is such that the source / drain has a low impurity concentration region and a high impurity concentration region. This is characterized in that there is a region with a high impurity concentration at a certain distance from the gate electrode 304. When a voltage is applied to the drain due to this structure, the electric field strength between the drain having a low impurity concentration and the substrate is weakened, and the snap-back voltage is increased. The high-concentration diffusion layer is used to reduce the resistance of the source / drain to perform a high-speed operation.

[Problems to be solved by the invention]

In the above-mentioned conventional N-channel MOS transistor, the source and drain are determined in a self-aligned manner by the gate electrode 304, and in order to shorten the channel, the impurity concentration of the source / drain diffusion layer and the subsequent heat treatment are required. The depth of the diffusion layer and the size of the gate electrode must be reduced. In order to shorten the channel, it is conceivable to increase the impurity concentration of the substrate. However, even if this is effective in shortening the channel, the junction capacitance increases, and electron injection into the gate insulating film becomes difficult. This increases the speed and increases the reliability. In addition, since the gate electrode and the high-concentration region must be separated from each other, a margin is required as a lithography technique, which hinders high density.

An object of the present invention is to provide a method for manufacturing a semiconductor device capable of high-speed operation, having high density and improved reliability.

[Means for solving the problem]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a thick field insulating film on a semiconductor substrate of one conductivity type; and burying an active region surrounded by the field insulation with a semiconductor layer of the opposite conductivity type. Forming a groove extending from the surface of the semiconductor layer to the surface of the semiconductor substrate, and forming a thin insulating film on the entire surface including the groove surface after introducing one conductivity type impurity into the exposed semiconductor substrate. Forming a conductor layer on the entire surface, filling the groove, and then patterning to form a gate electrode extending from the active region on the field insulating film with a width wider than the width of the groove. Forming a high-concentration impurity layer of the opposite conductivity type on the semiconductor layer having a predetermined distance from an end of the gate electrode.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: forming a thick field insulating film on a semiconductor substrate of one conductivity type; and implanting impurities of the opposite conductivity type into the semiconductor substrate in an active region surrounded by the field insulating film. Introducing an impurity layer, forming a groove penetrating the impurity layer, and then introducing one-conductivity-type impurity into the semiconductor substrate exposed at the bottom of the groove, and thinning the entire surface including the surface of the groove. Forming an insulating film; removing the insulating film in the source / drain formation region; depositing a semiconductor layer of a reverse conductivity type in the activation region to fill the groove; and insulating the surface of the activation region by the field insulation. And a step of patterning the semiconductor layer to form an electrode serving also as a source / drain and a gate electrode having a width wider than the width of the groove.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

1 (a) to 1 (d) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a first embodiment of the present invention.

First, as shown in FIG.
A field oxide film 102 is formed on 1 by a normal selective oxidation method. The active region is a portion where the surface of the P-type semiconductor substrate 101 is exposed.

Next, as shown in FIG. 1B, an epitaxial layer containing an N-type impurity at a relatively low concentration is grown on the entire surface of the semiconductor substrate, and the field oxide film 10 is formed by a grinding method or a polishing method.
The N-type epitaxial layer 103 is buried in the active region so that no epitaxial layer remains on 2. Thereafter, a predetermined portion is removed by applying a photoresist 104, and using this photoresist 104 as a mask, N
A groove 113 extending from the surface of the epitaxial layer 103 to the inside of the P-type semiconductor substrate 101 is formed. Next, a P-type impurity is introduced into the bottom of the groove 113 by ion implantation, and the P-type impurity layer 105 is formed.
To form

Next, as shown in FIG.
After the removal, the gate insulating film 106 is formed by thermally oxidizing the trench and the epitaxial layer. Subsequently, for example, polycrystalline silicon containing impurities such as phosphorus is grown on the entire surface so as to fill the trench 113, and a photoresist 107 is formed leaving a portion where a gate electrode is to be formed, and this is used as a mask. Etch polycrystalline silicon and remove photoresist 107
A gate electrode 108 made of polycrystalline silicon is formed below.

At this time, a difference usually occurs between the edge of the gate electrode 108 and the edge of the photoresist 107. Then, using the photoresist 107 as a mask, an N-type impurity is introduced into the N-type epitaxial layer 103 by ion implantation, and the N ⁺ -type diffusion layer 1 is formed.
09,110 are formed. Therefore, the N ⁺ -type diffusion layers 109 and 110 are provided at a certain distance from the end of the gate electrode 108, and furthermore, the source and drain are formed by the N-type epitaxial layer 103 and separated by the trench 113. Is formed in the low concentration diffusion layer.

Next, as shown in FIG.
After the removal, the insulating film 111 is grown by a vapor phase growth method through an appropriate heat treatment, and a contact hole for connection is opened at a predetermined position. After that, the metal wiring 112 is provided to complete the MOS semiconductor device.

In the MOS type semiconductor device manufactured as described above, the channel length can be determined by the width and the depth of the groove 113 in one lithography, and high-density design can be performed. Further, since the drain diffusion layer is formed from the low-concentration N-type epitaxial layer 103, the snapback voltage is increased, and the power supply margin is increased, so that the reliability is improved.

In addition, since the P-type impurity layer 105 having a relatively high impurity concentration is formed only in the channel region and is not in contact with the source or drain diffusion layers, the source / drain diffusion layers have a further low concentration, so that the gate insulation is reduced. Electron injection into the film is suppressed, the electric capacity of the diffusion layer is reduced, reliability is improved, and high-speed operation is possible.

Further, since the region surrounded by the field oxide film is filled with the N-type epitaxial layer, there is no step, and since the trench 113 is filled with the gate electrode material, the surface is flattened and the metal wiring is There are advantages such as being able to increase the number of layers.

FIGS. 2 (a) and 2 (b) are cross-sectional views of a semiconductor chip for explaining a second embodiment of the present invention.

First, as shown in FIG.
First, a field oxide film 102 is formed. Next, an N-type impurity is introduced into the active region using an ion implantation method to form an N-type diffusion layer 203. This corresponds to N in FIG. 1 (b).
Type epitaxial layer 103.

Next, as shown in FIG. 2B, a groove is formed in the same manner as in the first embodiment, and thereafter, a P-type impurity layer 105 having a relatively high concentration is formed on the substrate. After forming the gate insulating film 106 and removing part of the gate insulating film, polycrystalline silicon containing an N-type impurity such as phosphorus is grown,
The trench is filled, and a region surrounded by the field oxide film 102 is filled. Next, the polycrystalline silicon is patterned by lithography to form a source / drain region 20.
6,207 and the gate electrode 208 are formed separately. Thereafter, an insulating film 111 is grown, and a contact hole is opened at a predetermined position.
The metal wiring 112 is provided to complete the MOS type semiconductor device.

In this second practical example, a low-concentration source / drain is formed by ion implantation over the entire active region of the substrate.
Forming a P-type impurity layer in the substrate at the bottom of the groove, and forming a gate electrode made of polycrystalline silicon and an electrode serving as a source / drain region via a gate insulating film. The structural feature is that the surface of the active region is flattened by performing it at the same time.

The MOS type semiconductor device thus formed has a relatively low concentration of the source and drain, increases the snap-back voltage, and reduces the electric capacity of the diffusion layer, thereby enabling high-speed operation. . In this second embodiment,
Gate electrode 208 and high-concentration source / drain regions 206 and 207
Can be formed at the same time, and since the electrodes serving as the source / drain regions are formed of polycrystalline silicon, compared to the case where the metal wiring is applied directly when the junction becomes shallow, the The influence of the spike is eliminated, and the leak current is suppressed. Accordingly, a shallow junction can be achieved, flattening can be performed at high density, the resistance of this electrode can be freely reduced, and high-speed operation can be performed.

In the above embodiment, a case where a P-type substrate is used has been described. However, the present invention can be applied to a P-channel transistor on an N-type substrate. The effect of making the up phenomenon difficult to occur is produced.

〔The invention's effect〕

As described above, according to the present invention, a reverse conductivity type impurity layer is formed on the surface of a semiconductor substrate of one conductivity type, a groove reaching the inside of the semiconductor substrate is dug in this impurity layer, a gate insulating film is formed on the surface, and this groove is formed. By filling the gate electrode and forming a high-concentration impurity layer of opposite conductivity type at a certain distance from the edge of the gate electrode, high-speed operation is possible, high-density design is possible, and reliability is improved. Thus, a semiconductor device with improved characteristics can be obtained.

[Brief description of the drawings]

FIGS. 1 (a) to 1 (d) and FIGS. 2 (a) and 2 (b) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining the first and second embodiments of the present invention. 3 (a) to (c) are cross-sectional views of a semiconductor chip for explaining a conventional method of manufacturing a semiconductor device. 101: P-type semiconductor substrate, 102: Field oxide film, 10
3 ... N-type epitaxial layer, 104 ... Photoresist, 10
5 ... P-type impurity layer, 106 ... Gate insulating film, 107 ... Photoresist, 108 ... Gate electrode, 109,110 ... N ⁺ type diffusion layer, 111 ... Insulating film, 112 ... Metal wiring, 113 ... Groove, 203
... N-type diffusion layer, 206, 207 ... source / drain region, 2
08 ... Gate electrode, 301 ... P-type semiconductor substrate, 302 ... Field insulating film, 303 ... Gate insulating film, 304 ... Gate electrode, 305,306 ... Source / drain diffusion layer, 307 ... Photoresist, 308,309 ... … Diffusion layer, 310 …… insulating film, 311,
312 ... Metal wiring.

Claims (2)

(57) [Claims] A step of forming a thick field insulating film on a semiconductor substrate of one conductivity type; a step of filling an active region surrounded by the field insulating film with a semiconductor layer of an opposite conductivity type to planarize the semiconductor; Forming a groove reaching from the surface of the layer to the surface of the semiconductor substrate, forming a thin insulating film on the entire surface including the groove surface after introducing one conductivity type impurity into the exposed semiconductor substrate, Forming a conductive layer and filling the groove, and then patterning to form a gate electrode extending from the active region on the field insulating film with a width wider than the width of the groove; and an end of the gate electrode. Forming a high-concentration impurity layer of a reverse conductivity type on the semiconductor layer having a predetermined distance from a portion. 2. A step of forming a thick field insulating film on a semiconductor substrate of one conductivity type, and introducing an impurity of a reverse conductivity type into the semiconductor substrate in an active region surrounded by the field insulating film to form an impurity layer. A step of introducing a one-conductivity-type impurity into the semiconductor substrate exposed at the bottom of the groove after forming a groove penetrating the impurity layer, and a step of forming a thin insulating film on the entire surface including the surface of the groove. Removing the insulating film in the source / drain formation region, depositing a semiconductor layer of the opposite conductivity type in the activated region, filling the trench, and making the surface of the activated region substantially coincide with the field insulating film. Patterning the semiconductor layer to form an electrode serving both as a source and a drain and a gate electrode having a width wider than the width of the groove.