JP2644573B2 - Switching method for two-sided buffer memory in image signal encoding device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a two-sided buffer memory between an encoding processing unit and a preprocessing unit thereof in an image signal encoding device used for a video conference or a video phone. It relates to a switching method.

(Prior Art) In an image signal encoding apparatus used for a video conference or a videophone, a period required for encoding processing of one frame such as a camera output (NTSC signal or the like) is determined by a transmission speed of a transmission path or an encoding apparatus. In the case where the frame rate is one frame cycle or more due to the low processing speed, a two-sided buffer memory may be provided between the encoding processing unit in the image signal encoding device and the preprocessing unit. By doing so, there is also an advantage that noise removal or the like can be performed between two pictures of the buffer memory, that is, between the encoded frame and the pre-processed frame.

The image signal encoding device converts an image signal from a camera or the like into an A /
After D conversion, separation into a luminance signal and a chrominance signal, and preprocessing such as noise removal, pixel data for one frame is written to one memory surface of a two-surface buffer memory. In parallel with this pre-processing, pixel data previously written to the other memory surface is read out for encoding processing.

FIG. 4 shows a flowchart of a method for switching a two-sided buffer memory in a conventional image signal encoding device. In the figure, side A is one side of the two-side buffer memory, side B is the other side, and at the start of processing such as when power is turned on, preprocessing of side A is started, and encoding processing is performed on side B. Shall be started.

YE of (A) when the pre-processing started on the A side is completed
In S), if the encoding process on the B side is not completed (NO in (A)), the preprocessing of the next frame is started again on the A side (C), and the previous frame is not encoded. It will be dropped.

Generally, the pre-processing period for one frame does not fluctuate equally to the frame period of an image signal from a camera or the like. However, the encoding processing period for one frame in the inter-frame encoding varies depending on the change in the image signal between the encoded frames, so that the number of dropped frames also varies.

On the other hand, if the encoding process on the B-side has been completed at the time when the pre-processing started on the A-side has been completed (YES in (A)) (YES in (A)), the pre-processing surface is changed to the B-side. , The encoding processing plane is simultaneously switched to the A plane (d).

Conversely, from the standpoint of the encoding process started on the B-side, it is as follows. At the time point when the encoding process on the side B is completed (YES in (e)), if the preprocessing on the side A is not completed (NO in (f)), the process waits for the end. (YES in (f)), the preprocessing surface is simultaneously switched to the B surface, and the encoding processing surface is simultaneously switched to the A surface (d).

Thereafter, in a similar manner, the preprocessing surface and the encoding processing surface are repeatedly switched between the A surface and the B surface at the same time.

FIG. 5 shows an example of a circuit which realizes a method for switching between two-sided buffer memories in a conventional image signal encoding device. In the figure, 1 is a pre-processing circuit, 2 is a pre-processing start signal generation circuit, 3 is a frame memory on two sides, 31 and 32 are A and B planes of the frame memory, 4 is a memory plane switching control circuit, and 41 is a memory plane switching control circuit. In the memory plane switching control circuit 4, a memory plane designating circuit composed of a 1-bit counter or the like, 42 is an encoding processing end signal holding circuit composed of a set-reset flip-flop or the like, 43 is an AND circuit, and 5 is a write circuit A control circuit 51, a switch for switching a write surface in the write control circuit 5, 52 a write address counter, 6 a preprocessing end signal generation circuit, 7 an encoding processing circuit, 8 an encoding processing start signal generation circuit, 9 Is a read control circuit, 91 is a read address counter in the read control circuit 9,
Reference numeral 10 denotes an encoding processing end signal generation circuit.

 This circuit operates as follows.

First, preprocessing and encoding processing are performed as follows. When handling an NTSC signal, the preprocessing start signal generation circuit 2 periodically generates a preprocessing start signal at a rate of about 30 times per second.

In response to this preprocessing start signal, the address counter 52 in the write control circuit 5 is reset, and any one of the frame memories 31 and 32 specified by the output Q of the memory surface specifying circuit 41 in the memory surface switching control circuit 4 The processing circuit 1 is connected by the switch 51 in the write control circuit 5, and the preprocessing circuit 1 starts writing preprocessed data from the head address.

The preprocessing circuit 1 supplies a clock to the address counter 52 to sequentially write preprocessed data while advancing the address value of the frame memory. Then, the preprocessing end signal generating circuit 6 outputs a preprocessing end signal to the memory surface switching control circuit 4 when detecting the end of the preprocessing.

On the other hand, upon the inversion of the output Q and the output of the memory surface designation circuit 41, the encoding process start signal generating circuit 8 generates an encoding process start signal. In response to the encoding start signal, the address counter 92 in the read control circuit 9 is reset, and any one of the frame memories 31 and 32 designated by the output of the memory plane designation circuit 41 and the encoding processing circuit 7
The encoding processing circuit 7 is connected by the switch 91 in the read control circuit 9 and starts reading the encoding processing data from the head address.

The encoding processing circuit 7 supplies a clock to the address counter 92 to sequentially read the encoding processing data while advancing the address value of the frame memory. And
The encoding process end signal generation circuit 10 outputs an encoding process end signal to the memory surface switching control circuit 4 when detecting the end of the encoding process.

Next, switching control of the preprocessing surface (writing surface) and the encoding processing surface (reading surface) in the two-surface frame memory 3 is performed as follows.

From the viewpoint of preprocessing, the preprocessing end signal generation circuit 6
Generates a pre-processing end signal for one side of the two-sided frame memory 3, the encoding process end signal generation circuit 10
Does not generate an encoding processing end signal for the other surface, since the encoding processing end signal has not been input to the holding circuit 42, the output of the preprocessing end signal generating circuit 6 and the Q output of the holding circuit 42 There is no change in the output of the AND circuit 43 that performs an AND operation with AND. Accordingly, there is no change in the output of the memory surface designation circuit 41, and the writing surface is not switched, so that the preprocessing circuit 1 overwrites the same memory surface with the preprocessed data of the next frame.

Conversely, if the encoding process end signal generation circuit 10 has already generated the encoding process end signal for the other surface and the holding circuit 42 holds the encoding process end signal, the logical product circuit 43
Rises to "1", and the output Q of the memory surface designating circuit 41 is inverted. Accordingly, the writing surface and the reading surface are simultaneously switched, the preprocessing circuit 1 writes the preprocessed data of the next frame on the other memory surface, and the encoding processing circuit 7 writes the preprocessed data written on one memory surface. The data is read as the next encoding data.

Note that the encoding process end signal held by the holding circuit 42 is reset by the output of the AND circuit 43 for switching the memory surface of the two-frame memory 3.

Conversely, from the viewpoint of the encoding process, when the encoding process end signal generating circuit 10 generates the encoding process end signal for the other surface of the two-sided frame memory 3, the preprocessing end signal generating circuit 6 When the preprocessing end signal for one surface has not been generated, the output of the AND circuit 43 does not change, only the encoding processing end signal is held in the holding circuit 42. Therefore, there is no change in the output of the memory surface designation circuit 41 and the read surface is not switched, so that the encoding process start signal generating circuit 8 does not generate an encoding process start signal, and the encoding process circuit 7 It waits for the start of the encoding process until switching.

As described above, when the preprocessing end signal generating circuit 6 generates the preprocessing end signal, the preprocessing surface and the encoding processing surface are simultaneously switched. Of course, when the pre-processing end signal is generated at the same time as the generation of the encoding processing end signal, the pre-processing surface and the encoding processing surface are simultaneously switched, so that it is not necessary to hold the start of the encoding process.

FIG. 6 shows a transition diagram of switching between the preprocessing plane and the encoding processing plane in the conventional switching method of the two-sided buffer memory shown in FIGS. 4 and 5 above. In the figure, W1, W2, W3,
.. Are pre-processing periods, R1, R2, R3,... Are encoding periods, A is one surface of the two-side buffer memory, and B is the other surface. Also, the shaded pre-processing period means the above-mentioned dropped frame which is not subjected to the encoding process.

6A shows the case where the encoding processing period R is within the pre-processing period W for one frame, that is, within the frame period of the input image signal, and FIG. (C) shows a case of 2 to 3 frame periods.

In FIG. 6 (a), if the encoding processing period R for one frame is always within the frame period, the difference period becomes a useless period without performing encoding processing, but the preprocessed frame is not used. Are all coded, so that there is an advantage that frame dropping does not occur. However, in this case, it is necessary to design the peak load such that the maximum value of the encoding processing period R is set within the frame period in consideration of the fact that the encoding processing period R8 fluctuates depending on the change of the image signal as described above. Becomes

In FIG. 6 (b), if the encoding processing period R for one frame is always within one to two frame periods, the difference period from the two frame period is a useless period in which no encoding processing is performed, and (Odd frames corresponding to W1, W3, W5, etc.) are dropped. Further, it is necessary to design a peak load such that the maximum value of the encoding processing period is within two frame periods.

In FIG. 6 (c), if the encoding processing period R for one frame is always within the period of two to three frames, the difference period from the three frame period is a useless period in which no encoding processing is performed, and 2/3 of the frames (W1, W2, W4, W5, W7, W8, etc.) are dropped. Further, it is necessary to design a peak load such that the maximum value of the encoding processing period is set within three frame periods.

The drawbacks of such a conventional two-sided buffer memory switching method are summarized as follows.

The first disadvantage is that even if the encoding process for one frame on one memory surface is completed, the encoding process for the next frame cannot be started until the preprocessing for the other memory surface is completed. A wasteful waiting period occurs.

The second drawback is that the encoding processing period R is equal to N of the frame period.
In the case of (N + 1) times, N frame dropouts always occur during the period, the frame dropout rate becomes N / (N + 1), and frame dropouts are likely to occur.

The third disadvantage is that even if the pre-processing of the head pixel data of a certain frame is started, the encoding of the frame cannot be started unless the pre-processing of the entire pixel data of the frame is completed. Since the encoding process of the data is started at least one frame cycle after the process is started, real-time performance is inferior.

The fourth disadvantage is that when the maximum frame drop rate is N / (N + 1), that is, when encoding is performed with N frames skipped, the peak value of the encoding processing period is set to be (N + 1) times or less the frame period. A load design is required, and an encoding device with a high processing speed corresponding to a peak load is required although almost no need is made.

(Object of the Invention) The object of the present invention is to eliminate such disadvantages.
After the encoding process of one memory surface is completed, even if the other memory surface is being pre-processed, the encoding process of the other memory surface is started, thereby eliminating an unnecessary waiting period of the encoding process, and Reduce dropping, improve real-time processing,
It is an object of the present invention to provide a two-sided buffer memory switching method of an image signal encoding device that enables an average load design.

(Structure of the Invention) (Differences between Features of the Invention and the Prior Art) In order to achieve the above object, the present invention provides a two-sided buffer between an encoding processing unit and a preprocessing unit of an image signal encoding device. In the memory switching method, it is detected that the encoding process for one frame (field) of the other memory surface is completed at the time when the pre-processing for one frame (field) for one memory surface is completed. Switch the pre-processing surface to the other memory surface, detect that the other memory surface is in the process of encoding, continue the next pre-processing on one memory surface, and encode the other memory surface When the processing is completed, the next encoding plane is immediately switched to one of the memory planes regardless of whether the preprocessing is in progress or the preprocessing is completed, and the read address for encoding does not pass the write address of the preprocessing. And controlled so, that the most important feature that is switched to pre-treated surface and the encoding process independently.

With the conventional technology, after the encoding process of one memory surface is completed,
The difference is that the encoding process of the other memory surface is started even if the other memory surface is being pre-processed. This eliminates useless waiting periods in the encoding process as in the related art, and reduces the number of dropped frames.

(Embodiment) FIG. 1 is a flowchart showing a method for switching a two-sided buffer memory when the method of the present invention is applied to an image signal encoding apparatus. In FIG. 1, side A is one side of a two-side buffer memory, side B is the other side, and at the start of processing such as when power is turned on, preprocessing of side A is started, and encoding is performed on side B. Shall be started.

YE of (A) when the pre-processing started on the A side is completed
In S), if the encoding process on the B side is not completed (NO in (A)), the preprocessing of the next frame is started again on the A surface (C), and the previous frame is encoded. It will be dropped without a piece.

On the other hand, when the encoding process for the B side has been completed ((a)
YES) switches the pre-processing surface to the B surface (d). After that, in a similar manner, the preprocessing surface is repeatedly switched between the A surface and the B surface.

From the standpoint of the encoding process started on the B side, it is as follows. If the preprocessing surface is the A surface, or if the preprocessing address precedes the coding processing address even if the preprocessing surface is the B surface (YES in (e)), the coding process is continued on the B surface. (F). Then, at the point of time when the encoding process on the B surface is completed (YES in (G)), the encoding process surface is switched to the A surface (h). Thereafter, in a similar manner, the coding processing plane is repeatedly switched between the A plane and the B plane.

As described above, the encoding process of the frame being pre-processed can be started without waiting for one frame period, while the encoding process address follows the pre-processing address within a range that does not pass. Further, as is clear from FIG. 1, the switching of the encoding process on the pre-processing surface is independent.

FIG. 2 is a block diagram of the image signal encoding apparatus 2 according to the present invention.
3 shows an example of a circuit for implementing a method of switching a plane buffer memory.
In FIG. 2, reference numerals 44 and 45 denote a memory plane designating circuit composed of a 1-bit counter or the like in the memory plane switching control circuit, 46 a comparison circuit for comparing the outputs of the memory plane designation circuits 44 and 45, and 47 a logical product. Circuit, 93 is an AND circuit in the read control circuit, 11 is an address control circuit that prevents the read address from overtaking the write address,
Reference numeral 111 denotes a comparison circuit for comparing a read address and a write address in the address control circuit 11, reference numeral 112 denotes a NAND circuit in the address control circuit, and the other circuit blocks are the same as those in FIG. .

 The circuit of FIG. 2 operates as follows.

First, preprocessing and encoding processing are performed as follows. When handling an NTSC signal, the preprocessing start signal generation circuit 2 periodically generates a preprocessing start signal at a rate of about 30 times per second. The pre-processing start signal causes the write control circuit 5
Of the frame memories 31 and 32 designated by the output Q1 of the memory plane designation circuit 44 in the memory plane switching control circuit 4 and the preprocessing circuit 1 The preprocessing circuit 1 starts to write preprocessed data from the head address.

By supplying a clock to the address counter 52, the preprocessing circuit 1 sequentially writes preprocessed data while advancing the address value of the frame memory. Then, the preprocessing end signal generating circuit 6 outputs a preprocessing end signal to the memory surface switching control circuit 4 when detecting the end of the preprocessing.

On the other hand, triggered by the inversion of the output Q2 of the memory surface designating circuit 45,
The encoding process start signal generating circuit 8 generates an encoding process start signal. By this encoding process start signal, the address counter 92 in the read control circuit 9 is reset,
Either of the surfaces of the frame memories 31 and 32 specified by the output Q2 of the memory surface specifying circuit 45 and the encoding processing circuit 7 are connected by a switch 91 in the read control circuit 9, and the encoding processing circuit 7 Start reading data for use from the start address. The encoding circuit 7 is an address counter
By supplying a clock to 92, the data for encoding processing is sequentially read out while advancing the address value of the frame memory. Then, upon detecting the end of the encoding process, the encoding process end signal generation circuit 10 outputs an encoding process end signal to the memory surface switching control circuit 4.

Next, switching control of the preprocessing surface (writing surface) and the encoding processing surface (reading surface) in the two-surface frame memory 3 is performed as follows.

From the viewpoint of preprocessing, the preprocessing end signal generation circuit 6
Generates a pre-processing end signal for one side of the two-sided frame memory 3, the output of the comparison circuit 46 becomes "1" only while the outputs Q1 and Q2 of the memory side designating circuits 44 and 45 match. Only when the output of the AND circuit 47 which takes the AND and outputs the AND of the comparison circuit 46 and the output of the pre-processing end signal generating circuit 6 rises to "1", the output Q1 of the memory surface designation circuit 44 is inverted, The preprocessing circuit 1 starts writing the preprocessed data of the next frame to the other memory surface.

Otherwise, since the output of the comparison circuit 46 has not risen to “1”, the AND circuit 47 and the memory surface designation circuit
There is no change in the output of 44 and the writing surface is not switched, and the preprocessing circuit 1 overwrites the same memory surface with the preprocessed data of the next frame. That is, if the encoding process is being performed on the same memory surface at the end of the preprocessing for one memory surface, the next preprocessing is switched to the other memory surface because the other memory surface is free. If the other memory surface is being encoded, the next preprocessing is performed again on one memory surface.

Conversely, from the viewpoint of the encoding process, when the encoding process end signal generating circuit 10 generates the encoding process end signal for the other surface of the two-sided frame memory 3, the memory surface designation circuit 45 Output Q2 is inverted. Therefore, the read surface is switched without waiting for the encoding process, and the encoding processing circuit 7 reads the preprocessed data written in one memory surface as the next encoding data.

In this case, a period occurs in which the pre-processing surface and the encoding processing surface are on the same surface. If during this period the reading address for the encoding process exceeds the writing address for the pre-processing, the read data becomes two frames that are temporally different. Therefore, it is necessary to control the read address. For example, when reading the encoding processing data line by line, the comparison circuit 111 uses the address counters 52 and 92
Are compared, and if the values are the same, the output rises to "1". Therefore, if the output of the comparison circuit 46 rises to "1", the NAND of the outputs of the comparison circuits 111 and 46 is taken. The output of the product circuit 112 falls to “0”.

The AND circuit 93 which ANDs the output of the NAND circuit 112 and the clock output of the encoding processing circuit 7 stops the clock supply to the address counter 92 and prevents the read address from proceeding. Can be controlled not to overtake the write address.

8 or 16 pixels in the horizontal direction and 8 or 16 pixels in the vertical direction
When reading is performed for each line block, the comparison circuit
Reference numeral 111 requires that the output be raised to "1" every time the read line address value catches up with the write line address value by 8 or 16 lines.

FIG. 3 shows a transition diagram of switching between the preprocessing plane and the encoding processing plane in the switching method of the two-side buffer memory according to the present invention. In the figure, W1, W2, W3,...
.. R2, R3,... Are encoding processing periods, the A side is one side of the two-side buffer memory, and the B side is the other side. The shaded pre-processing period means a dropped frame that is not encoded.

3A shows the case where the encoding processing period R is within the pre-processing period W for one frame on a time average, that is, within the frame period of the input image signal, and FIG. (C) is a time average of 2
1 to 3 frame periods.

In FIG. 3 (a), if the encoding processing period R for one frame is always within a one-frame period on a time average basis, even if the one-frame period is sometimes exceeded, a maximum of two frames can be obtained without dropping frames. Acceptable up to the frame period. Further, the average load can be designed so that the time average value of the encoding processing period is within one frame period.

In FIG. 3 (b), if the encoding processing period R for one frame is always within the period of one to two frames on a time average basis, the dropped frame occurrence rate is reduced to 1 / A maximum of three frame periods can be tolerated without increasing to two or more.

Further, it is possible to design an average load such that the time average value of the encoding processing period is set within two frame periods.

In FIG. 3 (c), if the encoding processing period R for one frame is always within the period of two to three frames on an average in terms of time, the occurrence rate of dropped frames is sometimes reduced to 2 / A maximum of four frame periods can be tolerated without increasing the number to three or more. Further, it is possible to design an average load such that the time average value of the encoding processing period is within a period of three frames.

For convenience of explanation, the preprocessing is started on the A side when the power is turned on, and the encoding process is started on the B side. However, the reverse is also possible. Further, since the switching between the preprocessing surface and the encoding processing surface is performed independently, if the encoding processing address is not overtaken by the preprocessing address, even if the preprocessing and the encoding processing are started on the same surface, good. Further, when the number of pixel data for one frame consisting of two fields is too large in terms of processing speed, only odd or even one-field pixel data may be handled.

(Effects of the Invention) As described above, according to the present invention, after the encoding process of one memory surface is completed, the encoding process of the other memory surface is performed even if the other memory surface is being pre-processed. Starting has the following advantages:

The first advantage is that the useless processing time of the encoding process can be eliminated as compared with the related art, so that the processing capability of the encoding processing unit can be effectively used to the maximum.

The second advantage is that when the time average value of the encoding processing period is N to (N + 1) times the frame period, the frame drop rate is (N-
1) The ratio becomes / N to N / (N-1), and the frame drop rate can be reduced as compared with the related art.

The third advantage is that the encoding process of the frame being pre-processed can be started without waiting for one frame period while the encoding process address follows the pre-processing address within a range that does not overtake the pre-processing address. It is to be able to enhance the nature.

A fourth advantage is that when the maximum frame drop rate is N / (N + 1), the time average value of the encoding processing period is set to N
Since the average load can be designed to be twice or less, the processing speed of the encoding device may be lower than that of the related art.

[Brief description of the drawings]

FIG. 1 is a flowchart for switching a two-sided buffer memory according to the present invention, FIG. 2 is a diagram showing an example of a circuit for implementing a two-sided buffer memory switching method according to the present invention, and FIG. FIG. 4 is a switching transition diagram of a conventional two-sided buffer memory, FIG. 5 is a diagram showing a circuit example for implementing a conventional two-sided buffer memory switching method, and FIG. FIG. 10 is a switching transition diagram between a conventional preprocessing plane and an encoding processing plane. 1... Pre-processing circuit, 2... Pre-processing start signal generating circuit, 3
…… Two-sided frame memory, 31 …… Frame memory (A
32) Frame memory (B surface), 4 ... Memory surface switching control circuit, 44, 15 ... Memory surface designation circuit, 46, 111 ...
... comparator circuit, 47,93 ... AND circuit, 5 ... write control circuit, 51,91 ... switch, 52,92 ... address counter, 6 ... preprocessing end signal generation circuit, 7 ... encoding Processing circuit 8, encoding processing start signal generation circuit 9, readout control circuit 10, encoding processing end signal generation circuit 11,
... Address control circuit, 112 NAND circuit.

Claims (1)

(57) [Claims] In a method for switching between two buffer memories between an encoding processing unit and a preprocessing unit of an image signal encoding device, preprocessing for one frame (field) for one memory surface is completed. At this point, it is detected that the encoding process for one frame (field) of the other memory surface has been completed, the preprocessing surface is switched to the other memory surface, and the other memory surface is in the encoding process. The next pre-processing is continuously performed for one memory surface after detecting that there is, and when the encoding process for the other memory surface is completed,
Immediately switches the next encoding plane to one of the memory planes irrespective of whether preprocessing is in progress or the end of preprocessing, and controls the read address for encoding so that it does not pass the write address of the preprocessing. A two-sided buffer memory switching method for an image signal encoding device, wherein a processing surface and an encoding processing surface are independently switched.