JP2643898B2 - Resin-sealed semiconductor device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-sealed semiconductor device, and more particularly to a resin-sealed semiconductor device with improved electrical characteristics between electrodes of a semiconductor chip to be mounted and outer leads, and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, the number of input / output terminals has been increased in accordance with higher integration and more functions of a semiconductor chip (hereinafter, referred to as an IC chip). When mounting these IC chips, use a DIP (Dual In-line Packa).
Ge) was used as a standard, but it was sometimes difficult to mount due to restrictions on the number of terminals, mounting method, strength, price, etc., and various resin-sealed packages or mounting methods have been developed.

As described above, high integration of IC chips,
With the increase in the number of functions, the number of input / output terminals is increasing.
For example, about 300 to 6 for an IC chip of 10 to 15 mm square
Some have a 00 pin input / output terminal. For example, the inner lead bonding (IL
B) The mounted IC chip is mounted on a printed circuit board by outer lead bonding (OLB).
When it comes to a multi-pin IC chip with 100 to 600 pins,
The OLB needs to be highly accurate, and the OLB becomes difficult. That is, the lead strength and the dimensional accuracy are reduced, and the solder bridge is defective when mounted on the board. In addition, lead inductance has also become a problem as the number of terminals increases and the functionality increases.

An example for solving such an improvement in the electrical characteristics is described in Japanese Patent Application Laid-Open No. 63-246851. FIG. 4 is a perspective view illustrating constituent members of a lead frame for mounting the semiconductor device described in the publication.
4A, which shows a partial cross-sectional view of a resin-encapsulated semiconductor device using this lead frame, FIG. 4A shows an annular insulating tape 22 adhered to the lower surface of the inner lead 21, and FIG. It has a metal plate 23 bonded below as a power supply potential supply layer, an annular insulating tape 24 bonded thereunder, and a metal plate 25 bonded below as a ground potential supply layer. I have.

[0005] These metal plates 23, 25 are provided with projections (tabs) 26a, 2
6b, 27a, and 27b, and these metal plates are provided at sides and corners where these tabs do not overlap. These members are laminated, and these tabs 26a, 26b, 27a, 27b are respectively joined to the power supply potential supply lead and the ground potential supply lead of the internal lead group 21 by electric welding (FIG. 4).
(See reference numeral 26a in (b)) The lead frame 21 is formed.

[0006] An IC chip 28 is mounted on the lead frame 21 described above, and each electrode of the IC chip and the inner lead group 2 are mounted.
1 are connected by wire bonding. At this time, the power supply potential supply electrode is wire-bonded to the metal plate 23 and the ground potential supply electrode is wire-bonded to the metal plate 25. For example, the metal plate 23 is connected to the inner lead 29 by a tab 26a. Are electrically welded to each other, and are sealed by the resin 30.

The joining of the metal plates reduces the lead inductance of the power supply system and the ground system.

On the other hand, another example for solving the difficulty and the improvement of the electric characteristics of the OLB with higher precision is disclosed in Japanese Patent Application No. Hei.
No. 75067. Referring to FIG. 5, which shows a cross-sectional view of the semiconductor device, metal wiring layers 31, 32 and 33, 34 each formed of an inner lead and an outer lead formed on both surfaces of a flexible insulating substrate 1 by a conductor layer.
And a metal plate 35 connected to a power supply potential supply or ground potential supply lead in a region surrounded by the leads 33 and 34 on the upper surface of the substrate. 33 and 36 are through-holes 37, and leads 32 and 34 are through-connected with through-holes 38, respectively.
By providing the connecting portion 31a and the second connecting portion 36, an outer outer lead pitch twice as large as that of the conventional case is obtained.

Further, a semiconductor device 40 is mounted face-down on the back surface of the substrate, and each electrode of the semiconductor device 40 is bonded to leads 31 and 32 by wires 41 and sealed with a resin 42.

With the above-described configuration, the solder bridge defect is improved and the lead impedance for supplying the power supply potential or the ground potential is reduced.

[0011]

In the above-mentioned conventional resin-encapsulated semiconductor device, when attention is paid to a configuration for reducing the lead inductance of the power supply system and the grounding system,
The object is achieved by disposing a part of a lead path having a large inductance as a part of a lead on a metal plate or a metal layer on a flat plate having a small inductance.

However, the size of the metal plate or metal layer provided as a part of the lead is limited to the size of the sealing package itself because it is accommodated in the resin sealing. become.

Therefore, the effect of compensating for the lead path is about ４ to に 対 し て of the entire lead path, the actual inductance reduction effect is about 10 to 50%, and the function of the mounted IC chip is reduced. In some cases, impedance reduction has not yet been sufficient.

SUMMARY OF THE INVENTION An object of the present invention is to provide a resin-sealed type in which the lead impedance in a power supply system and a grounding system from an electrode of a mounted IC chip to a tip end of an outer lead is reduced as compared with the prior art. It is to provide a semiconductor device.

[0015]

A feature of the resin-encapsulated semiconductor device of the present invention is that an inner lead group, an outer lead group, and an island are formed on one surface of a flexible insulating substrate by using a conductor pattern, and In the resin-encapsulated semiconductor device in which each electrode of the semiconductor chip mounted on the island is wire-bonded to the inner lead group and an internal region excluding the outer lead group is sealed with resin, While the entire surface other than a part of the part is covered with one conductor layer solid pattern,
The conductive layer solid pattern is to be electrically connected only to a predetermined electrode of the electrode group.

Further, the conductive layer solid pattern is connected to each end of the power supply lead or the ground potential supply lead of the outer lead group and the island, respectively, and the island is connected to the semiconductor chip. It is wire-bonded to either the power supply potential supply electrode or the ground potential supply electrode.

Further, the entire surface other than a part of the corner portion on the other surface is covered with a solid pattern of the conductor layer divided into a plurality of sheets, and the island is also divided corresponding to the plurality of sheets. The conductive layer solid pattern is connected to the predetermined outer lead tip and the island through holes, respectively, and each of the plurality of islands is one of a power supply potential supply electrode and a ground potential supply electrode of the semiconductor chip. It may be wire-bonded to the corresponding electrode.

Further, the semiconductor chip is mounted in a face-down state by bonding to the island formed by the conductor pattern using an insulating adhesive.

The method of manufacturing the resin-encapsulated semiconductor device according to the present invention is characterized in that an inner lead group, an outer lead group, and an island are formed on one surface of a flexible insulating substrate by using a conductor pattern, and the island is formed on the island. In a method for manufacturing a resin-encapsulated semiconductor device in which each electrode of a semiconductor chip to be mounted is wire-bonded to the inner lead group and an internal region excluding the outer lead group is sealed with resin, a part of a corner portion on the other surface is provided. The entire surface other than the conductive layer solid pattern is covered with a single conductive layer solid pattern, and the conductive layer solid pattern is connected to the predetermined lead end portion of the outer lead group and a predetermined lead end portion and the island through the flexible hole. Using a conductive insulating substrate, and attaching the semiconductor chip to an island of the substrate with an insulating adhesive. A first step of bonding by means of paste-down, and when connecting the electrode group of the semiconductor chip and the inner lead group by wire bonding, either the power supply potential supply electrode or the ground potential supply electrode of the electrode group and the island are connected. And a second step of performing wire bonding connection.

Further, the entire surface other than a part of the corner portion of the other surface is respectively covered with a plurality of divided conductor layer solid patterns, and the islands are also divided corresponding to the plurality of sheets. The conductive layer solid pattern uses the flexible insulating substrate connected to the predetermined lead end portion and the island of the outer lead group and the island through holes, respectively, and straddles the divided islands of the substrate. A first step of bonding the back surface of the semiconductor chip to be mounted face down with an insulating adhesive, and a power supply of the electrode group when the electrode group of the semiconductor chip and the inner lead group are connected by wire bonding. Each of the potential supply electrode and the ground potential supply electrode corresponds to one of the divided islands. It may have a second step of each wire bonding towards that.

[0021]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1A is a sectional view showing a first embodiment of the present invention, and FIG. 2B is a partial perspective view thereof. FIG. 2A is a partial bottom view showing an embodiment before resin sealing, and FIG. 2B is a partial plan view thereof.

Referring to FIGS. 1A and 2A, the upper surface of the flexible insulating substrate 1 corresponds to the substrate shape up to the upper end of the outer lead formed by the conductive pattern on the back surface of the substrate. Thus, one conductive layer solid pattern 2 covering the entire surface is provided.

On the lower surface of the flexible insulating substrate 1, an island 4 of a predetermined size larger than the bottom area of the IC chip 3 mounted at the center is provided by a conductive pattern. Inner leads 5a, 5b and outer leads 6a, 6b of a conductive pattern are provided so as to surround the island 4.

Further, each electrode except the ground potential supply electrode of the IC chip 3 mounted face down on the island 4 is bonded to the inner lead 5a by a wire 7a.

Only the ground potential supply electrode is directly bonded to the island 4 by wire 7b.
The island 4 has a through hole 8 provided in advance for penetrating the conductive solid pattern 2 on the substrate surface.
a and 8b.

Further, the leading end of the outer lead 6b for supplying the ground potential on the back surface of the substrate is also penetrated to the conductor layer solid pattern 2 on the substrate surface by a through hole 8c provided in advance.

In this state, the region including the inner leads 6 and the islands 4 is sealed with the resin 9.

Referring to FIG. 2B, the through hole 8a of the conductive layer solid pattern 2 corresponding to the through hole 8a of FIG. 2A and the through hole 8c provided in the outer lead 6b of FIG. Conductive layer solid pattern 2 corresponding to
Is provided.

The conductive layer solid pattern 2 has a corner portion cut at a right angle, and both surfaces of the substrate 1 are integrally filled with the resin 9 through the cutout portion (at four corners). .

Referring to FIG. 1 (b), the semiconductor device sealed with the resin according to the above-described structure has a structure in which the upper portions of the outer leads 6a and 6b protruding to the outside from each side include the gaps between the leads. It can be understood that a through hole 8c that is covered with the conductor layer solid pattern 2 with the interposition therebetween and that connects the outer lead 6b and the conductive layer solid pattern 2 is provided at the tip of the outer lead 6b.

Therefore, the conductor layer solid pattern 2 is extended to the ends of the outer leads 6a and 6b without being limited to the inside of the package as in the prior art. As a result, the grounding system has a large area, and therefore the resistance value is large. Is connected in series with the output end of the outer lead 6b and is used as a ground potential supply lead.
The lead inductance is smaller than that of a grounding path from the electrode 10 to the inner lead 5b by wire bonding to the outer lead 6b.

The lead inductance becomes smaller, for example, about 2 to 7 nH compared to the conventional 20 nH, and the lead impedance can be reduced.

As a secondary effect, there is also an effect that the upper surface of the substrate is entirely covered with a conductive layer solid pattern and grounded, so that the semiconductor device to be mounted is shielded.

In the above configuration, the ground potential supply electrode 10
Is connected to the island 4 by wire bonding, but may be applied to a power supply potential supply electrode.

Next, referring to FIG. 3 (a) showing a second embodiment of the present invention in a partial bottom view and FIG. 3 (b) showing a partial plan view thereof, these figures show resin sealing. The state before the stop is shown. The difference from the first embodiment is that the island 4 and the conductive layer solid pattern 2 in the first embodiment are each divided into at least two regions, and one region is a power supply system. Is connected to the power supply potential supply outer lead as the conductor layer, and the other region is connected to the ground potential supply outer lead as the grounding system.

That is, the island 4 is composed of two regions, a ground system island 4a and a power supply system island 4b.
The conductive solid pattern 2 is a ground-type conductive solid pattern 2a.
And the power supply system conductive solid pattern 2b.

Ground potential supply electrode 10 of IC chip 3
Is connected by wire bonding to an arbitrary connection point 11 of the island 4a, and is connected to the through hole 8a of the conductive layer solid pattern 2a via the through hole 8a. The conductive layer solid pattern 2a is further connected to the front end of the outer lead 6b on the back surface of the substrate via a through hole 8c.

The other components are the same as those of the first embodiment, and the same components are denoted by the same reference numerals and description thereof is omitted.

According to the above-described configuration, the grounding system has a large area, and therefore the conductive solid pattern 2a having a low resistance value is inserted in series with the tip of the outer lead 6b and used as a ground potential supply lead. The impedance can be reduced as compared with the path of the grounding system from the wire 10 to the inner lead 5b and to the outer lead 6b.

On the other hand, the power supply potential supply electrode 12 of the IC chip 3 is connected by wire bonding to an arbitrary connection point 13 of the island 4b, and the through-hole 1 of the island 4b is formed.
4 through hole 14 of conductive layer solid pattern 2b
Connected to. The conductive layer solid pattern 2b is further connected to the end of the outer lead 6c on the back surface of the substrate via the through hole 15.

Also in this case, the power supply system has a large area, and therefore the conductive solid pattern 2b having a low resistance value is inserted in series with the tip of the outer lead 6c and used as a power supply lead. The impedance can be reduced as compared with the path of the power supply system that is wire-bonded to the inner lead 5c and reaches the outer lead 6c.

In the method of manufacturing a resin-encapsulated semiconductor device according to the above-described embodiment, in the case of the first embodiment, the entire surface other than a part of the corner portion is covered with one conductive layer solid pattern 2, and The conductor layer solid pattern 2 has outer leads 6
(b) a flexible insulating substrate in which at least one portion is connected to a tip portion of the island 4 and the island 4 at least one through hole, and the semiconductor chip 3 is bonded face down to the island 4 of the substrate by an insulating adhesive; After the step, when the electrode group and the inner lead group of the semiconductor chip 3 are connected by wire bonding, either the power supply potential supply electrode 12 or the ground potential supply electrode 10 of the electrode group and the island 4 are connected by wire bonding. A second step is performed.

In the case of the second embodiment, the entire surface including the outer lead group except for a part of the corner portion is covered with the two solid conductive patterns 2a and 2b, and the island on the back surface is also divided into the islands 4a and 4b. The conductive layer solid pattern 2a is formed by the tip of the outer lead 6b and the island 4a.
And at least one of the through holes 8c and 8
a, and the conductor layer solid pattern 2b uses a flexible insulating substrate 1 in which at least one portion is connected to the tip of the outer lead 6c and the island 4b by through holes 15 and 14, respectively. Island 4
a, 4b, and the semiconductor chip 3 with an insulating adhesive.
After the first step of bonding the semiconductor chip 3 face down, when the electrode group and the inner lead group of the semiconductor chip 3 are connected by wire bonding, the ground potential supply electrode 10 and the island 4a of the electrode group and the power supply potential supply electrode 12 are formed. And the island 4b are connected by wire bonding.

After that, the semiconductor device after the above-described second step is housed in a cavity formed according to a known resin encapsulation technique so as to conform to a predetermined package shape. Resin is enclosed. In this case, the resin flows into the upper surface through the notch formed in the corner region, and is designed so that the resin is uniformly injected into the upper and lower surfaces.

The resin encapsulation is set by being sandwiched between a lower mold and an upper mold which are heated to a high temperature of 150 ° to 180 ° C., clamped by a mold press, and filled with a thermoplastic resin having a fluidity of 60 to 180 ° C. The package is transfer-molded by injecting it into a mold at a low pressure of 120 kg / cm ² , and then a lead is molded.

[0047]

As described above, according to the resin-encapsulated semiconductor device and the method of manufacturing the same of the present invention, the inner leads, the outer leads, and the islands are formed on one surface of the flexible insulating substrate in a conductive pattern. On the other side, the entire surface other than the corners was covered with a single conductive layer solid pattern, the island, the conductive layer solid pattern, and the outer lead tips were connected by through holes, and mounted face-down on the islands A ground current supply path is formed by wire bonding the ground potential supply electrode of the semiconductor chip to the island at the shortest distance, and the island and the conductive layer solid pattern have two regions of a ground system and a power system island, respectively. Of each system, conductive layer solid pattern and outer lead And the power supply potential supply electrode and the ground potential supply electrode are wire-bonded to the islands of the respective systems at the shortest distance to form current paths for the ground system and the power system. In the path from each of the power supply potential supply electrode and the ground potential supply electrode to the corresponding end of the outlead, a large area conductive layer solid pattern is inserted from the island to the lead inductance. Becomes smaller than before, and the impedance can be reduced.

[Brief description of the drawings]

FIG. 1A is a cross-sectional view showing a first embodiment of the present invention. (B) is a partial perspective view thereof.

FIG. 2A is a partial bottom view showing the embodiment before resin sealing. (B) It is the fragmentary top view.

FIG. 3 (a) is a partial bottom view showing an embodiment before resin sealing of the second embodiment. (B) It is the fragmentary top view.

FIG. 4A is a perspective view for explaining constituent members of a lead frame on which a conventional semiconductor device is mounted. FIG. 3B is a partial cross-sectional view of the resin-sealed semiconductor device using the lead frame.

FIG. 5 is a sectional view showing another conventional semiconductor device.

[Description of Signs] 1 Flexible resin substrate 2 Conductor layer solid pattern 3, 28, 40 IC chip 4, 4a, 4b Island 5a, 5b, 21 Inner lead 6a, 6b Outer lead 7a, 7b, 41 Wire 8a, 8b, 8c, 14, 15, 37, 38, 39
Through hole 9, 30, 42 Resin 10 Electrode for ground potential supply 11, 13 Arbitrary point of island 12 Power supply electrode 20 Lead frame 22, 24 Insulating tape 23 Metal plate to be power layer 25 Metal plate to be ground layer 26a, 26b, 26c, 27a, 27b Tab 29 Power supply potential lead 31, 32, 33, 34 Metal wiring layer 31a First connection 35 Metal plate 36 Second connection

Claims (6)

(57) [Claims] An inner lead group, an outer lead group and an island are formed on one surface of a flexible insulating substrate using a conductor pattern, and each electrode of a semiconductor chip mounted on the island is connected to the inner lead group. In the resin-encapsulated semiconductor device in which the internal regions other than the outer lead group are respectively sealed by resin while being wire-bonded and connected, the entire surface other than a part of the corner portion on the other surface is covered with a single conductive layer solid pattern. A resin-encapsulated semiconductor device, wherein the conductive layer solid pattern is electrically connected only to predetermined electrodes of the electrode group. 2. The conductor layer solid pattern is connected to each end of a power supply lead or a ground potential supply lead of the outer lead group and the island, respectively, and the island is connected to the semiconductor chip. 2. A wire bonding connection to one of the power supply potential supply electrode and the ground potential supply electrode.
The resin-encapsulated semiconductor device according to claim 1. 3. An entire surface other than a part of a corner portion of the other surface is covered with a conductor layer solid pattern divided into a plurality of sheets, and the islands are also divided corresponding to the plurality of sheets. The conductive layer solid pattern is connected to the predetermined outer lead tip and the island through holes, respectively, and each of the plurality of islands is one of a power supply potential supply electrode and a ground potential supply electrode of the semiconductor chip. 2. The resin-encapsulated semiconductor device according to claim 1, wherein the semiconductor device is wire-bonded to a corresponding electrode. 4. The resin encapsulation according to claim 1, wherein the semiconductor chip is mounted in a face-down state by bonding to the island formed by the conductor pattern using an insulating adhesive. Type semiconductor device. 5. An inner lead group, an outer lead group, and an island are formed on one surface of a flexible insulating substrate by using a conductor pattern, and each electrode of a semiconductor chip mounted on the island is respectively associated with the inner lead group. In the method of manufacturing a resin-encapsulated semiconductor device for performing wire bonding connection and sealing an internal region excluding the outer lead group with a resin, the entire surface other than a part of a corner portion on the other surface is covered with one conductive layer solid pattern. In addition, the conductive layer solid pattern uses the flexible insulating substrate which is connected to the predetermined lead end portion of the outer lead group and the island through holes, respectively, and has an insulating property on the island of the substrate. A first step of bonding the semiconductor chip face down with an adhesive; A second step of wire bonding connecting either the power supply potential supply electrode or the ground potential supply electrode of the electrode group and the island when the electrode group of the chip and the inner lead group are connected by wire bonding. A method for manufacturing a resin-encapsulated semiconductor device, comprising: 6. An entire surface other than a part of a corner portion of the other surface is respectively covered with a plurality of conductor layer solid patterns formed separately, and the islands are also divided corresponding to the plurality of sheets. The conductive layer solid pattern uses the flexible insulating substrate connected to the predetermined lead end portion and the island of the outer lead group and the island through holes, respectively, and straddles the divided islands of the substrate. A first step of bonding the back surface of the semiconductor chip to be mounted face down with an insulating adhesive, and a power supply of the electrode group when the electrode group of the semiconductor chip and the inner lead group are connected by wire bonding. Each of the potential supply electrode and the ground potential supply electrode is connected to a corresponding one of the divided islands. 6. A method for manufacturing a resin-encapsulated semiconductor device according to claim 5, further comprising a second step of performing wire bonding connection on each of the semiconductor devices.