JP2642035B2 - Storage access processor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage access processing device, and more particularly to a storage access processing device having an address conversion table.

[0002]

2. Description of the Related Art Conventionally, in this type of storage access processing apparatus, as shown in FIG. 2, a plurality of address translation tables (Address Translation B) are used.
UTF (ATB) 4-1 to 4-n, the logical address held in the logical address holding unit 1 is converted into a physical address and held in the physical address holding unit 6.

The logical address holding unit 1 comprises a space number holding unit 1a, a page number holding unit 1b, and an in-page address holding unit 1c, and the physical address holding unit 6 includes a physical page number holding unit 6a and an in-page address. And a holding portion 6b.

When converting a logical address into a physical address, each of the address conversion tables 4-1 to 4-n converts a page number of a logical address in one space into a physical page number of a physical address. Therefore, a directory 2 is provided which holds the space numbers of the address conversion tables 4-1 to 4-n in order to indicate which space the address conversion tables 4-1 to 4-n correspond to. Here, the directory 2 stores space number holding units 2a-1 to 2a-1 corresponding to the address conversion tables 4-1 to 4-n, respectively.
2a-n and parity (P) holding units 2b-1 to 2b-n
Consists of

When a logical address is given, the comparators 3-1 to 3-n respectively provide a space number 101 of the logical address holding unit 1 and a space number 104 of the corresponding directory 2.
The address conversion tables 4-1 to 4-n having the same space number as the space number 101 are searched by comparing -1 to 104-n.

The selector 5 includes comparators 3-1 to 3-n
Page numbers 10 read from the address conversion tables 4-1 to 4-n by the page numbers 102 of the logical address holding unit 1 in accordance with the comparison results 106-1 to 106-n of
One of 7-1 to 107-n is selected.

Thus, the page number 108 selected by the selector 5 is held in the physical page number holding section 6a of the physical address holding section 6, and the in-page address 103 of the logical address holding section 1 is held in the in-page address holding section 6b. Will be retained.

Thus, the page numbers of the physical addresses corresponding to the page numbers of the logical addresses of the searched address conversion tables 4-1 to 4-n can be obtained, and the page numbers and page numbers of these physical page number holding sections 6a can be obtained. A physical address is generated based on the in-page address of the internal address holding unit 6b.

For the space number of the directory 2, parity check circuits (PC) 9-1 to 9-n are used.
, A parity check is always performed based on the space numbers 104-1 to 104-n of the directory 2 and the parities 105-1 to 105-n.

[0010]

In the above-mentioned conventional storage access processing device, the parity check circuit constantly checks whether the space number held in the space number holding section of the directory is correct. Is required in large quantities.

SUMMARY OF THE INVENTION An object of the present invention is to provide a storage access processing apparatus which can solve the above problems and can greatly reduce the amount of hardware.

[0012]

A storage access processing apparatus according to the present invention comprises a plurality of address conversion tables for converting a page number of a logical address in one address space into a physical page number of a physical address. It is provided corresponding to each of the plurality of address conversion tables, and at least determines which address space the own table corresponds to.
A plurality of holding means for holding the address space numbers shown, and provided corresponding to each of the plurality of address conversion tables.
And a memory access processing unit and a plurality of comparing means for comparing been an address space number held in said holding means and the address space number where the logical address belongs, according to the plurality of comparing means each comparison result selection means for selecting one of the contents held in the plurality of holding means each Te, checking the health of the selected content held by and said selecting means is provided in common to said plurality of address translation tables each Inspection means.

[0013]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention. In the figure, in one embodiment of the present invention, one of the parities 105-1 to 105-n of the directory 2 is compared with the comparison results 106-1 to 103-1 of the comparators 3-1 to 3-n.
And a parity check circuit (PC) 8 for performing a parity check based on the parity 109 selected by the selector 7 and the space number 101 of the logical address holding unit 1. The configuration is the same as that of the conventional example shown in FIG. 2 except for the provision of. The operations of the same components are the same as those of the conventional example, and the description of the operations will be omitted.

When a logical address is given, the in-page address 103 of the logical address holding unit 1 is held in the in-page address holding unit 6b of the physical address holding unit 6, and is selected by the selector 5 in the physical page number holding unit 6a. The page number 108 is held.

When a physical address is generated by the page number of the physical page number holding unit 6a and the in-page address of the in-page address holding unit 6b, the selector 7
Is the comparison result 106-1 of the comparators 3-1 to 3-n.
Parity 105-1 of directory 2 based on 106-n
One is selected from -105-n.

The parity check circuit 8 performs a parity check based on the space number 101 of the logical address holding unit 1 and the parity 109 selected by the selector 7. Directory 2 that matches the space of the logical address to be accessed
Are the space numbers 109 of the logical address holding unit 1. Therefore, the parity check in the parity check circuit 8 is the same as the parity check based on the space numbers 104-1 to 104-n and the parities 105-1 to 105-n in the directory 2.

Note that the selector 7 uses comparators 3-1 to 3-3.
If one of the space numbers 104-1 to 104-n and the parity 105-1 to 105-n of the directory 2 is selected based on the comparison results 106-1 to 106-n of -n, the parity can be obtained. In the check circuit 8, the space numbers 104-1 to 104-n in the directory 2 and the parity 105-
Parity check based on 1 to 105-n can also be performed.

As described above, the comparators 3-1 to 3-n
Of the directory 2 selected by the selector 7 based on the comparison results 106-1 to 106-n
Parity check is performed by the parity check circuit 8 based on the space number 101 of the directory 2 based on the space number 101 of the directory 2 and the space number 101 of the directory 2.
04-n parity check to address conversion table 4
-1 to 4-n can be performed in common.

Therefore, conventionally, the address conversion table 4-
Since only one parity check circuit provided for each of 1 to 4-n is required, the amount of hardware can be significantly reduced.

[0021]

As described above, according to the present invention, a plurality of comparison means for comparing the address space information of the logical address with the address space information specifying the address space of the own table are used. By selecting one of parity information of address space information corresponding to each address translation table and checking the normality of the address space information based on the parity information, the amount of hardware can be significantly reduced. There is an effect that can be.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a conventional example.

[Explanation of symbols]

 1 Logical Address Holder 1a Space Number Holder 1b Page Number Holder 2 Directory 2a-1 to 2a-n Space Number Holder 2b-1 to 2b-n Parity Holder 3-1 to 3-n Comparator 4-1 4-n address conversion table 5, 7 selector 8 parity check circuit

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-55-105882 (JP, A) JP-A-1-297743 (JP, A) JP-A-3-263252 (JP, A)

Claims (3)

(57) [Claims] 1. A plurality of address conversion tables for converting a page number of a logical address in one address space into a physical page number of a physical address , and provided corresponding to each of the plurality of address conversion tables. At least what address space your table corresponds to
A plurality of holding means for holding the address space numbers shown, and provided corresponding to each of the plurality of address conversion tables.
And a memory access processing unit and a plurality of comparing means for comparing been an address space number held in said holding means and the address space number where the logical address belongs, according to the plurality of comparing means each comparison result selection means for selecting one of the contents held in the plurality of holding means each Te, checking the health of the selected content held by and said selecting means is provided in common to said plurality of address translation tables each A storage access processing device comprising: a check unit. 2. The method according to claim 1, wherein each of the plurality of holding units holds the address space information and parity information for confirming the normality of the address space information. The address space information and parity information held in one of the plurality of holding units are selected accordingly, and the checking unit determines the address space information based on the address space information and parity information selected by the selection unit. 2. The storage access processing device according to claim 1, wherein a normality is checked. 3. The plurality of holding units hold the address space information and parity information for confirming the normality of the address space information, and the selection unit stores a comparison result of each of the plurality of comparison units. And selecting the parity information held in one of the plurality of holding units in accordance with the parity information. The checking unit converts the parity information based on the address space information of the logical address and the parity information selected by the selecting unit. 2. The storage access processing device according to claim 1, further comprising a checking unit that checks the normality of the address space information of the holding unit that holds the data.