JP2637853B2 - Cache memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory device for storing an instruction and data separately, and more particularly to a cache memory device used in an information processing device for processing data rewritten by an instruction as an instruction. It is.

[0002]

2. Description of the Related Art In recent years, in an information processing apparatus, a cache memory device which stores only frequently accessed portions of data and instructions stored in a main storage device and which can access at a higher speed than the main storage device. Often, performance is enhanced by having Furthermore, the cache memory device is often separated into a cache for storing instructions and a cache for storing data so that instructions and data can be accessed simultaneously.

FIG. 5 is a block diagram of an information processing apparatus using a conventional cache memory device. In FIG. 5, 1
Is a data cache having a plurality of entries for storing data, tags, and valid bits V. An instruction cache 2 has a plurality of entries for storing instructions, tags, and valid bits V. Each tag stores an upper part of an address corresponding to data or an instruction. Valid bit V indicates whether the corresponding data or instruction is valid. A control circuit 50 controls the data cache 1 and the instruction cache 2 and requests external access. Reference numeral 4 denotes a CPU (Central Processing Unit) that performs a process specified by an instruction. Reference numerals 5 and 6 denote address translation devices, each of which is an address translation pair 2 for storing a logical address LA and a corresponding physical address PA.
It has a plurality of 0 and 21 and converts a logical address to a physical address. When the CPU 4 reads data by a load instruction, it outputs a logical data address 9, converts the logical data address 9 into a physical data address 10 by an address conversion device 6, and reads an entry in the data cache 1. When the tag of the entry matches the upper part of the physical data address 10 and the valid bit V is 1, that is, when the cache hits, the entry data is transferred to the CPU 4 via the data bus 13. Similarly, in the case of reading an instruction, the logical instruction address 7 is converted into the physical instruction address 8 by the address conversion device 5 and the instruction is read from the instruction cache 2. As described above, by separating the instruction cache 2 and the data cache 1, the instruction and the data can be accessed at the same time and the performance can be improved. However, a problem occurs in the following cases.

There are cases where a plurality of programs stored in an external memory device are combined into one and executed, or a part of the program is modified and executed during execution. When an instruction in a program is moved or rewritten, a load / store instruction is usually used. When a store instruction is used to store an instruction at a new address or rewrite an instruction at a certain address, only the data cache is updated without updating the external memory device. However, when trying to read an instruction for execution, the instruction cache is accessed instead of the data cache. Therefore, there is a problem in that the pre-update instruction already stored in the instruction cache or, if not stored in the instruction cache, the pre-update instruction is erroneously read from the external memory device and executed. To avoid this, conventionally, before reading the moved or updated instruction, the instruction stored in the data cache is written to an external memory device using a special instruction, the instruction cache is invalidated, and the instruction is read as an instruction. In such a case, the latest instruction is always read from the external memory device. The external memory device referred to here refers to a storage device of the second or later hierarchy of the storage device having a hierarchical structure. That is, it is a main storage device, a second-level cache memory device, or the like.

[0005]

In the prior art, all data stored in the data cache is checked, and if the data has been updated, it is written to an external memory device. Interrupted and required a very large number of cycles. Further, by invalidating the entire instruction cache, even the instruction that has not been updated is invalidated, and the instruction is read from the external memory device more than necessary. There was a problem.

The present invention has been made in view of the above circumstances. Even when an instruction is updated by a store instruction, the external memory device can be updated immediately, and only a necessary portion of the instruction cache is invalidated or updated. When trying to read an instruction, by reading the instruction from the data cache or external memory device instead of the instruction cache,
It is an object of the present invention to provide a cache memory device that efficiently processes updated instructions.

[0007]

According to the present invention, there is provided an address selecting circuit for selecting and outputting an instruction address or a data address, and a control circuit.
When a control signal indicating that data to be written is in the instruction area is provided, the address selection circuit selects an address of the data and supplies the selected data to the instruction cache. invalidates the instruction is obtained by such requests the storage of data in the external memory device.

Another means for solving the above problem comprises an instruction cache and a control circuit which can read an instruction by an instruction address, invalidate the instruction by a data address and an invalidation request signal, and write data in an instruction area. given a signal indicating that within the control circuit outputs an invalidation request signal, is obtained so as to request the storage of data in the external memory device.

Still another means includes an address selection circuit for selecting and outputting an instruction address or a data address, and a control circuit. When a control signal indicating that the instruction to be read is in the data area is applied, The address selection circuit selects the address of the instruction and supplies it to the data cache, and the control circuit reads the data in the data cache corresponding to the address of the supplied instruction or requests the external memory device to read the instruction. It was done.

[0010]

According to the present invention, the first or second configuration described above, when an attempt is made to write the data in the instruction region by the store instruction, invalidates the corresponding instruction in the instruction cache, the data in the external memory device When reading updated data as an instruction by writing, since the corresponding instruction in the instruction cache has already been invalidated, the external memory device is accessed and the latest instruction can always be read. .

According to the third configuration, when an instruction updated in the data area is to be read, a correct updated instruction can be read from the data cache or the external memory device.

In any of the first to third configurations, an updated instruction using a store instruction can be read without using a special instruction.

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an information processing apparatus using a cache memory device according to a first embodiment of the present invention. still,
The same parts as those in FIG. 5 are denoted by the same reference numerals, and detailed description thereof will be omitted. In FIG. 1, reference numeral 3a denotes a control circuit which controls the data cache 1 and the instruction cache 2 or requests access to an external memory. The address translation pair 21 of the address translation device 6 has a logical address L
It has an instruction area bit i in addition to A and the physical address PA. When the instruction area bit i is 1, it indicates that the address specified by the logical data address 9 is within the instruction area. An address selection circuit 11 selects a physical data address 10 or a physical instruction address 8 and supplies it to the instruction cache 2. Instruction reading is performed in the same manner as in the conventional example, except that the address selection circuit 11 selects the physical address 8.

A case where data is written in the instruction area will be described. The CPU 4 executes the store instruction, outputs data to be written to the data bus 13, and outputs a logical data address 9 and a write request signal 14. The address translator 6 converts the logical data address 9 into the physical data address 10
Convert to At this time, the address translation used for translation
The instruction area bit i of 1 is 1, and the instruction area access signal 15 is output to indicate that data access is being performed on the instruction area. When the write request signal 14 and the instruction area access signal 15 indicate that the instruction area is to be updated, the address selection circuit 1
1 selects the physical data address 10 and gives it to the instruction cache 2. The control circuit 3a invalidates the instruction by setting the valid bit V of the entry of the instruction cache 2 specified by the selected physical data address to 0, and also disables the instruction of the data cache 1 specified by the physical data address 10. The valid bit V of the entry is set to 0 and invalidated. Further, the control circuit 3a outputs a memory access request 16 to an external memory device such as a main storage device or a secondary cache memory device, and connects the data bus 13 to the address of the external memory device indicated by the physical data address 10. Then, the data given from the CPU 4 is written. Thus, the physical data address 10
Both the entry in the data cache memory and the entry in the instruction cache memory are invalidated, and the external memory device is updated with the data from the CPU 4.

FIG. 2 is a block diagram of an information processing apparatus using a cache memory device according to a second embodiment of the present invention. FIG.
, The instruction cache 2a has a first instruction entry access unit 33 and a second instruction entry access unit 34, and the first instruction entry access unit 33
Accesses the entry of the instruction cache 2a by the physical instruction access 8, and when the instruction invalidation request signal 35 is given, the second instruction entry access means 34 validates the entry of the instruction cache 2a specified by the physical data address 10. By setting bit V to 0, the instruction is invalidated. First instruction entry access means 33 and second instruction entry access means 3
4 can operate independently.

A case where data is written in the instruction area will be described. The CPU 4 executes the store instruction, and executes the write request signal 14 and the instruction area access signal 1 in the same manner as in the first embodiment.
5 indicates that the instruction area is to be updated, the control circuit 3b sends the instruction invalidation request signal 35
To the second instruction entry access means 34 of the instruction cache 2a. The second instruction access unit 34 invalidates the entry of the instruction specified by the physical data address 10 of the data to be written. The control circuit 3
b sets the valid bit V of the entry of the data cache 1 designated by the physical data address 10 to 0, and invalidates the corresponding data. Further, the control circuit 3
b outputs a memory access request 16 to the external memory device and writes the data given from the CPU 4 via the data bus 13 to the address of the external memory device indicated by the physical data address 10. In this way, the entries in the data cache memory and the instruction cache memory specified by the physical data address 10 are both invalidated, and the external memory device is updated with the data from the CPU 4.

As described above, in the first and second embodiments, when the instruction in the instruction area is read and executed after updating the data in the instruction area, the instruction cache always misses. The updated data can be read and executed. Further, in the second embodiment, since the reading of the instruction using the physical instruction address and the invalidation of the instruction using the physical data address can be performed at the same time, the reading of the instruction is not hindered by the invalidation, and the high-speed processing can be performed. it can.

In the first and second embodiments, the control circuits 3a, 3b
Invalidates the entry in the instruction cache 2 specified by the physical data address. In the third embodiment shown in FIG. 3, the write request signal 14 and the instruction area access signal 15 are used to update the instruction area. Control circuit 3c supplies a data write signal 36 to the instruction cache and the CPU 4
3 can be written to an entry of the instruction cache 2 specified by the physical data address. In this case, when the updated instruction is read, the updated instruction is stored in the instruction cache 2, so that the instruction can be read from the instruction cache 2 at high speed.

FIG. 4 is a block diagram of an information processing apparatus using a cache memory device according to a fourth embodiment of the present invention. FIG.
, 3d is a control circuit, and the data cache 1
Or request for access to the control of the instruction cache 2 or an external memory. The address translation pair 22 of the address translation device 5 has a data area bit d in addition to the logical address LA and the physical address PA. Data area bit d
Is 1, it indicates that the address specified by the logical instruction address 7 is within the data area and may be updated by a store instruction. 41 is an address selection circuit, which is a physical data address 10 or a physical instruction address 8
Is given to the data cache 1. For a load / store instruction, the address selection circuit 41 selects the physical data address 10.

A case where an instruction is read from the data area will be described. The CPU 4 outputs a logical instruction address 7 and an instruction request signal 42. The address translator 5 translates the logical instruction address 7 into a physical instruction address 8. At this time, the data area bit d of the address translation pair used for translation is 1, and the data area access signal 43 is output, the instruction is read from the data area, and has already been updated by the store instruction. Indicates a possibility. When the instruction request signal 42 and the data area access signal 43 indicate that an instruction is to be read from the data area, the address selection circuit 41 sets the physical instruction address 8
Is given to the data cache 1. Control circuit 3
“d” inhibits reading of the instruction cache 2 and reads the data cache 1 by the physical instruction address 8 given by the address selection circuit 41. When the data cache 1 hits, the read data is output to the instruction bus 12 by the bus connection means 44 and given to the CPU 4. When the data cache 1 misses, it issues a memory access request 16 to the external memory device, reads an instruction from the external memory storage device, and gives it to the CPU 4 via the instruction bus 12. In this way, even if the data cache has been updated using the store instruction, by specifying the updated area as the data area in advance, the updated data can be read when read as an instruction.

[0022]

As described above, according to the present invention, when an attempt is made to rewrite data in an instruction area using a store instruction with a very simple configuration, a corresponding instruction in the instruction cache is rewritten. disable can update the data in the external memory device. Alternatively, when an instruction in the data area is to be read, the updated instruction can be read from the data cache or the external memory device. Therefore, it is not necessary to transfer data in the data cache to the external memory device or to provide a special instruction for invalidating the instruction cache, and the program can be simplified and the processing can be speeded up. Further, when invalidating the instruction cache, the instruction is invalidated in order to invalidate only the instruction corresponding to the address of the data to be written, whereas conventionally, all instructions in the instruction cache are performed. The missing instruction can be read from the instruction cache at a high speed, and the processing can be speeded up. Since the number of accesses to the external memory device can be reduced,
Other devices can use the external memory device, which can improve the performance of the entire system.

[Brief description of the drawings]

FIG. 1 is a block diagram of an information processing apparatus using a cache memory device according to a first embodiment of the present invention.

FIG. 2 is a block diagram of an information processing apparatus using a cache memory device according to a second embodiment of the present invention.

FIG. 3 is a block diagram of an information processing apparatus using a cache memory device according to a third embodiment of the present invention.

FIG. 4 is a block diagram of an information processing apparatus using a cache memory device according to a fourth embodiment of the present invention.

FIG. 5 is a block diagram using an information processing device using a conventional cache memory device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Data cache 2, 2a ... Instruction cache 3a, 3b, 3c, 3d ... Control circuit 4 ... Central processing unit 5, 6 ... Address converter 7 ... Logical instruction address 8 ... Physical instruction address 9 ... Logical data address 10 ... Physical Data address 11, 41 Address selection circuit 14 Write request signal 15 Command area access signal 16 Memory access signal 41 Command request signal 42 Data area access signal

Claims (6)

(57) [Claims] An instruction cache for storing an instruction, a data cache for storing data, an address selection circuit for selecting an address of data and an address of the instruction and outputting the selected address to the instruction cache, and a control circuit; When a control signal indicating that data to be written is in the instruction area is provided, the address selection circuit selects an address of the data to be written and provides the address to the instruction cache, and the control circuit provides an address from the address selection circuit. it was invalidated instructions of the instruction cache corresponding to the address of the data to be written the cache memory apparatus characterized by being configured to request storage of data to be written the outside portion memory apparatus. 2. When a control signal indicating that data to be written is in an instruction area is supplied, the control circuit invalidates an instruction in an instruction cache corresponding to an address of the data to be written, which is supplied from an address selection circuit. 2. The cache memory device according to claim 1, wherein the data corresponding to the address of the write data in the data cache is invalidated, and the external memory device is requested to store the write data. 3. An instruction cache for storing an instruction, a data cache for storing data, a data address and an instruction address, and
And an address selection circuit for outputting to the decree cache, and a control circuit writes the data given the control signal indicating that the instruction region, the control circuit, the write data supplied from the address selection circuit The data to be written is stored in an instruction cache position specified by an address, data corresponding to the address of the data to be written in the data cache is invalidated, and an external memory device is requested to store the data to be written. It features and be Ruki Yasshumemori device. 4. A control signal indicating that data to be written is in an instruction area is composed of a write request signal and an instruction area access signal. The instruction area access signal is provided by an address conversion device for converting a logical address to a physical address. The cache memory device according to claim 1, wherein the cache memory device is provided. 5. An instruction cache for storing instructions, a data cache for storing data, and a control circuit, wherein the instruction cache has a first access unit and a second access unit, and Access means accesses an instruction in the instruction cache by an instruction address, second access means accesses an instruction in the instruction cache by an address of data, and when an instruction invalidation request signal is given, an address of the data is invalidates the instructions in specified, writing data is applied a control signal indicating that the instruction region, the control circuit outputs the instruction invalidation request signal, the data to be written to an external memory device A cache memory device configured to request storage. 6. An instruction cache for storing instructions, a data cache for storing data, an address selection circuit for selecting an address of data and an address of the instruction and outputting the selected data to the data cache, and a control circuit, When a control signal indicating that the instruction to be read is in the data area is provided, the address selection circuit selects an address of the instruction to be read and supplies the selected address to the data cache. When reading is prohibited and data corresponding to the address of the read instruction provided from the address selection circuit exists in the data cache, data corresponding to the address of the read instruction is read while data in the data cache is read. If not, request the external memory device to read the instruction Cache memory apparatus characterized by being configured urchin.