JP2635988B2 - Digital phase locked loop - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a phase locked loop circuit that generates a signal phase-locked to a digitized input signal.

(Prior Art) An NTSC color television signal is separated into a luminance signal (Y) and a chrominance signal (C) to separate an I signal, a Q signal or an RY signal,
In order to accurately obtain a BY signal or the like, a phase synchronization circuit that generates a signal that is phase-synchronized with the color subcarrier is required.
The phase locked loop includes a method based on analog signal processing and a method based on digital signal processing.

In the method based on analog signal processing, A / A is controlled by a clock having an n-fold frequency synchronized with the color subcarrier of the input television signal.
D / D conversion is performed, and then Y / C separation is performed by digital signal processing. In such a method, it is desirable for the extraction of digital signals having the same phase that the frequency of the sampling clock used for A / D conversion is four times the chrominance subcarrier frequency, and the sampling frequency is limited. Was.

Further, in this method, when separating the color subcarriers, since the amplitude separation method of the synchronization signal cannot be used as in the case of performing the separation of the horizontal synchronization signal, in the input television signal, only the period of the color subcarrier is separated. Requires a circuit to open the gate, and the separation circuit has a complicated circuit configuration.
Since such a complicated circuit must be constituted by an analog circuit, there is a disadvantage that the circuit is likely to be unstable.

As a method based on digital signal processing, there is a method of generating the same data as the input signal using a clock having the same frequency as the sampling frequency for A / D converting the input signal.

In this type of conventional method, data is stored in a form in which a signal having the same waveform as the input signal is sampled at a frequency sufficiently m times higher than the clock, and a phase corresponding to a sampling period of the data is stored. A memory address signal is generated and read every time.

In general, since the repetition frequency of the input signal and the sampling frequency do not have a positive ratio, a ROM is used as a means (phase generation circuit) for generating the read address signal, and the contents of the ROM are read. By setting the value to a predetermined value, the portion that does not become a positive number ratio is represented by an approximate value. FIG. 3 is a block diagram of a phase generating circuit using such a ROM. The sampling clock is counted by a counter 31, and the count value is used as an address of the ROM 32, and the phase information 33 of the carrier at the sampling time is read from the ROM 32.
Occurs.

As described above, in the conventional method, the ROM is also used as a means for generating the read address signal, so that the memory capacity becomes extremely large.
There was a disadvantage that it was difficult to enter the chip.

(Object of the Invention) An object of the present invention is to provide a phase-locked loop circuit which solves the above-mentioned conventional drawbacks and solves the limitation of the sampling frequency, the instability of the circuit, and the miniaturization of the circuit. It is.

(Structure of the Invention) (Difference between Features of the Invention and Conventional Technique) The present invention keeps a basic address signal (that is, phase information) input to generate a signal having the same waveform as an input signal constant for each sampling clock. The most important feature is that it is generated by a circuit that accumulates the values of. In the related art, the address signal is generated using a ROM, whereas in the present invention, the address signal is generated by a logic circuit.

(Embodiment) FIG. 1 is a block diagram showing an embodiment of the present invention.
In the figure, 1 is an NTSC signal input terminal, 2 is a synchronization separation circuit, 3 is a clock generation circuit, 4 is an A / D conversion circuit, and 5 is Y / C
Separation circuit, 6 is a color signal demodulation circuit, 50 is a Y signal output terminal,
Reference numeral 51 denotes a C1 signal output terminal, 52 denotes a C2 signal output terminal, and 100 denotes a phase-locked loop that is an object of the present invention. In this phase synchronization circuit, 101 is a phase comparison circuit, 102 is a signal generation circuit, 103
Is a synchronization signal output terminal, 104 is a phase generation circuit, 105 is a phase correction circuit, and 106 is a phase correction amount determination circuit.

Next, the operation will be described. The NTSC color television signal input from the NTSC signal input terminal 1 is separated into a horizontal synchronizing signal in a synchronizing separation circuit 2, and a sampling clock (T) synchronized in phase with the horizontal synchronizing signal is clocked. The sampling clock (T) generated by the generation circuit 3
Are supplied to various necessary circuits.

The input NTSC color television signal is also supplied to an A / D conversion circuit 4, where the signal is converted from an analog signal to a digital signal.

The NTSC signal format is such that a carrier chrominance signal component obtained by modulating a color subcarrier with a chrominance signal is frequency-multiplexed in the high frequency region of the luminance signal Y. Therefore, the luminance signal Y and the carrier chrominance signal C
Need to separate Y / C in order to process independently.

Therefore, the output signal of the A / D conversion circuit is separated into a luminance signal Y and a carrier chrominance signal C in a Y / C separation circuit 5, and the luminance signal Y
Is supplied to the Y signal output terminal 50, and the carrier color signal is supplied to the color signal demodulation circuit 6.
Is output to

The color signal demodulation circuit 6 demodulates the two color signals C1 and C2. At this time, it is necessary to generate a signal in phase with the color subcarrier of the input NTSC signal for demodulation. It is the phase locked loop 100 that generates this signal.

The phase synchronization circuit 100 focuses on only the color subcarrier in the digitized NTSC signal output from the A / D conversion circuit 4 and compares the phase of the color subcarrier with the output of the signal generation circuit 102. The comparison is performed in the circuit 101, and the phase correction amount determination circuit 106 determines a phase correction amount for phase synchronization.

The configurations of the phase comparison circuit 101 and the phase correction amount determination circuit 106 can be realized by an existing method. For example, for the color subcarrier SIN θ of the input NTSC signal, the signal generation circuit 102
+ Φ) and COS (θ + φ), and SIN θ · SIN (θ + φ) and SIN θ · COS (θ + φ) in the phase comparator 101.
Is calculated. Then, the phase correction amount determination circuit 106 operates so that φ = 0. That is, when φ = 0, SIN ² θ =
Since the maximum value is reached and SINθ · COSθ = 0, the phase correction amount determination circuit 106 operates to satisfy this condition.

The signal generation circuit 102 basically generates the SIN at the phase of each sampling clock (T) based on the output of the phase generation circuit 104.
It generates the value of θ · COSθ, but operates according to the phase corrected by the value supported by the phase correction amount determination circuit 106 with respect to the output of the phase generation circuit 104, that is, the output of the phase correction circuit 105.

Next, the basic operation principle of the phase generation circuit 104, which is a feature of the present invention, will be described. As an example, a case where the sampling frequency is 13.5 MHz which is a standard in a studio will be described.

FIG. 2 is a diagram showing the basic relationship between the color subcarrier and the phase of each sampling point. Since the frequency f _SC of the chrominance subcarrier shown in FIG. 1A has a relationship of f _SC = 455/2 · f _{H with} respect to the horizontal synchronization frequency f _H of the television signal, the scanning is performed as shown in FIG. There will be 455 cycles per line 2 lines. Also, 13.5M
In the case of Hz sampling, there are 1716 samples per two lines as shown in FIG. Accordingly, the period 1 / f _SC of the input repetitive waveform is divided by M, and the period of the sampling clock in which the input repetitive waveform is sampled, that is, one sample interval is divided by N, and 455M = 1716N is satisfied (M, N). Use a combination of That is, the phase is expressed for each 1 / M of one cycle of the color subcarrier. And
The phase generation circuit 104 accumulates 2π × N / M for each sample, that is, for each 13.5 MHz sampling clock, and outputs the accumulation result as the output of the phase generation circuit 104. Thus, a signal from the output of the phase generation circuit 104 to the input of the signal generation circuit 102 is a log ₂ M (bit) signal.

FIG. 4 shows a configuration example of the phase generation circuit 104.
For each sampling clock, the adder 42 adds the output value of the register 41 indicating the carrier phase at the time of the immediately preceding sampling clock and the constant N / M, sets the result in the register 41, and sets the carrier in the next sampling clock transfer. The phase is 43. In the example of FIG. 2 described above, M and N satisfy 455M = 1716N, and the constant N / M has a value of 455/1716.
.. = 0.2651... Is a value represented by the number of bits of the time required precision of the carrier wave phase. With the configuration of FIG. 4, the ROM of FIG.
A carrier phase sequence similar to the output can be generated.

(Effect of the Invention) As described above, according to the present invention, the phase generation circuit 104 is configured by a logic circuit that simply accumulates a predetermined value without using a large-capacity memory. There are advantages that can be done. In particular, when implementing an LSI, a large capacity memory is required in the signal generation circuit 102 and the like. Therefore, when the phase generation circuit 104 is also configured with a memory, the memory capacity becomes too large, and it is difficult to realize it with one chip. On the other hand, as a result of reducing the memory capacity, there is an advantage that the possibility of realizing the LSI is increased.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing a basic relationship between a basic phase of a chrominance subcarrier and each sampling point, FIG. 3 is a diagram showing a conventional phase generating circuit, FIG. 4 is a diagram showing a phase generating circuit according to the present invention. 1 ... NTSC signal input terminal, 2 ... Sync separation circuit, 3 ...
Clock generation circuit, 4 ... A / D conversion circuit, 5 ... Y / C separation circuit, 6 ... Color signal demodulation circuit, 50 ... Y signal output terminal,
51 ... C1 signal output terminal, 52 ... C2 signal output terminal, 100 ...
... Phase synchronization circuit, 101 ... Phase comparison circuit, 102 ... Signal generation circuit, 103 ... Synchronization signal output terminal, 104 ... Phase generation circuit, 105 ... Phase correction circuit, 106 ... Phase correction amount determination circuit .

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Tetsuo Tajiri 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation (72) Inventor Kazutoshi Yanaka 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation (72) Inventor Toshiyuki Takahashi 1-6-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation (56) References JP-A-58-88905 (JP, A)

Claims (1)

(57) [Claims] 1. An input signal sequence including a repetitive waveform,
In a digital phase-locked loop circuit that generates a signal synchronized with the phase of the waveform of the repetition portion, the period of the input repetition waveform is divided into M, the period of the sampling clock in which the input repetition waveform is sampled is divided by N, When the sampling clock is T, the sampling data corresponding to the input repetitive waveform is stored for each phase of 2π × 1 / M, and this is stored as 2π × N / M × T phase data for each sampling clock. And a phase generating circuit for generating a basic address signal of the signal generating circuit. The basic address signal of the phase generating circuit is changed to 2π × N / M every time the sampling clock T increases by one. A digital phase-locked loop characterized in that the digital phase-locked loop is configured to accumulate by one and output the accumulation result.