JP2635306B2 - Image processing device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to first and second different color images according to characteristics of a color image represented by a plurality of input color component signals.
The present invention relates to an image processing apparatus that selectively outputs a plurality of color component signals having resolutions of.

[Prior Art] Conventionally, this type of image processing apparatus clearly expresses line drawings such as characters, expresses continuous tone images such as photographs with good gradation, and displays halftone images such as printed photographs. An image in which gradation is expressed by an area change of dots or lines, etc., with good gradation
Moreover, the purpose is to express the image without causing image quality deterioration such as moiré. The image processing method proposed to achieve such an object has been reported in literatures such as IE83-67 "Dotding of mixed text and photograph images", etc. I have. However, according to the conventional methods disclosed in these reports, for example, a dither method and a density pattern method are used in accordance with the type of an input image in order to convert an input image signal into a signal having a dot arrangement used in digital printing. Since processing such as conversion of the processing method is necessary, such as using differently, there is a drawback that the algorithm is considerably complicated.

Therefore, in order to eliminate this drawback, the present applicant uses an input system having a low resolution in addition to a high input system having a high resolution, and cuts a low frequency component into an input signal from the input system having a low resolution. Perform high-pass filtering,
Based on the result, an area determination is made as to whether the input signal belongs to the character / line drawing area or the photographic halftone area, and based on the result of the area determination, the input signal from the high-resolution input system and the low-resolution input system are used. An image localization device which selects any one of the input signals and uses it as an output signal is proposed. According to this apparatus, image quality degradation such as moire when a halftone dot document is used as an input image and particle noise of a photo document are eliminated by a relatively simple algorithm, and the edges of characters and photos are clearly output. be able to.

However, if the image processing method used in the above-described proposed apparatus is applied to the input signal of color image data as it is, it is necessary to repeat the processing by the number of color separations or to perform the processing in parallel. The disadvantage is that the number of circuits is increased or otherwise the processing time is increased.

[Purpose] The present invention eliminates the above-mentioned drawbacks, and can determine the characteristics of a color image represented by a plurality of input color component signals with a simple circuit scale and with high accuracy, thereby providing a good output color. It is an object to provide an image processing device capable of obtaining image data.

Examples Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 shows the configuration of an embodiment of the present invention. Where 11,12
Reference numerals 13 and 13 denote buffer memories for storing data r ', g' and b 'for each of the color-separated colors inputted from the blur input system having a resolution lower than a specific set value. Reference numeral 14 denotes a determination signal generation circuit, and the buffer memories 11, 1
From the data r _i , g _i, and b _{i of} each color obtained from 2 and 13, a signal f for making a region judgment is generated. Fifteen
Is an edge detection circuit that applies a high-pass filter to the determination signal f to cut low-frequency components. Reference numeral 16 denotes an area determination circuit, which determines whether an area belongs to an edge area or a non-edge area, that is, a text line image or a photograph, using an edge signal h which is an output signal of the edge detection circuit 15. 17, 18, and 19 are signal selection circuits, respectively.
The output signal i _r on the basis of the area signal i output from the area determining circuit 16, i _g, data from the high resolution input system as i _b r, g, _b
And data r ″, g ″, and b ″ from the low-resolution input system are selected and output.

The above-described r, g, and b are image data input from an input system (not shown) having high resolution after being color-separated through corresponding red, green, and blue filters, respectively. That is, r
Is red, g is green, and b is blue image data. Also,
r ', g', and b 'are image data input from an input system (not shown) having a resolution lower than a specific set value after being color-separated through corresponding red, green, and blue filters, respectively. .

Input image data r ', g', b 'from low-resolution input system
Are temporarily stored in the corresponding buffer memories 11, 12, and 13. In parallel with this, the image data r _i , g _i , b _i required in the subsequent determination signal generation circuit 14 are stored in the buffer memories 11, 12,
Read from 13. The image data r _i , g _i , and b _i for each color are input to the determination signal generation circuit 14, which outputs a determination signal f to be used in the subsequent area determination operation.
The determination signal f is input to the edge detection circuit 15 and its low-frequency components are cut off to become edge signals h of only high-frequency components corresponding to edges in the image. The edge signal h is input to the area determination circuit 16, which outputs an area signal i for dividing the edge area and the non-edge area. The area signal i is input to signal selection circuits 17, 18 and 19, and based on the area signal i, the input signal data r, g, b from the high-definition input system having the high resolution and the buffer Image data r ″ obtained from the memories 11, 12, and 13,
One of g ″ and b ″ is selected to be output signals i _r , i _g and i _b .

FIG. 2 (A) shows an example of the input resolution of the high-definition input system having the above-mentioned high resolution, and FIG. 2 (B) shows an example of the input resolution of the above-mentioned low-resolution blur input system. Here, the upper limit of the resolution of a low-resolution input system is, for example, 50 lines / i.
The frequency is set so as to be the frequency of the basic lattice of an nch halftone original or the basic lattice frequency of a halftone original of 75 lines / inch.

FIG. 3 shows an example of the configuration of the above-described determination signal generation circuit 14. As shown in the figure, for image data r _i , g _i , b _i sent from buffer memories 11, 12, 13, weight coefficients a _r , a _g , a _b set for each color are set. Each multiplier 31, 32, 33
, And the result of the multiplication is added by the adder 34.
The result of the addition is output as a determination signal f. This conversion equation is represented by the following equation (1).

f = a _r · r _i + a _g · g _i + a _b · b _i (1) FIG. 4 shows another configuration example of the above-described determination signal generation circuit 14. In the case of FIG. 4, one of the data r _i , g _i , b _i output from the buffer memories 11, 12, 13 is selected by the switch 41 and output as the determination signal f.

FIG. 5 shows an example of a coefficient matrix M (i, j) used in the edge detection circuit 15 described above. Here, the center of the coefficient matrix M (i, j) is set to (2a + 1) × (2a + 1) with the size of the (0,0) matrix, and the determination signal f is converted to a two-dimensional array f ( i, j) (see FIG. 6), the edge detection circuit 1
The edge signal h (i, j) which is the output of 5 is f ′ of the following equation (2).
It is given by the absolute value of (i, j).

In the edge detection circuit 15, M (i, j)
In the coefficient matrix having the element “0”, the calculation of the above equation (2) is not performed, and the calculation of the above equation (2) is performed only on the part where the element is not “0”. FIG. 7 shows an example of this calculation processing.

FIG. 8 (A) shows a waveform obtained by cutting the determination signal f (see FIG. 6) along the one-dimensional X coordinate direction, and FIG. 8 (B) shows the waveform data of FIG. 8 (A). 8 (C) shows a waveform corresponding to f '(i, j) calculated by the above equation (2), and FIG. 8 (C) shows an edge signal h obtained by taking the absolute value of the waveform of FIG. 8 (B). 3 shows the waveforms of FIG.

FIG. 8 (D) shows a signal h 'obtained by binarizing the above-mentioned edge signal h with a specific first threshold value S1, and FIG. 8 (E).
FIG. 8F shows a signal h ″ obtained by adding the signal h ′ of FIG. 6D by a predetermined range, and FIG.
An area signal i obtained by binarizing the signal h ″ in FIG. 9E with a specific second threshold value S2 is shown.

In the area determination circuit 16 shown in FIG. 1, the edge signal h is subjected to threshold processing at a specific threshold S1, and n × n pixels near the pixel to be determined are determined.
The number of pixel data h 'in which the edge signal h is equal to or larger than the threshold value S1 in the square area of the pixel is calculated. Assuming that the result of the threshold processing is “1” and “0”, the coefficient is the same as adding the signal after the threshold processing in the above-described square area, and as a result, FIG. A signal h "as shown in the figure is obtained. In addition, the area determination circuit 16 compares the signal h", which is the result of the counting, with a specific threshold value S2 by two.
It outputs a region signal i as shown in FIG. 8 (F).

FIG. 9 shows an example of the configuration of the area determination circuit 16 described above.
Here, reference numeral 50 denotes a comparator, which compares the edge signal h with a specific threshold value S1 as shown in FIG. 8 (D). If the signal h is larger than the threshold value S1, it is set to "1". 0 "
A 1-bit (bit) binarized edge candidate point signal h 'is output.

Reference numeral 51 denotes a random access memory (RAM) for storing the edge candidate point signal h 'for a plurality of lines. Figure 10 shows this R
The address space in AM51 is shown. The RAM 51 has a size corresponding to n pixels, which is a size in the Y direction of a block described later in the Y direction, and reduces the amount of memory by using a remainder obtained by dividing the Y address by n as a physical address. Figure 11 shows RAM51
An example of the storage state of the middle edge candidate point h 'is shown. Although it is physically a memory for n lines, it is illustrated here as a memory for the number of lines for the entire screen. For the data in the RAM 51 shown in FIG. 11, a rectangular block of nxm pixels (shown by a broken line) or a square block of nxn pixels is determined at the time of reading. This block is moved one pixel at a time by the read address control.

Reference numeral 52 denotes a counter for counting the number of edge candidate points (that is, pixels for which the edge candidate point signal h 'is "1") in the block. That is, the counter 52 counts the number of pixels h 'in which the edge signal h is equal to or more than the predetermined threshold value in the block indicated by the broken line in FIG. 11, but in this case, the number is 2 pixels. FIG. 8E shows the result of counting while moving the block only in the i direction.

53 compares the edge number signal h ″ output from the counter 52 with a specific threshold value S2, as shown in FIG.
This is a comparator that outputs a coded area signal i.

A Y address counter 54 outputs a Y address signal YADR for supporting a write / read Y address of the RAM 51, and a subtraction 55 outputs an X address signal XADR indicating a write / read X address of the RAM 52. It is a vessel. An X address counter 56 counts the first clock signal CK1 and outputs the count value to the subtractor 55. 57 is an offset count, which is cleared by the first clock signal CK1, counts the second clock signal CK2, outputs the count value to the subtractor 55, and when the offset value is reached, the carry signal is OR gated. Output to 58 and becomes zero. The OR gate 58 is connected to the horizontal synchronizing signal Hsyn.
The logical sum of c and the carry signal of the offset counter 57 is calculated, and the result is output to the Y address counter 54.

Next, the operation of the area determination circuit 16 in FIG. 9 will be described in further detail using an example in which the above-described block is formed of 5 × 5 pixels. First, the X address counter 56 is increased by "1" by the clock CK1 from a signal generator (not shown), the offset counter 57 is cleared, and the counter 52 is cleared. Next, the edge signal h, which is the input signal, is compared with a predetermined threshold value S1 by the comparator 50 to become a 1-bit edge candidate point signal h '. Further, in the subtracter 55, the content of the offset counter 57 is subtracted from the content of the X address counter 56, and the result becomes the X address signal XADR. At first, since the content of the offset counter 57 is “0”, the X address signal XADR becomes X
It is equal to the contents of the address counter 56. On the other hand, the Y address counter 54 is a counter which increases by "1" according to the result of the logical sum of the horizontal synchronization signal Hync and the carry signal from the offset count 57, and the count content is the Y address signal.
Output as YADR. Since the Y address counter is an n-ary counter determined by the block size, it returns to the original address after counting the entire block.

Next, the above-mentioned edge candidate point signal h 'output from the comparator 50 is used for the X address signal XADR and the X address signal.
YADR is written to the RAM 51 as a write address.
Subsequently, the edge candidate point signal h 'input at this time is "1".
If the signal h 'is "0", the counter 52 increments by "1", and if the signal h' is "0", the counter 52 retains the same value (in this case,
“0”) is retained.

Thereafter, the following operation is repeated based on generation of second clock signal CK2. That is, the clock signal CK2
As a result, the offset counter 57 increases, whereby the X address signal XADR output from the subtractor 55 decreases by "1". This X address signal XADR and the above-mentioned Y address signal YA
With DR as a read address, the previously input edge candidate point signal h 'is read from the RAM 51. The counter 52 increases the count value by "1" if the read edge candidate point signal h 'is "1", and holds the value as it is if it is "0". The Y address counter 54 is a quinary counter to make the block 5 × 5 pixels. Therefore, the offset counter 57 generates a carry signal and becomes “0” by the clock signal CK2 after the above operation is repeated four times. In addition,
The clock signal CK2 is 5 minutes of the clock signal CK1.

The carry signal of the offset counter 57 is input to the Y address counter 54, and the Y address counter 54 increases by "1". As a result, the Y address signal YADR increased by “1” and the X address signal XADR returned to the contents of the X address counter 56 are used as read addresses in the RAM 5.
The edge candidate point signal h 'is read from 1 and the counter 52
Increases the contents of the count or holds the data in accordance with the value of the signal h ', similarly to the above-described operation.

Here, the Y address of the RAM 51 is five lines from "0" to "4", as shown in FIG. 10, and the Y address counter 54 is a quinary counter. The edge candidate point signal h 'corresponding to all the pixels in the block of 5 * 5 pixels indicated by the broken line in FIG.
It is read from 1 and the number of candidate edge points in the same block is counted by the counter 52. The content of the counter 52 at this time is output to the comparator 53 as an edge number signal h ″, and the comparator 53 compares the predetermined edge number signal h ″ with the threshold value S2 to output an area signal i (eighth signal). Figures (E) and (F). a At this time, since the Y address counter 54 is a quinary counter, it is incremented five times in the above-described process, and has the same contents as when the clock CK1 was input first.

The above-described area signal i output from the area determination circuit 16 in this manner is input to the signal selection circuits 17, 18, and 19 in FIG. In the signal selection circuits 17, 18, and 19, if the eight-region signal i is an edge region where the signal is "1", the image data r, g, b from the high-definition input system is selected and the output signals i _r , _ig , i _b And if the area signal i is a non-edge area of “0”, the blur input system data r ″, g ″, b ″ to be input from the blur input system through the buffer memories 11, 12, 13 are selected and output signals are output. i _r , i _g , i _b
Output as

As a result, the output signals i _r , i _g , and i _b obtained by the apparatus of the present invention become blurred input type color image data r ″, g ″, b ″ with respect to a halftone dot input document or a background image of a character. High-definition input color image data r, g,
b, so there is no image quality degradation such as moiré caused by halftone dots even during multicolor digital printing that performs processing such as dithering, and without blurring characters or edges in images. It can output clearly.

In the embodiment of the present invention described above, the input image signal is set to red, green,
Although described as the image data that has been color-separated by a blue filter, a color signal composed of a combination of an intensity signal and a color difference signal, such as used in a color TV, can be applied as the input image signal. In this case, the area determination can be performed using the intensity signal (white / black) signal as the determination signal f shown in FIG. In the field of printing and the like, a color image signal is composed of color-specific data indicating Y (yellow), M (magenta), C (cyan), and K (black).
Region determination can also be performed using data or M data as the determination signal f.

[Effects] As described above, according to the present invention, it is possible to determine the characteristics of a color image represented by a plurality of input color component signals with a simple circuit scale and with high accuracy.
A remarkable effect that good output color image data can be obtained is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of the configuration of the color image processing apparatus of the present invention. FIG. 2A is a characteristic diagram showing an example of an input resolution of an input system having a higher resolution than a specific set value. FIG. 3B is a characteristic diagram showing an example of an input resolution of an input system having a lower resolution than a specific set value. FIG. 3 is a block diagram showing an example of the configuration of the determination signal generation circuit 14 in FIG. 5 is a block diagram showing another example of the configuration of the determination signal generation circuit 14 in FIG. 1. FIG. 5 is a coefficient matrix M used in the edge detection circuit 15 in FIG.
FIG. 6 is a diagram showing an example of the determination signal f, FIG. 7 is an explanatory diagram for explaining the operation of the edge detection circuit 15 in FIG. 1, and FIG. (A) is a waveform diagram showing an example of the determination signal f, FIG. 8 (B) is a waveform diagram showing an example of a signal f ′ obtained by high-pass filtering the determination signal f, and FIG. 8 (C). Is a waveform diagram showing an example of the edge signal h in FIG. 1 obtained by converting the signal f 'in FIG. 8 (B) into an absolute value, and FIG. 8 (D) processes the edge signal h with a predetermined threshold value S1. FIG. 8 (E) is a waveform diagram showing an example of a signal h ″ obtained by adding the threshold-processed signal h ′ within a predetermined block range, and FIG. 8 (F). 9) is a waveform diagram showing an example of the area signal i, FIG. 9 is a block diagram showing an example of the configuration of the area determination circuit 16 in FIG. 1, and FIG. 10 is a data diagram of the RAM 51 in FIG. 11 is an explanatory diagram showing an example of a data storage state of the RAM 51. 11, 12, 13... Buffer memory, 14... A determination signal generation circuit, 15... Edge detection Circuit, 16 ... Area judgment circuit, 17,18,19 ... Signal selection circuit.

Claims (1)

(57) [Claims] 1. A method according to claim 1, wherein said first and second different color image signals are represented by a plurality of color component signals.
An image processing apparatus for selectively outputting a plurality of color component signals having a resolution of: multiplying each of the plurality of input color component signals by a weight coefficient set for each color component, A determination signal generating unit that outputs a signal for determining a feature of the color image by adding a result; an edge detection unit that extracts an edge signal of the color image based on the determination signal; Based on the characteristic of the color image, and using the result of the determination in common for each color component signal, selectively outputting a plurality of color component signals having the first and second resolutions different from each other. An image processing apparatus comprising: