JP2634861B2 - Current sense amplifier circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a current sense amplifier circuit, and more particularly to a current sense amplifier circuit used for a semiconductor memory device.

[Prior Art] Normally, a current sense amplifier circuit is used for an output unit that senses a small current flowing in a semiconductor storage unit in a semiconductor storage device, and a small current flows or does not flow depending on information stored in the semiconductor storage unit. It is for recognizing this and electrically outputting a high level or a low level.

FIG. 3 is a circuit diagram of a conventional example of a current sense amplifier circuit, and FIG. 4 is a circuit diagram of the conventional current sense amplifier circuit of FIG.
FIG. 5 is an operation waveform diagram when a place where a memory cell is present in a semiconductor memory is selected. FIG. 5 is an operation waveform when a place where a memory cell is not present in a semiconductor memory is selected in the conventional current sense amplifier circuit of FIG. FIG.

This current sense amplifier circuit, as shown in FIG.
The drain side C (hereinafter, referred to as a digit line C) of the N-channel transistor 7 of the semiconductor memory unit and the digit line C
N-channel transistor 5 serially connected to
(Hereinafter referred to as a Y selector 5) are connected to the drain B of the P-channel transistors 1 and 2, which constitute a current mirror circuit, a complementary inverter 8, and an output signal of the complementary inverter 8 which constitute a current mirror circuit. As a gate electrode input signal, the source electrode is connected to the input side of the complementary inverter 8 and the digit line C, and the drain electrode is connected to the drain electrode of the P-channel transistor 1.
It comprises an N-channel transistor 4 constituting a ratio inverter with the channel transistor 3 and the P-channel transistor 2.

When a high level is input to the input terminals A1 and A3, the N-channel transistor 7 in the semiconductor memory is selected,
The operating state of the channel transistor 7 and the Y selector 5 are also in the operating state, and the operation of each connection point is such that the level of the connection point B is set to the parasitic capacitance 9 of the digit line C as shown in FIG.
Is instantaneously reduced to a low level in order to charge the data, and the drain B of the Y selector 5 is at a low level because the N-channel transistor is still operating after the charging of the parasitic capacitance 9 of the digit line C is completed. Also, the level of the connection point A falls to the low level during the charging period of the parasitic capacitance 9 of the digit line C so as to follow the level of the connection point B, and remains at the low level even after the charging is completed, so that the P-channel transistors 1 and 2 operate. State. Normally, the level of the connection point D changes depending on the ratio of the transconductance of the P-channel transistor 2 (hereinafter, g _mp ) and the transconductance of the N-channel transistor 4 (hereinafter, g _mN ). When g _mp > g _mN , By designing the level of the connection point D to be a high level, when the P-channel transistor 2 is in the operating state as described above, g _mp > g _mN and the connection point D outputs a high level.

When a high level is input to the input terminals A1 and A2, 6 having no N-channel transistor in the semiconductor memory is selected, the Y selector 5 is activated, and the operation of each connection point is connected as shown in FIG. The level of point B is digit line C
In order to charge the parasitic capacitance 9 of the digit line C, the potential drops momentarily to a low level, and after the charging of the parasitic capacitance 9 of the digit line C is completed, it goes to a high level. Also, the level of the connection point A falls to a low level during the charging period of the parasitic capacitance 9 of the digit line C so as to follow the level of the connection point B, and after the completion of the charging, it becomes a high level, and the P-channel transistors 1, 2 , The mutual conductance becomes worse, g _mp <g _mN , and the level at the connection point D becomes low.

[Problems to be Solved by the Invention] In the conventional current sense amplifier circuit described above, when a place where an N-channel transistor (hereinafter, a memory cell) is not provided in a semiconductor storage unit is selected, the parasitic capacitance of a digit line is charged for a moment. The output of the current sense amplifier circuit is at a high level, a high level is output during the charging of the parasitic capacitance of the digit line, and after the charging is completed, the current sense amplifier circuit outputs a normal low level. _Has a disadvantage that the access time (T _{AC2 in} FIG. 5) of the N channel transistor 3 is long, and the level of the gate of the N channel transistor 3 is near the intermediate level between the power supply potential and the ground potential. And the current for charging the parasitic capacitance 9 of the digit line C is small, and the current mirror circuit Since the gate voltages of the P-channel transistors 1 and 2 are [the power supply potential− (the threshold level of the P-channel transistor)], the transconductance of the P-channel transistor 1 is poor and the parasitic capacitance 9 of the digit line C is charged. However, there is a disadvantage that the current is small and the access time is long.

An object of the present invention is to provide a current sense amplifier circuit which can mitigate the above-mentioned drawbacks and can speed up the access time.

[Means for Solving the Problems] A current sense amplifier circuit according to the present invention comprises a complementary inverter, a drain side connected to an output side of the complementary inverter,
A first P-channel transistor for inputting a pulse signal; a first N-channel transistor having an output signal of the complementary inverter as a gate electrode input signal and a source connected to the input side of the complementary inverter and a digit line; A current mirror circuit including a P-channel transistor connected to the drain electrode of the channel transistor; and a second P-channel transistor having a drain connected to the gate electrode of the P-channel transistor of the current mirror circuit and receiving the pulse signal at the gate electrode. A channel transistor and a P-channel transistor of the current mirror circuit include a second N-channel transistor that forms a ratio inverter.

[Operation] Since the level of the gate of the first N-channel transistor is high while the pulse signal is at the low level, the transconductance of the first N-channel transistor is improved, and The flowing current increases and the time for charging the parasitic capacitance of the digit line decreases, and the second P-channel transistor also operates while the pulse signal is at a low level. In this state, since the gate level of the second P-channel transistor is low, the transconductance is good, the current flowing into the digit line increases, and the time for charging the parasitic capacitance of the digit line decreases.

Similarly, when the location where the memory cell of the semiconductor memory section is present is selected, when the pulse signal is momentarily set to the low level,
When the parasitic capacitance of the digit line is rapidly charged and the pulse signal changes from low level to high level, the memory cell is in the operating state, so the digit line immediately drops to low level and the current sense amplifier circuit The output goes high.

Example Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of a current sense amplifier circuit according to the present invention, and FIG. 2 is a waveform showing an operation of each connection point of the present embodiment when a portion having no memory cell in a semiconductor memory section is selected. FIG. In FIG. 2, the dotted line shows the operation of the conventional current sense amplifier circuit, and the solid line shows the operation of the present embodiment.

This embodiment is different from the conventional example shown in FIG. 3 in that a P-channel in which a pulse signal is input, the drain side is connected to the output terminal of the complementary inverter 8, and the gate electrode is connected to the input terminal IN. Transistor 10 and P-channel transistors 1 and 2 forming a current mirror circuit
The gate electrode is connected to the drain, and the P-channel transistor 11 whose gate electrode is connected to the input terminal IN is added.

Transconductance of P-channel transistors 2 (hereinafter, g _mp1)> transconductance of N-channel transistor 4 (hereinafter, g _MN1) when the level of the connection point D is high level is output, when g _mp1 <g _MN1, The connection point D outputs a low level.

Next, the operation of the current sense amplifier circuit of this embodiment is described in the second.
This will be described with reference to the timing chart in FIG.

At the same time as the input signal A1 changes from the low level to the high level, the input signal IN is momentarily set to the low level. input signal
While IN is at the low level, the output signal at the output terminal E of the complementary inverter 8 is output at the high level because the P-channel transistor 10 is in operation, and is input to the gate of the N-channel transistor 3. The level of the gate of the N-channel transistor 3 of the conventional current sense amplifier circuit is an intermediate level between the power supply potential and the ground potential, but the level of the gate of the N-channel transistor 3 of the current sense amplifier circuit of the present embodiment is the input signal IN. Is at a high level during the low level period, the transconductance of the N-channel transistor 3 is improved, the current flowing through the N-channel transistor 3 is increased, and the time for charging the parasitic capacitance 9 of the digit line C is shortened. , P
The channel transistor 11 also operates during the period when the input signal IN is at the low level. Since the gate level of the P-channel transistor 1 of the conventional current sense amplifier circuit operates at a level close to [power supply potential- (threshold level of the P-channel transistor)], the mutual conductance of the P-channel transistor 11 is poor. The P-channel transistor 11 of this embodiment is in the operating state when the pulse signal IN is at a low level. In this state, since the gate level of the P-channel transistor 11 is low, the transconductance is good, the current 12 flowing into the digit line becomes large, and the parasitic capacitance 9 of the digit line C becomes large.
The time to charge becomes shorter. That is, when the input signal A1 changes from the low level to the high level, the connection points A and B momentarily decrease to the low level. However, since the charging of the parasitic capacitance 9 of the digit line C is performed quickly, the connection points A and B B becomes faster high level, also, the mutual conductance of the P-channel transistors 1 and 2 are poor, g _mp1 of P-channel transistors 2 <N-channel transistor 4 g _MN1
Therefore, a low level is output as the output D. Also,
Similarly, when the memory cell of the semiconductor memory section is selected, when the input signal IN is temporarily set to the low level, the parasitic capacitance 9 of the digit line C is quickly charged, and the input signal IN is changed from the low level to the high level. At this time, since the memory cell is in the operating state, the digit line C immediately drops to the low level, and the output D of the current sense amplifier circuit goes to the high level.

The input signal IN shown in FIG. 1 can be used as an input signal IN by detecting a rising edge of a gate signal of the Y selector 6 and generating a one-shot pulse in addition to inputting a pulse signal from the outside. Although the semiconductor memory unit uses horizontally stacked memory cells of N-channel transistors, the same effect can be obtained with a P-ROM semiconductor memory cell, which is effective for all semiconductor memory cells.

[Effects of the Invention] As described above, the present invention is achieved by adding first and second P-channel transistors to a current sense amplifier circuit of a semiconductor integrated circuit composed of MOS FETs and inputting a pulse signal. This has the effect that reading can be performed at a much higher speed than a normal current sense amplifier.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an embodiment of a current sense amplifier circuit of the present invention, FIG. 2 is an operation waveform diagram of the circuit of FIG. 1, FIG. 3 is a circuit diagram of a conventional current sense amplifier circuit, FIG. FIG. 5 is an operation waveform diagram when a memory cell is selected in the semiconductor storage unit in the conventional current sense amplifier of FIG. 3, and FIG. 5 is a circuit diagram of the semiconductor storage unit in the conventional current sense amplifier circuit of FIG. FIG. 7 is an operation waveform diagram when a place where there is no memory cell is selected. 1,2,10,11 …… P-channel transistor, 3,4,5,7 ……
N-channel transistor, 8 ... complementary inverter,
9: parasitic capacitance, IN: pulse input signal terminal, A1, A2, A3
…… Memory cell selection signal, V _DD …… Power supply potential, V _ref ……
Reference potential, 0: ground potential, A: control signal of current mirror circuit, D: output signal of current sense amplifier circuit,
B: a drain signal of the Y selector, E: an output signal of the complementary inverter 8, C: a digit line.

Claims (1)

(57) [Claims] 1. A complementary inverter, a first P-channel transistor having a drain connected to an output of the complementary inverter and receiving a pulse signal, and an output signal of the complementary inverter as a gate electrode input signal; A first N-channel transistor connected to the input side of the complementary inverter and a digit line; a current mirror circuit including a P-channel transistor connected to a drain electrode of the channel transistor; and a gate of a P-channel transistor of the current mirror circuit A second P-channel transistor having a drain connected to the electrode and a gate electrode receiving the pulse signal, and a P-channel transistor of the current mirror circuit forming a second N-channel transistor forming a ratio inverter. Having current sense Amplifier circuit.