JP2630092B2 - Image display device and clock signal generation circuit for image display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device and a clock signal generation circuit for the image display device, and more particularly, to an image display device suitable for a flat display device such as a liquid crystal display or a plasma display, and an image display device for the same. The present invention relates to a clock signal generation circuit for a display device.

In recent years, a flat panel liquid crystal display, a plasma display, an EL display, or the like has been used as an image display device that receives data from a signal source such as a personal computer and displays data. Since these are operated by digital signals unlike CRT displays, they require a dot clock when latching display data sent from a signal source.

However, in general, in a personal computer system, a CR that does not require a dot clock conventionally has been used.
T-displays are often used as image display devices, and dot clocks have a high frequency and transmission through a cable or the like gives radiation noise to the computer body and other peripheral devices, which is not preferable. As a result, normally, the dot clock is not transmitted from the personal computer main body.

In view of the above circumstances, in a flat display device or the like that receives display data from a signal source such as a personal computer and displays the data, it is necessary to reproduce a necessary dot clock on the display device side. The signal generation circuit is provided in the image display apparatus main body or in addition to the signal generation circuit. In reproducing the dot clock, a horizontal synchronization signal, which is one of the synchronization signals transmitted from the signal source together with the display data, is generally used as a reference point for determining the phase of the dot clock.

[0005]

2. Description of the Related Art One conventional clock signal generation circuit will be described with reference to FIG. The reference signal generating circuit 1 includes a delay line 2 serving as a delay synchronization signal generating means and a data selector 3 serving as a delay synchronization signal selecting means.
The delay line 2 receives a horizontal synchronization signal HSYNC from a computer (not shown) and generates a number of delay synchronization signals H1 to Hn from the horizontal synchronization signal. As shown in FIG. 5A, each of the delay synchronization signals H1 to Hn has a different delay time, and is formed so as to have each delay time that is gradually different from the horizontal synchronization signal HSYNC.

The data selector 3 receives a selection signal SELECT from an image adjustment switch (not shown), selects one of the horizontal synchronizing signal and each of the delay synchronizing signals, and uses this as a reference signal HS as a PLL (phase). The signal is supplied to a comparison circuit 4 which forms a part of a clock signal reproducing means 8 configured as a synchronous loop (circuit) circuit. The PLL circuit 8 includes the comparison circuit 4, a voltage controlled oscillator (VCO) 5, and an N-ary counter 6. The rising phase of the output signal CLK of the voltage controlled oscillator 5 is referenced via the N-ary counter 6 and the comparison circuit 4. Synchronize with the falling phase of the signal HS, for example (FIG. 5b).
As a result, the clock signal generation circuit generates a clock signal CLK having an optimal phase for latching display data,
The clock signal CLK is supplied to an image display device main body (not shown). The clock signal having the optimal phase is, for example, the clock signal CLK3 or CLK4 shown in FIG.
In this case, the display data DT is latched at the rising edge of the clock signal CLK3 or CLK4 at the center position where the data occurs.

The selection signal SELE from the image adjustment switch
The CT is set at the initial adjustment at the time of shipment of this image display device, and in some cases, the setting is changed at the readjustment at the site of use, and one of the delay synchronization signals is selected via the selection signal at the time of these adjustments The image signal is supplied to a PLL circuit as a reference signal, and the image device is adjusted to an optimum screen state.

Some personal computers, for example, include a plurality of dot clock generating means and operate by selecting one of the dot clocks. FIG. 6 shows an example of a conventional clock signal generation circuit used in an image display device for a signal source of this type. In a signal source operating with a plurality of (3 in the figure) dot clocks, information on the selection of the dot clock is output by a mode determination signal 11 forming a display mode signal.

Clock signal reproducing means 1 including a PLL circuit
8 includes voltage-controlled oscillators 13 to 15 oscillating at the frequency of each dot clock corresponding to each dot clock. One of the voltage-controlled oscillators is selected by the selector 16 via the mode determination signal 11. You.
With this configuration, the output signal of the selected voltage controlled oscillator
The phase of the CLK is synchronized with the phase of the reference signal HS selected by the delay synchronization signal selecting means via the N-ary counter 17 and the comparison circuit 12, and as a result, a clock signal CLK that obtains an optimal image state is generated.

[0010]

In the case of the above-mentioned conventional clock signal generation circuit used in an image display device of a signal source having a plurality of dot clocks, the reference signal HS is determined to be one by setting an image adjustment switch. The reference signal HS output via the image adjustment switch so as to obtain an optimal image state in one dot clock is irrelevant to the display data synchronized by another dot clock. For this reason, when the selection of the dot clock is changed and the display mode is switched, there arises a problem that the display data cannot be latched unless the image adjustment switch is reset each time.

[0011] In the above case, personal computers have recently become widespread, and the number of users unfamiliar with the apparatus has been increasing, and it is difficult to deal with these unfamiliar users, which is a particular problem.

Accordingly, an object of the present invention is to provide a display mode in which any dot clock is adopted in a signal source operating with one dot clock selected from a plurality of dot clocks in view of the above-mentioned problems of the conventional clock signal generation circuit. However, the display data can be latched without resetting the image adjustment switch each time, so that a clock signal generating circuit for an image display device which is easy to operate and an image display device incorporating the same are provided. The purpose is to provide.

[0013]

FIG. 1 is a block diagram of a clock signal generation circuit according to one embodiment of the present invention.

In order to achieve the above object, a clock signal generating circuit according to the present invention, as shown in FIG. 1, includes display data and a synchronization signal synchronized by one dot clock selected from a plurality of dot clocks. A clock signal generation circuit for an image display device that is disposed at a subsequent stage of a signal source that outputs a display signal and a display mode signal corresponding to the selection of the dot clock and displays the display data on a screen. A delay synchronization signal generating means (22, 48, 55) for receiving the synchronization signal and generating a plurality of delay synchronization signals having different delay times from the synchronization signal; and image adjusting means (41, 42, 43, 51). ) Via a selection signal that at least obeys a configuration signal generated by the selection
Delay synchronization signal selecting means (23, 24, 25, 49, 55) for selecting one of the synchronization signal and each of the delay synchronization signals and outputting as a reference signal (35, 50, 56)
And oscillators (28, 29, 30) oscillating at the same frequency as the dot clocks, respectively, corresponding to the dot clocks, and the output signals of one of the oscillators selected via the display mode signal. Clock signal reproducing means (36) for synchronizing a phase with the phase of the reference signal and outputting an output signal of the selected oscillator, further comprising data selecting means controlled by the display mode signal, The different delay synchronization signal is selected for each of the oscillators via the data selection means, and the reference signal (3
5).

[0015]

The clock signal generating circuit according to the present invention includes data selecting means controlled by the display mode signal, and the different delay synchronizing signal is selected for each oscillator via the data selecting means, and the reference signal (35) is selected. ), Once the image is adjusted under each display mode signal by the setting signal of the image adjusting means, the display mode is changed even if the selection of the oscillator is changed when the display mode is changed. A reference signal corresponding to each oscillator at the time of adjustment is output according to the signal, and the display data can be latched without requiring resetting by the image adjustment means.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A clock signal generating circuit according to an embodiment of the present invention will be described with reference to FIG. In the figure, the clock signal generation circuit includes four data selectors 23 to 26 in a reference signal generation circuit 21. First to third data selectors 23 to 25 constituting delay synchronization signal selection means
Receives n types of delay synchronization signals H1 to Hn from a delay signal generation means (delay line) 22 and an external horizontal synchronization signal HSYNC, and outputs setting signals S1 to S3 from image adjustment switches (not shown). Then, one of the input signals, that is, one delayed synchronizing signal or horizontal synchronizing signal, is output to the fourth data selector 26 serving as data selecting means.

The fourth data selector 26 receives signals from the first to third data selectors 23 to 25 and receives the signals from the first to third data selectors 23 to 25 in accordance with a mode determination signal (display mode signal) MODE. And outputs it as a reference signal 35 for clock signal reproducing means 36 including a PLL circuit. The PLL circuit of the clock signal regenerating means 36 includes a comparator 27 serving as a phase comparator.
, Three voltage-controlled oscillators 28 to 30 corresponding to the type of dot clock of the signal source, and an N-ary counter 32, and the N-ary counter 32 includes a decoder 33 and a counter 34.

Each of the voltage controlled oscillators 28 to 30 supplies an output signal having a frequency of 15, 20, or 25 MHz, for example, to a fifth data selector 31 constituting a part of the clock signal reproducing means 36. The fifth data selector 31 receives the output of each of the voltage controlled oscillators 28 to 30 and receives a mode determination signal.
The output of any one of the voltage controlled oscillators is selected according to the MODE, and given to the counter 34 of the N-ary counter 32. Data decoder 33 decodes the output of counter 34 and outputs the falling edge of the most significant bit to comparison circuit 27. The comparison circuit 27 compares the falling phase of the reference signal 35 with the output of the decoder 33, and if there is a difference between them, outputs the difference to each of the voltage controlled oscillators 28 to 30 as a control voltage signal.

With the above configuration, this clock signal generation circuit operates as follows. The horizontal synchronization signal HSYNC and each of the delay synchronization signals H1 to H
n is selected by each of the first to third data selectors 23 to 25 via the image adjustment switch setting signals S1 to S3 corresponding to each display mode, and each of the selection signals SE
Output as LECT1 to SELECT3. When the specific mode determination signal MODE is given to the fourth data selector 26, the adjustment is performed so as to obtain an optimal image state in the mode through setting adjustment of one corresponding image adjustment switch. This adjustment is performed similarly in each of the other modes.

At the time of actual use, the image adjustment switch is maintained at the above setting, and each of the data selectors 23-
25, each one of the delay synchronization signals selected by the adjusted setting signal is output to the fourth data selector 26.
, One of these is the mode decision signal
The selection is made according to the MODE, and the reference signal at the time of adjustment is selected as it is to be the reference signal at the time of use.

As described above, image adjustment in the mode is performed by setting each image adjustment switch corresponding to each mode determination signal from the signal source at the time of adjustment, and the dot clock of the signal source is used at the time of subsequent use. Is selected automatically by the fourth data selector 26 even if the selection is changed, the display data corresponding to each display mode does not need to be changed each time. Are latched, and the image at the time of adjustment is reproduced. In the case of the above embodiment, the image adjustment switch and the delay synchronization signal selection means are provided corresponding to each display mode.

FIG. 2 is a block diagram of a reference signal generation circuit and an image adjustment switch, which are main parts of a clock signal generation circuit according to a second embodiment of the present invention. In the figure, image adjustment switches 41, 42, and 43 are each configured as a 4-bit code switch.
The setting signals S4, S5, and S6 by the second and the third 43 are first and second data selectors 44 and 46 that constitute data selection means.
The data is processed through an adder 45 to form 4-bit selection signals D1 to D4, which are supplied to a third data selector 49 which receives the horizontal synchronization signal HSYNC and the delay synchronization signals H1 to Hn of the delay line 48 as inputs. Give it.

The mode determination signals MODE1 and MODE2 are input to the clock signal generation circuit as 2-bit signals, and each bit is converted into the first and second data selectors 44 and 46, respectively.
Given to. The first data selector 44 receives the signals of the second and third code switches 42 and 43 and outputs a signal of one of the code switches according to the first bit MODE1 of the mode determination signal.

The adder 45 includes a first code switch 41
And the output of the first data selector 44 are input and added, and a 4-bit output signal is provided to the second data selector 46 except for the most significant bit. The second bit MODE2 of the mode determination signal is input as a control signal to the second data selector 46, and the second data selector 46 receives the first code switch 41 or the second code switch 41 according to the second bit MODE2 of the mode determination signal. The output of the adder 45 is provided as selection signals D1 to D4 to a third data selector 49 which functions as delay synchronization signal selection means.

In the case of the second embodiment, first, the second bit MODE2 of the mode determination signal is set to "1", and the initial image adjustment is performed by setting the first code switch. By setting the first bit MODE1 of the signal to "1" and the second bit MODE2 to "0" and setting the second code switch, both bits of the mode determination signal are further set to "0" and the third code switch The initial image adjustment is similarly performed depending on the setting. In actual use, signals from each code switch are input to the third data selector 49 as selection signals D1 to D4 having exactly the same values as in the initial image adjustment, according to the mode determination signal from the signal source. The delay synchronization signal at the time of adjustment according to each display mode is input as a reference signal to the comparison circuit of the PLL circuit of the clock signal reproducing means.

If the initial image adjustment cannot be performed with the initial adjustment due to some cause, for example, a change in temperature, and the image adjustment is required again, the first code switch 41 is set to the setting in each display mode. used. Normally, such a change fluctuates in each display mode in the same manner. Therefore, by changing the setting in any one of the display modes, it is expected that an optimum image state can be obtained in all the display modes, and the usability is good.

FIG. 3 is a block diagram of a main part of the clock signal generation circuit according to the third embodiment. In the case of FIG. 6, the selection signal SELECT is generated by each one code switch 51 and the nonvolatile memory 52 constituting data selection means. In the case of this embodiment, an address of the nonvolatile memory 52 is specified by the same mode determination signals MODE1 and MODE2 as in the second embodiment, and the signal of the code switch 51 is stored at the address according to each display mode. With this configuration, the setting signal S7 of the code switch 51 during the initial adjustment
However, even in use, the mode determination signal MODE from the signal source
1. Read from the address in accordance with MODE2 to become a selection signal, which is supplied to a data selector 55 which constitutes a delay synchronization signal selection means.

In the third embodiment, when readjustment of an image is required, the code switch 51 is set again in the same mode and the data at the address is rewritten. In the case of this embodiment, unlike the case of the second embodiment, there is a high possibility that readjustment is required in each mode.

[0029]

As described above, according to the present invention, the selection signal is switched in accordance with the display mode signal, and the reference signal can be selected for each oscillator. The image state at the time of adjustment can be automatically selected without necessity, and a clock signal generation circuit for an image display device with good operability and an image display device incorporating the same can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a block diagram of a second embodiment of the present invention.

FIG. 3 is a block diagram of a third embodiment of the present invention.

FIG. 4 is a block diagram of a conventional clock signal generation circuit having one VCO.

5A and 5B are explanatory diagrams of a latch of display data, FIG. 5A is an explanatory diagram of a delay synchronization signal, FIG. 5B is an explanatory diagram of phase synchronization, and FIG.
FIG. 4 is an explanatory diagram of an optimal phase for a latch.

FIG. 6 is a block diagram of a conventional clock signal generation circuit having a plurality of VCOs.

[Explanation of symbols]

HSYNC horizontal synchronization signal H1 to Hn delay synchronization signal S1 to S7 setting signal 22, 48, 54 delay synchronization signal generation means 23 to 25, 49, 55 delay synchronization signal selection means 26, 44 to 46, 52 data selection means 28 to 30 Voltage controlled oscillator 36 Clock signal reproducing means including PLL circuit

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical display location H04N 5/66 H03L 7/18 E

Claims (4)

(57) [Claims] A signal for outputting a display signal including display data and a synchronization signal synchronized by one dot clock selected from a plurality of dot clocks, and a display mode signal corresponding to the selection of the dot clock. A clock signal generation circuit for an image display device, which is arranged at a subsequent stage of a source and displays the display data on a screen, comprising: a plurality of delay synchronization circuits which receive the synchronization signal and have different delay times from the synchronization signal. Delay synchronizing signal generating means (22, 48, 55) for generating a signal, and image adjusting means (41, 42,
43, 51), by selecting one of the synchronization signal and each of the delay synchronization signals through a selection signal at least according to a setting signal generated by the selection of the reference signal (35, 51).
50, 56) for outputting the delayed synchronization signal selecting means (2
3, 24, 25, 49, and 55) and oscillators (28, 29, 3) that oscillate at the same frequency as the dot clocks.
0) corresponding to each of the dot clocks, synchronizing the phase of the output signal of one of the oscillators selected via the display mode signal with the phase of the reference signal, and outputting the output signal of the selected oscillator. And a clock signal reproducing means (36) for outputting a clock signal, wherein the data selecting means is further controlled by the display mode signal, and the different delay synchronization signal is selected for each of the oscillators via the data selecting means. A clock signal generating circuit which is adapted to form the reference signal (35). 2. The clock signal generating circuit according to claim 1, wherein the reference signal for each oscillator is obtained from one image adjusting means common to each oscillator. 3. A storage circuit having a storage cell for storing a setting signal for each of said oscillators, wherein an address of each of said storage cells is specified by said display mode signal. 3. The clock signal generation circuit according to 2. 4. An image display device incorporating the clock signal generation circuit according to claim 1.