JP2629586B2 - Semiconductor device and method of manufacturing the same - Google Patents
Semiconductor device and method of manufacturing the sameInfo
- Publication number
- JP2629586B2 JP2629586B2 JP5316209A JP31620993A JP2629586B2 JP 2629586 B2 JP2629586 B2 JP 2629586B2 JP 5316209 A JP5316209 A JP 5316209A JP 31620993 A JP31620993 A JP 31620993A JP 2629586 B2 JP2629586 B2 JP 2629586B2
- Authority
- JP
- Japan
- Prior art keywords
- lower electrode
- thin film
- barrier layer
- film
- ferroelectric
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 239000010408 film Substances 0.000 claims description 41
- 239000010409 thin film Substances 0.000 claims description 32
- 239000010410 layer Substances 0.000 claims description 30
- 230000004888 barrier function Effects 0.000 claims description 26
- 239000011229 interlayer Substances 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 10
- 239000010936 titanium Substances 0.000 claims description 10
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims description 7
- 239000007772 electrode material Substances 0.000 claims description 5
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 238000005498 polishing Methods 0.000 claims description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims 2
- 229910010413 TiO 2 Inorganic materials 0.000 description 11
- 229910004298 SiO 2 Inorganic materials 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 238000002955 isolation Methods 0.000 description 3
- 229910052745 lead Inorganic materials 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 238000003980 solgel method Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- -1 TiO 2 Chemical compound 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 229910052746 lanthanum Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000005546 reactive sputtering Methods 0.000 description 1
- 230000009257 reactivity Effects 0.000 description 1
- 238000000682 scanning probe acoustic microscopy Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体集積回路装置に内
蔵されている半導体デバイス及びその製造方法に関す
る。The present invention relates to a semiconductor device built in a semiconductor integrated circuit device and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】半導体メモリセル内の容量絶縁膜として
強誘電体薄膜を用いることにより、高速で書き込み、読
み出し動作を行うことの出来る不揮発メモリ、もしくは
比誘電率の大きい強誘電体薄膜を容量絶縁膜として利用
した集積度の高いダイナミックランダムアクセスメモリ
（ＤＲＡＭ）を作製することができる。このようなメモ
リセルを作製する場合、容量絶縁膜として主にＰｂもし
くはＢｉを成分として含む酸化物強誘電体薄膜が利用さ
れる。従来の技術としては、「ビットパラレル構造を持
つ１６キロビット強誘電体不揮発メモリ」：ウォーマッ
ク、トイッシュ、ダイジェスト オブ １９８９ アイ
トリプルイー インターナショナル ソリッドステイト
サーキット カンファレンス、ページ２４２−２４３、
１９８９年（”Ａ １６ｋｂ Ｆｅｒｒｏｅｌｅｃｔｒ
ｉｃ Ｎｏｎｖｏｌａｔｉｌｅ Ｍｅｍｏｒｙ ｗｉｔ
ｈ ａ Ｂｉｔ Ｐａｒａｌｌｅｌ Ａｒｃｈｉｔｅｃ
ｔｕｒｅ”， ：Ｒ．Ｗｏｍａｃｋ ａｎｄ Ｄ．Ｔｏ
ｉｓｃｈ， Ｄｉｇｅｓｔｏｆ １９８９ ＩＥＥＥ
Ｉｎｔｅｒｎａｔｉｏｎａｌ Ｓｏｌｉｄ−Ｓｔａｔｅ
Ｃｉｒｃｕｉｔｓ Ｃｏｎｆｅｒｅｎｃｅ， ｐｐ．
２４２−２４３，Ｆｅｂ． １９８９）に示されている
構造が用いられている。すなわち、図１に示すように層
間絶縁膜３もしくは多結晶シリコンとの相互拡散を防ぐ
ための導電性バリア層上に作製された下部電極４を微細
加工した後、強誘電体薄膜５が６００℃前後の成膜温度
で作製される。この後強誘電体薄膜は微細加工され上部
電極６、素子分離膜７、Ａｌ配線８が作製される。2. Description of the Related Art By using a ferroelectric thin film as a capacitor insulating film in a semiconductor memory cell, a nonvolatile memory capable of performing writing and reading operations at a high speed, or a ferroelectric thin film having a large relative dielectric constant is used as a capacitor insulating film. A highly integrated dynamic random access memory (DRAM) used as a film can be manufactured. When fabricating such a memory cell, an oxide ferroelectric thin film mainly containing Pb or Bi as a component is used as a capacitive insulating film. As a conventional technology, "16 kilobit ferroelectric nonvolatile memory having a bit parallel structure": Warmac, Toish, Digest of 1989 i Triple E International Solid State Circuit Conference, pp. 242-243,
1989 ("A 16 kb Ferroelectric
ic Nonvolatile Memory wit
ha Bit Parallel Architect
cure ",: R. Womack and D. To
isch, Digestof 1989 IEEE
International Solid-State
Circuits Conference, pp.
242-243, Feb. 1989). That is, as shown in FIG. 1, after the lower electrode 4 formed on the interlayer insulating film 3 or the conductive barrier layer for preventing the interdiffusion with the polycrystalline silicon is finely processed, the ferroelectric thin film 5 is heated to 600 ° C. It is produced at a film forming temperature before and after. Thereafter, the ferroelectric thin film is finely processed to produce an upper electrode 6, an element isolation film 7, and an Al wiring 8.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら従来のメ
モリセル作製技術には次のような欠点がある。即ち層間
絶縁膜としては一般にＳｉＯ2 が用いられることが多い
が、Ｐｂを成分に含む強誘電体薄膜を微細加工された電
極パターン上に６００℃前後の成膜温度で作製する場
合、電極に覆われていない部分の層間絶縁膜と強誘電体
薄膜との間でＰｂとＳｉが相互拡散を起こす。この相互
拡散により、層間絶縁膜の下に位置するトランジスタな
どの半導体素子の特性が劣化したり、層間絶縁膜直上の
強誘電体薄膜を通して電極上の強誘電体薄膜の特性が劣
化するという問題があった。However, the conventional memory cell fabrication technique has the following disadvantages. That is, SiO 2 is generally used as an interlayer insulating film. However, when a ferroelectric thin film containing Pb is formed on a finely processed electrode pattern at a film forming temperature of about 600 ° C., the electrode is not covered. Pb and Si cause interdiffusion between the unexposed portion of the interlayer insulating film and the ferroelectric thin film. Due to this interdiffusion, the characteristics of a semiconductor element such as a transistor located below the interlayer insulating film are deteriorated, and the characteristics of the ferroelectric thin film on the electrode are deteriorated through the ferroelectric thin film immediately above the interlayer insulating film. there were.
【０００４】さらに強誘電体の下部電極材料として一般
的に用いられているＰｔは反応性に乏しく、反応性イオ
ンエッチングでは一度エッチングされたＰｔがレジスト
の側壁など周囲に再堆積してしまい、Ｐｔ電極が意図し
た形状に微細加工できず、デバイスの歩留りを低下させ
る要因の一つとなっている。又、強誘電体が下部電極と
上部電極に挟まれた構造において、下部電極と強誘電体
を連続して堆積させた場合は前記のような元素の相互拡
散はおこらないが、最終的な形状を得るためのエッチン
グ工程において強誘電体の側壁にＰｔが再付着し、下部
電極と上部電極が短絡してしまうという問題が生じてい
た。又、強誘電体薄膜の作製方法によっては段差被覆性
が悪いため、下部電極の加工により生ずる段差部分が素
子の不良の原因となる。Further, Pt, which is generally used as a material for a lower electrode of a ferroelectric substance, has poor reactivity. In reactive ion etching, once etched Pt is redeposited on the periphery such as a side wall of a resist, and Pt is removed. The electrode cannot be finely processed into an intended shape, which is one of the factors that lower the yield of the device. Further, in a structure in which the ferroelectric is sandwiched between the lower electrode and the upper electrode, when the lower electrode and the ferroelectric are successively deposited, mutual diffusion of the elements does not occur as described above, but the final shape In the etching process for obtaining the Pt, Pt is re-attached to the side wall of the ferroelectric substance, and a short circuit occurs between the lower electrode and the upper electrode. Also, depending on the method of manufacturing the ferroelectric thin film, the step coverage is poor, so the step formed by processing the lower electrode causes the element to be defective.
【０００５】[0005]
【課題を解決するための手段】本発明はチタンオキサイ
ドよりなる凹状のバリア層を層間絶縁膜上に層状に有
し、その層の窪み部分に下部電極材料が埋め込まれてお
り、かつ少なくとも該下部電極材料を覆う強誘電体薄
膜、上部電極で構成されていることを特徴とする半導体
デバイス構造およびその製造方法に関する。SUMMARY OF THE INVENTION The present invention provides a titanium oxide
Has a concave barrier layer of de layered on the interlayer insulating film, and the lower electrode material is embedded in the recess portion of the layer, and the ferroelectric thin film covering at least said lower electrode material, composed of an upper electrode And a method of manufacturing the same.
【０００６】本発明の半導体デバイスの形状によれば、
ＴｉＯ 2 等のチタンオキサイドよりなるバリア層によ
り、ＳｉＯ2 を成分として含む層間絶縁膜と強誘電体薄
膜が接する部分がなくなるため、元素の相互拡散の問題
が解決される。つまり、このバリア層は強誘電体薄膜作
製温度においても層間絶縁膜の主成分であるＳｉ、容量
絶縁膜に含まれるＰｂと相互拡散しないため結果的に層
間絶縁膜中へのＰｂの侵入、およびＳｉの強誘電体薄膜
中への侵入を抑制する働きを持つ。そのため強誘電体薄
膜及びトランジスタなどの素子の劣化をともに防ぐこと
が出来る。なお、バリア層としてチタンオキサイドを用
いるためには最初からＴｉの酸化物を堆積しても良い
が、金属Ｔｉを堆積し、強誘電体の形成・加工段階で同
時に酸化を行ってＴｉ酸化物としても良い。According to the shape of the semiconductor device of the present invention,
Ri by <br/> the barrier layer made of titanium oxide such as TiO 2, since the interlayer insulating film and the ferroelectric thin film is in contact with the portion containing SiO 2 as a component eliminated, the mutual diffusion of elements problem is solved. In other words, this barrier layer does not interdiffuse with Si, which is a main component of the interlayer insulating film, and Pb contained in the capacitive insulating film even at the ferroelectric thin film forming temperature, so that Pb penetrates into the interlayer insulating film, and It has a function of suppressing the penetration of Si into the ferroelectric thin film. Therefore, deterioration of the ferroelectric thin film and elements such as transistors can be prevented. In order to use titanium oxide as the barrier layer, an oxide of Ti may be deposited from the beginning. However, metal Ti is deposited and oxidized simultaneously in the ferroelectric formation and processing steps to form a Ti oxide. Is also good.
【０００７】さらに、埋め込まれた下部電極はバリア層
との間で段差を形成しないため強誘電体薄膜の作製方法
によらず信頼性の高い素子を作製できる。また下部電極
材料のエッチング工程を含まないため良好な強誘電体膜
作製に必要でかつ微細加工の困難な下部電極材料も選択
できる。Further, since the embedded lower electrode does not form a step with the barrier layer, a highly reliable element can be manufactured irrespective of the method of manufacturing the ferroelectric thin film. Further, since a lower electrode material etching step is not included, a lower electrode material which is necessary for producing a favorable ferroelectric film and which is difficult to finely process can be selected.
【０００８】[0008]
【実施例】本発明について図面を参照して説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described with reference to the drawings.
【０００９】（実施例１）ここでは層間絶縁膜上のバリ
ア層として３００ｎｍのＴｉＯ2 を反応性スパッタ法で
作製し２００ｎｍの深さの溝を作製したもの、下部電極
として４００ｎｍのＰｔをＤＣスパッタ法で、強誘電体
膜として２００ｎｍのＰＺＴ薄膜をゾルゲル法で作製し
た例を示す。バリア層は金属Ｔｉを層状に作製し、下部
電極を埋め込んだ後、酸素雰囲気中での強誘電体薄膜作
製時に同時にＴｉも酸化することを利用して作製するこ
ともできる。強誘電体膜としてはＰＺＴの他にＰｂＴｉ
Ｏ3、（Ｐｂ，Ｌａ）（Ｚｒ，Ｔｉ）Ｏ3 などのペロブ
スカイト型酸化物強誘電体を用いることができる。また
ゾルゲル法は成膜方法の性格上段差のある基板上に均一
な膜厚の薄膜を形成することが難しいと考えられる成膜
方法の一つであるが、平坦な基板上では均一で良好な特
性の強誘電体膜を１００ｎｍ以下の薄膜でも得ることが
できる成膜方法である。(Example 1) Here, 300 nm of TiO 2 was formed as a barrier layer on an interlayer insulating film by a reactive sputtering method to form a groove having a depth of 200 nm, and 400 nm of Pt was formed by DC sputtering as a lower electrode. An example is shown in which a 200 nm PZT thin film is formed as a ferroelectric film by a sol-gel method. The barrier layer can also be manufactured by using metal Ti in a layered form, embedding the lower electrode, and simultaneously oxidizing Ti when the ferroelectric thin film is manufactured in an oxygen atmosphere. As a ferroelectric film, besides PZT, PbTi
Perovskite oxide ferroelectrics such as O 3 and (Pb, La) (Zr, Ti) O 3 can be used. In addition, the sol-gel method is one of the film forming methods which is considered to be difficult to form a thin film having a uniform thickness on a substrate having a step due to the nature of the film forming method. This is a film forming method capable of obtaining a ferroelectric film having characteristics even in a thin film of 100 nm or less.
【００１０】図２は層間絶縁膜３上にバリア層ＴｉＯ2
薄膜９を設けた構造である。ＴｉＯ2 薄膜９に井戸状の
下部電極埋め込み穴を形成した後、下部電極４を作製す
る。下部電極は、機械的もしくは化学反応を利用した研
磨によりバリア層９と下部電極４の平坦化された表面が
露出するまで削られる。この表面にＰＺＴ薄膜５を作製
する。ＰＺＴ薄膜作製時にはＴｉＯ2 層９がＰＺＴ層５
と層間絶縁膜３との相互拡散バリアとして機能する。図
３に層間絶縁膜ＳｉＯ2 上に５０ｎｍのＴｉＯ2 バリア
層を作製したのち、ＰＺＴ薄膜を作製した場合のオージ
ェ電子分光により測定した深さ方向の組成分布を示す。
ＰＺＴ／ＴｉＯ2 界面でＰＺＴ層からバリア層に侵入す
るＰｂは界面から１０ｎｍ程度に留まっておりＳｉＯ2
中に侵入するＰｂは存在しない。さらにＴｉＯ2 ／Ｓｉ
Ｏ2 界面でもＳｉの拡散が抑制されており、ＰＺＴ層内
ではＳｉは検出限界以下である。この結果からＴｉＯ2
薄膜がＰＺＴ成膜時の拡散バリア層となることが確認さ
れる。ちなみにＴｉＯ2 層９上ではＰＺＴの準安定相で
ある常誘電体のパイロクロア構造となるが、パイロクロ
ア相部分はＰＺＴ成膜後にＴｉＯ2 バリア層と共にエッ
チングで除去されるので実用上問題はなく、エッチング
せずにパイロクロア相部分と酸化チタン部分を素子分離
膜として用いることもできる。FIG. 2 shows a barrier layer TiO 2 on an interlayer insulating film 3.
This is a structure in which a thin film 9 is provided. After forming a well-shaped lower electrode embedding hole in the TiO 2 thin film 9, the lower electrode 4 is manufactured. The lower electrode is polished by mechanical or chemical polishing until the flattened surfaces of the barrier layer 9 and the lower electrode 4 are exposed. A PZT thin film 5 is formed on this surface. When producing a PZT thin film, the TiO 2 layer 9 is
Functions as an interdiffusion barrier between the gate electrode and the interlayer insulating film 3. FIG. 3 shows the composition distribution in the depth direction measured by Auger electron spectroscopy when a 50 nm TiO 2 barrier layer is formed on the interlayer insulating film SiO 2 and then a PZT thin film is formed.
Pb penetrating from the PZT layer to the barrier layer at the PZT / TiO 2 interface remains at about 10 nm from the interface, and SiO 2
There is no Pb penetrating into it. Further, TiO2 / Si
The diffusion of Si is also suppressed at the O 2 interface, and Si is below the detection limit in the PZT layer. From this result, TiO 2
It is confirmed that the thin film becomes a diffusion barrier layer during PZT film formation. Incidentally, on the TiO 2 layer 9, a paraelectric pyrochlore structure which is a metastable phase of PZT is formed. However, since the pyrochlore phase is removed by etching together with the TiO 2 barrier layer after the PZT film is formed, there is no practical problem. Instead, the pyrochlore phase portion and the titanium oxide portion can be used as an element isolation film.
【００１１】（実施例２）図４に示す実施例は層間絶縁
膜３にコンタクトホールを作製し多結晶シリコン１０と
Ｓｉバリアメタル１１で下部電極４とトランジスタ２の
ドレインを接続する必要がある場合を示している。層間
絶縁膜３を作製した後第一のコンタクトホールを作製し
て多結晶シリコンを埋め込む。続けて金属Ｔｉ層９を作
製する。本構造の場合、多結晶シリコンを酸化させない
ためにバリア層として金属Ｔｉを用いなければならな
い。埋め込まれた第一のコンタクトホール上に容量キャ
パシタの面積として必要な面積の第二のコンタクトホー
ルを形成する。第二のコンタクトホールは、Ｓｉバリア
メタル１１、下部電極４で順次埋め込まれ平坦になるよ
うに研磨された後、その上にＰＺＴ薄膜５を作製する。
この場合は強誘電体膜作製時に酸化された酸化チタンバ
リア層９の膜厚ｔ１とＳｉバリアメタル１１の膜厚ｔ２
をｔ１＞ｔ２の関係にしなければならない。以上のよう
な構造のメモリセルを作製することにより第２図の場合
と同様にＰＺＴ薄膜とＳｉＯ2 との相互拡散を防ぐこと
ができ、かつ下部電極をエッチングすることなく平坦な
面上に容量絶縁膜を形成できる。(Embodiment 2) In the embodiment shown in FIG. 4, it is necessary to form a contact hole in the interlayer insulating film 3 and connect the lower electrode 4 and the drain of the transistor 2 with the polycrystalline silicon 10 and the Si barrier metal 11. Is shown. After forming the interlayer insulating film 3, a first contact hole is formed and polycrystalline silicon is buried. Subsequently, a metal Ti layer 9 is formed. In the case of this structure, metal Ti must be used as a barrier layer in order not to oxidize polycrystalline silicon. A second contact hole having an area required as an area of the capacitor is formed on the buried first contact hole. The second contact hole is sequentially buried with the Si barrier metal 11 and the lower electrode 4 and polished so as to be flat, and then the PZT thin film 5 is formed thereon.
In this case, the thickness t1 of the titanium oxide barrier layer 9 oxidized during the production of the ferroelectric film and the thickness t2 of the Si barrier metal 11
Must be in a relationship of t1> t2. By manufacturing the memory cell having the above structure, the interdiffusion between the PZT thin film and SiO 2 can be prevented as in the case of FIG. 2, and the capacitance can be formed on a flat surface without etching the lower electrode. An insulating film can be formed.
【００１２】なお、上記記述はメモリセルのキャパシタ
を想定した場合についてのみ述べたが、本発明は広く半
導体集積回路にＰｂを含む強誘電体薄膜を適用する多く
の場合に同様の効果が得られる。Although the above description has been made only on the assumption of a capacitor of a memory cell, the present invention can obtain the same effect in many cases where a ferroelectric thin film containing Pb is widely applied to a semiconductor integrated circuit. .
【図１】従来技術によるメモリセル構造である。FIG. 1 is a conventional memory cell structure.
【図２】本発明によるメモリセル構造である。FIG. 2 is a memory cell structure according to the present invention.
【図３】ＴｉＯ2 （５０ｎｍ）／ＳｉＯ2 上にＰＺＴ薄
膜が作製された場合の深さ方向の組成分布図である。FIG. 3 is a composition distribution diagram in the depth direction when a PZT thin film is formed on TiO 2 (50 nm) / SiO 2 .
【図４】多結晶シリコンによるコンタクトが存在する場
合の本発明によるメモリセル構造である。FIG. 4 is a memory cell structure according to the present invention when a contact made of polycrystalline silicon exists.
１ Ｓｉ基板 ２ トランジスタ ３ 層間絶縁膜 ４ 下部電極 ５ ＰＺＴ薄膜 ６ 上部電極 ７ 素子分離膜 ８ Ａｌ配線 ９ 酸化チタンバリア層 １０ 多結晶シリコン １１ Ｓｉバリアメタル DESCRIPTION OF SYMBOLS 1 Si substrate 2 Transistor 3 Interlayer insulating film 4 Lower electrode 5 PZT thin film 6 Upper electrode 7 Element isolation film 8 Al wiring 9 Titanium oxide barrier layer 10 Polycrystalline silicon 11 Si barrier metal
Claims (2)
る凹状のバリア層を有し、該バリア層の窪み部分に下部
電極材料が埋め込まれており、かつ少なくとも該下部電
極上を覆う強誘電体薄膜、及び上部電極を有することを
特徴とする半導体デバイス。1. The method according to claim 1, wherein the interlayer insulating film is made of titanium oxide.
That has a concave barrier layer, a semiconductor device characterized in that it comprises and the lower electrode material is embedded in the recess portion of the barrier layer, and a ferroelectric thin film covering the at least said lower electrode and an upper electrode .
ンオキサイドよりなるバリア層を形成した後、該層に電
極面積として必要な開口面積を持つ井戸状の溝を形成
し、その上に前記溝の深さより厚い下部電極層を形成し
た後に該下部電極層を研磨することにより平坦面に埋め
込まれた下部電極構造を形成し、しかる後に強誘電体膜
を形成した後該強誘電体膜を前記バリア層と共に加工
し、最後に上部電極を形成することを特徴とする請求項
１記載の半導体デバイスの製造方法。2. The method according to claim 1, further comprising: forming a metal titanium or titanium on the interlayer insulating film.
After forming a barrier layer made of oxide , a well-shaped groove having an opening area required as an electrode area is formed in the layer, and a lower electrode layer having a thickness greater than the depth of the groove is formed thereon. Forming a lower electrode structure embedded in a flat surface by polishing the layer, forming a ferroelectric film thereafter, processing the ferroelectric film together with the barrier layer , and finally forming an upper electrode The method for manufacturing a semiconductor device according to claim 1, wherein:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5316209A JP2629586B2 (en) | 1993-12-16 | 1993-12-16 | Semiconductor device and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5316209A JP2629586B2 (en) | 1993-12-16 | 1993-12-16 | Semiconductor device and method of manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07169854A JPH07169854A (en) | 1995-07-04 |
| JP2629586B2 true JP2629586B2 (en) | 1997-07-09 |
Family
ID=18074520
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5316209A Expired - Lifetime JP2629586B2 (en) | 1993-12-16 | 1993-12-16 | Semiconductor device and method of manufacturing the same |
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| Country | Link |
|---|---|
| JP (1) | JP2629586B2 (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3929513B2 (en) | 1995-07-07 | 2007-06-13 | ローム株式会社 | Dielectric capacitor and manufacturing method thereof |
| KR100228761B1 (en) * | 1995-12-27 | 1999-11-01 | 김영환 | Capacitor Formation Method of Semiconductor Device |
| US6093575A (en) * | 1996-09-04 | 2000-07-25 | Nippon Steel Corporation | Semiconductor device and production method of a semiconductor device having a capacitor |
| JPH10107223A (en) * | 1996-10-02 | 1998-04-24 | Texas Instr Japan Ltd | Dielectric capacitor, dielectric memory device, and manufacturing method thereof |
| CA2361737A1 (en) | 1999-02-04 | 2000-08-10 | Takashi Nakamura | Capacitor and method for manufacturing the same |
| WO2001024237A1 (en) * | 1999-09-28 | 2001-04-05 | Symetrix Corporation | Integrated circuits with barrier layers and methods of fabricating same |
| KR100391987B1 (en) * | 2000-09-18 | 2003-07-22 | 삼성전자주식회사 | semiconductor devices having ferroelectric material capacitor and method of making the same |
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| JP2601022B2 (en) * | 1990-11-30 | 1997-04-16 | 日本電気株式会社 | Method for manufacturing semiconductor device |
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1993
- 1993-12-16 JP JP5316209A patent/JP2629586B2/en not_active Expired - Lifetime
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| Publication number | Publication date |
|---|---|
| JPH07169854A (en) | 1995-07-04 |
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