JP2627796B2 - Semiconductor manufacturing equipment - Google Patents
Semiconductor manufacturing equipmentInfo
- Publication number
- JP2627796B2 JP2627796B2 JP63320281A JP32028188A JP2627796B2 JP 2627796 B2 JP2627796 B2 JP 2627796B2 JP 63320281 A JP63320281 A JP 63320281A JP 32028188 A JP32028188 A JP 32028188A JP 2627796 B2 JP2627796 B2 JP 2627796B2
- Authority
- JP
- Japan
- Prior art keywords
- processing
- wafer
- loading
- unloading
- control unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 63
- 238000004519 manufacturing process Methods 0.000 title claims description 53
- 230000007246 mechanism Effects 0.000 claims description 113
- 238000000034 method Methods 0.000 claims description 9
- 230000007723 transport mechanism Effects 0.000 claims description 9
- 235000012431 wafers Nutrition 0.000 description 84
- 239000011248 coating agent Substances 0.000 description 5
- 238000000576 coating method Methods 0.000 description 5
- 239000000428 dust Substances 0.000 description 3
- 230000003749 cleanliness Effects 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- FFUAGWLWBBFQJT-UHFFFAOYSA-N hexamethyldisilazane Chemical compound C[Si](C)(C)N[Si](C)(C)C FFUAGWLWBBFQJT-UHFFFAOYSA-N 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
Landscapes
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Control Of Conveyors (AREA)
Description
【発明の詳細な説明】 [発明の目的] (産業上の利用分野) 本発明は、半導体製造装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a semiconductor manufacturing apparatus.
(従来の技術) 従来より半導体の製造プロセスでは、被処理物例えば
半導体ウエハは複数の処理工程で各種の処理を受ける
が、近年、この半導体ウエハの高集積化に伴い、上記各
処理工程は益々増加し複雑化している。2. Description of the Related Art Conventionally, in a semiconductor manufacturing process, an object to be processed, for example, a semiconductor wafer is subjected to various processes in a plurality of processing steps. Increasing and more complex.
一方、半導体製造の環境も上記微細化に伴ってダスト
(塵埃)の付着による半導体素子の欠陥を防止するため
により高いクリーン度が要求されており、クリーンルー
ムの高いクリーン度化、また装置自身からの発塵の低減
化が一層必要とされている。On the other hand, in the environment of semiconductor manufacturing, a higher degree of cleanliness is required in order to prevent defects of semiconductor elements due to adhesion of dust (dust) along with the above miniaturization. There is a further need to reduce dust generation.
そこで複雑化する処理工程に容易に対応でき、また高
クリーン度化への対応が可能な半導体製造装置、例えば
レジスト処理装置として、複数の処理機構例えばウエハ
搬入・搬出機構、レジスト塗布機構、現像機構、加熱機
構等を配置接続し、ウエハ搬送機構により各処理機構へ
半導体ウエハを所定の処理手順に従って自動搬送して一
連の処理を行うように構成したものが開発されている。Therefore, a semiconductor manufacturing apparatus which can easily cope with complicated processing steps and can cope with high cleanliness, for example, as a resist processing apparatus, includes a plurality of processing mechanisms such as a wafer loading / unloading mechanism, a resist coating mechanism, and a developing mechanism. A configuration has been developed in which a heating mechanism and the like are arranged and connected, and a semiconductor wafer is automatically transferred to each processing mechanism by a wafer transfer mechanism according to a predetermined processing procedure to perform a series of processing.
このような半導体製造装置における各処理機構の配列
構成は、処理内容や設置条件等により異なり、例えば各
処理機構を直線的に配置接続し、ウエハ搬送機構により
一方端の処理機構から順次次処理機構へと搬送して処理
するものや、複数の処理機構を平行配列し、中央部にウ
エハ搬送機構を配設して各処理機構へ半導体ウエハを搬
送して処理するように構成したもの等がある。The arrangement configuration of each processing mechanism in such a semiconductor manufacturing apparatus differs depending on the processing contents, installation conditions, and the like. For example, each processing mechanism is linearly arranged and connected, and the next processing mechanism is sequentially arranged from one end processing mechanism by a wafer transfer mechanism. And a configuration in which a plurality of processing mechanisms are arranged in parallel, a wafer transport mechanism is arranged in the center, and a semiconductor wafer is transported to each processing mechanism for processing. .
この半導体製造装置によるウエハ処理動作は、まず半
導体ウエハを所定の間隔で多数積層収容したウエハキャ
リアを昇降自在に構成されたウエハ搬入機構(以下、セ
ンダー機構と呼ぶ)に搭載した後、このセンダー機構を
ウエハ配列ピッチ間隔で昇降例えば下降させて順次ウエ
ハをウエハ搬送腕により取出してウエハ搬送機構への移
載する。The wafer processing operation of this semiconductor manufacturing apparatus is performed by first mounting a wafer carrier in which a large number of semiconductor wafers are stacked and stored at predetermined intervals on a wafer loading mechanism (hereinafter, referred to as a sender mechanism) configured to be able to move up and down. Are moved up and down, for example, at wafer arrangement pitch intervals, and wafers are sequentially taken out by the wafer transfer arm and transferred to the wafer transfer mechanism.
そして予め記憶されている処理内容情報に基づいて半
導体ウエハを搬送機構により各処理機構へと搬送して一
連のプロセス処理を施す。Then, the semiconductor wafer is transported by the transport mechanism to each processing mechanism based on the processing content information stored in advance, and a series of process processing is performed.
処理済み半導体ウエハは、処理済みウエハを収容する
ウエハキャリアを搭載したウエハ搬出機構(以下、レシ
ーバ機構と呼ぶ)へと搬送されここで再びウエハ搬送腕
によりウエハ搬送機構からウエハキャリア内へと収容さ
れる。The processed semiconductor wafer is transported to a wafer unloading mechanism (hereinafter, referred to as a receiver mechanism) on which a wafer carrier for storing the processed wafer is mounted, where it is again stored by the wafer transport arm from the wafer transport mechanism into the wafer carrier. You.
このような半導体製造装置は半導体製造ラインの一部
として設けられており、作業の自動化を図るために、半
導体ウエハの品種や生産ロット種等に対応した処理内容
情報(以下、レシピ情報と呼ぶ)を予め装置制御部に記
憶し、半導体製造ライン側からの処理ウエハの品種情報
に対応するレシピ情報を選択して、一連の処理作業を自
動的に行えるように構成されている。Such a semiconductor manufacturing apparatus is provided as a part of a semiconductor manufacturing line, and in order to automate work, processing content information (hereinafter, referred to as recipe information) corresponding to a semiconductor wafer type, a production lot type, and the like. Is stored in advance in the apparatus control unit, and recipe information corresponding to the type information of the processed wafer from the semiconductor manufacturing line side is selected, so that a series of processing operations can be automatically performed.
(発明が解決しようとする課題) ところで、近年半導体製造プロセスでは多品種少量生
産化が進んでおり、少ロット生産例えば半導体ウエハ一
枚が1ロットである場合や、製造計画に割込み生産する
場合等、特殊な生産工程が多くなりつつあり、種々の生
産工程に柔軟に対応する必要がある。上述した上述の半
導体製造装置では、このような特殊生産に対応するため
には、半導体製造ライン側の生産計画を変更するか、半
導体製造装置をマニュアル操作する必要があり、一般的
には少ロット生産のために半導体製造ライン側の生産計
画を変更することは現実的ではないことからい、半導体
製造装置をマニュアル操作することで特殊生産に対応す
ることが行われている。しかしながら、マニュアル操作
では作業員が装置制御部に記憶されている多数のレシピ
情報の選択や組替え等の繁雑な操作を行わなければなら
ず、生産効率の低下、装置誤動作の原因となっていた。
このように従来の半導体製造装置では、多品種少量生産
化への対応が容易でないという問題があった。(Problems to be Solved by the Invention) In recent years, in the semiconductor manufacturing process, the production of many kinds and small quantities has been advanced, and the production of small lots, for example, when one semiconductor wafer is one lot, or when the production is interrupted by a production plan, etc. The number of special production processes is increasing, and it is necessary to flexibly cope with various production processes. In the above-described semiconductor manufacturing apparatus, in order to cope with such special production, it is necessary to change the production plan on the semiconductor manufacturing line side or manually operate the semiconductor manufacturing apparatus. Since it is not realistic to change the production plan on the semiconductor production line side for production, it is common to respond to special production by manually operating the semiconductor production equipment. However, the manual operation requires the operator to perform complicated operations such as selecting and changing a large number of pieces of recipe information stored in the apparatus control unit, which causes a reduction in production efficiency and a malfunction of the apparatus.
As described above, the conventional semiconductor manufacturing apparatus has a problem that it is not easy to cope with low-volume production of many kinds.
本発明は、上述した従来の問題点を解決するためにな
されたもので、被処理物の多品種少量生産への対応が容
易に行え、生産効率が向上する半導体製造装置を提供す
ることを目的とするものがある。SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to provide a semiconductor manufacturing apparatus which can easily cope with a wide variety of small-quantity production of an object to be processed and which improves production efficiency. There is something to say.
[発明の構成] (課題を解決するための手段) 本発明の半導体製造装置は、被処理物に予め定められ
た処理内容情報に基づいて処理を施す処理機構を複数配
置してなる処理装置ユニットと、 前記被処理物を前記各処理機構中選択された処理機構
に所定の手順で搬入・搬出する搬入・搬出機構とを有す
る半導体製造装置において、 前記被処理物の品種を識別する識別機構と、 前記被処理物の品種に対する処理内容情報を予め記憶
した記憶機構と、 前記識別した品種情報に対応する処理内容情報を前記
記憶機構から呼出す主制御部と、 前記主制御部によって前記記憶機構から呼出された前
記処理内容情報を受け、この処理内容情報に従って前記
搬入・搬出機構を制御し、前記被処理物を前記処理機構
に搬入・搬出する搬入・搬出機構制御部と、 前記主制御部によって前記記憶機構から呼出された前
記処理内容情報を受け、この処理内容情報に従って前記
処理機構を制御し、前記被処理物搬送機構によって搬入
された前記被処理物に処理を施す処理装置ユニット制御
部と を備えたことを特徴とするものである。[Structure of the Invention] (Means for Solving the Problems) A semiconductor manufacturing apparatus of the present invention is a processing apparatus unit in which a plurality of processing mechanisms for performing processing based on predetermined processing content information on an object to be processed are arranged. In a semiconductor manufacturing apparatus having a loading / unloading mechanism for loading / unloading the workpiece to a processing mechanism selected from among the processing mechanisms in a predetermined procedure, an identification mechanism for identifying a type of the workpiece. A storage mechanism in which processing content information for the type of the object to be processed is stored in advance; a main control unit that calls processing content information corresponding to the identified type information from the storage mechanism; Receiving the called processing content information, controlling the loading / unloading mechanism according to the processing content information, and loading / unloading mechanism control unit for loading / unloading the object to / from the processing mechanism; Receiving the processing content information called from the storage mechanism by the main control unit, controlling the processing mechanism according to the processing content information, and performing a process on the workpiece loaded by the workpiece transport mechanism And a processing unit control unit.
(作 用) 本発明は、予め記憶機構に被処理物の品種毎の処理内
容情報を記憶し、処理時に被処理物の品種を検出してこ
の品種に対応する処理内容を記憶機構から呼出し、呼出
した処理内容情報に基づいて処理装置ユニットおよび被
処理物搬送機構を制御する構成とすることで、被処理物
の多品種少量生産への対応が容易に行え、生産効率の向
上を図ることが可能となる。(Operation) According to the present invention, processing content information for each type of an object to be processed is stored in advance in a storage mechanism, the type of the object to be processed is detected at the time of processing, and the processing content corresponding to this type is called from the storage mechanism. By controlling the processing device unit and the processing object transport mechanism based on the called processing content information, it is possible to easily cope with high-mix low-volume production of the processing object and improve production efficiency. It becomes possible.
(実施例) 以下、本発明の半導体製造装置をレジスト塗布現像装
置に適用した一実施例を図面を参照して説明する。(Embodiment) An embodiment in which the semiconductor manufacturing apparatus of the present invention is applied to a resist coating and developing apparatus will be described below with reference to the drawings.
装置本体1の中央部付近には、被処理物例えば半導体
ウエハ2お保持例えば吸着保持するウエハ保持機構3を
搭載し、このウエハ保持機構3をX−Y−Z方向および
θ方向に移動させるウエハ搬送機構4が配設されてい
る。このウエハ搬送機構4は、例えばステッピングモー
タおよびこれに連結されたボールスクリュー等の回転駆
動機構(図示せず)によって移動、回転される。A wafer holding mechanism 3 for holding an object to be processed, for example, a semiconductor wafer 2, for example, by suction, is mounted near the center of the apparatus body 1, and a wafer for moving the wafer holding mechanism 3 in the XYZ direction and the θ direction. A transport mechanism 4 is provided. The wafer transfer mechanism 4 is moved and rotated by a rotation drive mechanism (not shown) such as a stepping motor and a ball screw connected thereto.
そして、このウエハ搬送機構4の一移動経路例えばX
移動経路5に沿って片側例えば図中上側には、夫々複数
のウエハ処理機構例えば半導体ウエハ2とレジスト膜と
の密着性を向上させるために行うHMDS処理機構6、半導
体ウエハ2上に塗布された第1層目のレジスト中に残存
する溶剤を加熱蒸発させるための第1のプリベーク機構
7、この第1のプリベーク機構7で加熱処理された半導
体ウエハ2を冷却する第1の冷却機構8が夫々順に並設
されており、一方、上記移動経路5の上記各ウエハ処理
機構7、8、9と対向する側には、半導体ウエハ2の上
面に第1層目のレジストを回転塗布する第1の塗布機構
9と、半導体ウエハ2の上面に第2層目のレジストを回
転塗布する第2の塗布機構10が順に並設されている。そ
してこれら各ウエハ処理機構6、7、8、9、10により
処理装置ユニット11が構成されている。尚、処理装置ユ
ニット11の一方側例えば図中右側は、処理工程に応じ
て、処理装置ユニット11と同様な他の処理装置ユニット
(図示せず)の増設が可能なように構成されている。Then, one movement path of the wafer transfer mechanism 4, for example, X
A plurality of wafer processing mechanisms, for example, an HMDS processing mechanism 6 for improving the adhesion between the semiconductor wafer 2 and the resist film, are coated on the semiconductor wafer 2 on one side, for example, the upper side in the figure along the movement path 5. A first pre-bake mechanism 7 for heating and evaporating the solvent remaining in the first-layer resist, and a first cooling mechanism 8 for cooling the semiconductor wafer 2 heated by the first pre-bake mechanism 7 are provided. On the other hand, on the side of the moving path 5 that faces the wafer processing mechanisms 7, 8, and 9, a first layer of resist is spin-coated on the upper surface of the semiconductor wafer 2. A coating mechanism 9 and a second coating mechanism 10 for spin-coating a second-layer resist on the upper surface of the semiconductor wafer 2 are arranged in order. Each of these wafer processing mechanisms 6, 7, 8, 9 and 10 constitutes a processing apparatus unit 11. One side of the processing unit 11, for example, the right side in the figure, is configured so that another processing unit (not shown) similar to the processing unit 11 can be added in accordance with a processing step.
処理装置ユニット11の一方側には、処理前の半導体ウ
エハ2を収納したウエハキャリア12を搭載したセンダー
機構13と、処理後の半導体ウエハ2を収納するウエハキ
ャリア14を搭載したレシーバ機構15と、半導体ウエハ2
を吸着保持してウエハキャリア14へ搬入またはキャリア
12から搬出するウエハ搬送腕16と、このウエハ搬送腕16
をX−Y−Zおよびθ方向に移動させる搬送腕駆動機構
17等から構成されるウエハ搬入・搬出機構17が配置され
ている。上記ウエハ搬送腕16によりウエハキャリア12か
らの処理前半導体ウエハ2の取出しおよびウエハキャリ
ア14への処理済み半導体ウエハ2の収納を行う。On one side of the processing unit 11, a sender mechanism 13 mounted with a wafer carrier 12 storing the semiconductor wafer 2 before processing, a receiver mechanism 15 mounted on a wafer carrier 14 storing the semiconductor wafer 2 after processing, Semiconductor wafer 2
And then carry it into the wafer carrier 14 or
A wafer transfer arm 16 to be unloaded from the
Arm driving mechanism for moving the camera in XYZ and θ directions
A wafer loading / unloading mechanism 17 composed of a component 17 and the like is arranged. The wafer transfer arm 16 takes out the unprocessed semiconductor wafer 2 from the wafer carrier 12 and stores the processed semiconductor wafer 2 in the wafer carrier 14.
また、搬送腕駆動機構17のX方向移動経路を挟んでウ
エハ搬入・搬出機構18と対向する位置には半導体ウエハ
2上に形成されている品種識別番号(以下、ID番号)を
検出するためのID検出機構19が配設されている。このID
読取り機構19の構成は、第2図に示すように、半導体ウ
エハ2上のID番号を読取るための画像認識機構等のIDリ
ーダー機構20と、半導体ウエハ2を搭載しIDリーダー機
構20と半導体ウエハのID番号形成部との位置併せを行う
ためのプリアライメント機構21と、これらIDリーダー機
構20とプリアライメント機構21の動作を制御するID読取
り機構制御部22から構成されている。A type identification number (hereinafter, ID number) formed on the semiconductor wafer 2 is detected at a position facing the wafer loading / unloading mechanism 18 with the X-direction movement path of the transfer arm driving mechanism 17 interposed therebetween. An ID detection mechanism 19 is provided. This ID
As shown in FIG. 2, the reading mechanism 19 has an ID reader mechanism 20 such as an image recognition mechanism for reading an ID number on the semiconductor wafer 2, and an ID reader mechanism 20 having the semiconductor wafer 2 mounted thereon. A pre-alignment mechanism 21 for aligning the position with the ID number forming section, and an ID reading mechanism control section 22 for controlling the operations of the ID reader mechanism 20 and the pre-alignment mechanism 21.
センダー機構13からウエハ搬送腕15により取出された
半導体ウエハ2は、このID読取り機構のプリアライメン
ト機構21上に移載されてプリアライメントされた後、ID
リーダ機構20により半導体ウエハ2上のID番号が読取ら
れる。The semiconductor wafer 2 taken out from the sender mechanism 13 by the wafer transfer arm 15 is transferred onto a pre-alignment mechanism 21 of the ID reading mechanism and pre-aligned.
The ID number on the semiconductor wafer 2 is read by the reader mechanism 20.
このような半導体製造装置の制御系の構成は、搬入・
搬出機構18の動作制御を行う搬入・搬出機構制御部31、
処理装置ユニット11の各処理機構6、7、8、9、10お
よびウエハ搬送機構4を制御する処理装置ユニット制御
部32、ID読取り機構制御部22、これら各制御部22、31、
32に所定の処理手順情報例えば搬送系の搬送手順やプリ
ベーク機構の設定温度条件等の情報からなる処理内容情
報であるレシピ情報を送信する主制御部33により構成さ
れている。上記レシピ情報は、予めレシピ記憶部34に記
憶されており、レシピ制御部35がレシピ記憶部34に記憶
された多数のレシピ情報A、B、……から処理すべき半
導体ウエハ2に対応するレシピ情報を選択し、該レシピ
情報を主制御部33へ出力するように構成されている。The configuration of the control system of such a semiconductor manufacturing device is
A loading / unloading mechanism control unit 31, which controls the operation of the loading / unloading mechanism 18,
The processing unit control section 32, the ID reading mechanism control section 22, and the control sections 22, 31, which control the processing mechanisms 6, 7, 8, 9, 10 and the wafer transfer mechanism 4 of the processing apparatus unit 11, respectively.
The main control unit 33 transmits to the processing information 32 recipe information which is processing content information including predetermined processing procedure information, for example, information such as a transport procedure of a transport system and a set temperature condition of a pre-bake mechanism. The recipe information is stored in the recipe storage unit 34 in advance, and the recipe control unit 35 calculates the recipe corresponding to the semiconductor wafer 2 to be processed from the large number of pieces of recipe information A, B,. It is configured to select information and output the recipe information to the main control unit 33.
以下にこのような構成の半導体製造装置の処理動作に
ついて第3図のフローチャートを参照して説明する。The processing operation of the semiconductor manufacturing apparatus having such a configuration will be described below with reference to the flowchart of FIG.
まず、搬入・搬出機構制御部31によりウエハ搬送腕15
を駆動制御してセンダー機構13に搭載されているウエハ
キャリア12から所定の半導体ウエハ2を取出し(10
1)、ID読取り機構19のプリアライメント機構21へと該
半導体ウエハ2を移載する(103)。こうしてID読取り
機構19の動作が開始される(102)。この後、IDリーダ
機構20と半導体ウエハ2上のID番号形成部とのプリアラ
イメトを行い(104)、このID番号の読取りを行い(10
5)、読取ったID情報を主制御部33へと送信する(10
6)。この後、半導体ウエハ2は再びウエハ搬送腕16に
より保持されてID読取り機構19外へと搬送される(10
7)。こうして、ID読取り機構18での動作が終了する(1
08)。First, the loading / unloading mechanism controller 31 controls the wafer transfer arm 15.
Is controlled to take out a predetermined semiconductor wafer 2 from the wafer carrier 12 mounted on the sender mechanism 13 (10
1) The semiconductor wafer 2 is transferred to the pre-alignment mechanism 21 of the ID reading mechanism 19 (103). Thus, the operation of the ID reading mechanism 19 is started (102). Thereafter, pre-alignment between the ID reader mechanism 20 and the ID number forming section on the semiconductor wafer 2 is performed (104), and the ID number is read (10).
5), and transmits the read ID information to the main control unit 33 (10)
6). Thereafter, the semiconductor wafer 2 is again held by the wafer transfer arm 16 and transferred out of the ID reading mechanism 19 (10).
7). Thus, the operation of the ID reading mechanism 18 is completed (1.
08).
この後、半導体ウエハ2は搬入・搬出機構18のウエハ
載置台23へと移載されて位置合せされた後(301)、こ
の後ウエハ搬送機構4のウエハ保持機構3により保持さ
れて予め定めらえた作業手順に従って各処理機構へと搬
送され(302)、処理機構内で所定の処理が施される(3
03)。Thereafter, the semiconductor wafer 2 is transferred to the wafer mounting table 23 of the loading / unloading mechanism 18 and aligned (301), and thereafter, held by the wafer holding mechanism 3 of the wafer transport mechanism 4 and set in advance. Is transported to each processing mechanism according to the work procedure obtained (302), and predetermined processing is performed in the processing mechanism (3).
03).
一方、主制御部33へと送信されたID情報はレシピ制御
部35へと送信され(201)、該レシピ制御部35にてレシ
ピ記憶部34に記憶されているレシピ情報A、B、……か
らこのID情報に対応するレシピ情報を選択する(20
2)。こうして選択されたレシピ情報は、再び主制御部3
5へ送信されて(203)、搬入・搬出機構31および処理装
置ユニット制御部32へと送信される(204)。On the other hand, the ID information transmitted to the main control unit 33 is transmitted to the recipe control unit 35 (201), and the recipe information A, B,... Stored in the recipe storage unit 34 by the recipe control unit 35. Select the recipe information corresponding to this ID information from (20
2). The recipe information thus selected is stored in the main control unit 3 again.
5 (203), and then to the loading / unloading mechanism 31 and the processing unit control unit 32 (204).
搬入・搬出機構31および処理装置ユニット制御部32で
は該受信したレシピ情報に基づいて一連の処理例えば上
述したウエハ載置台23のアライメント動作(301)、半
導体ウエハの搬送(302)、一連のプロセス処理(303)
の制御を行う。こうして、処理の終了した半導体ウエハ
2は再びウエハ搬送機構4により搬入・搬出機構18へと
搬送されレシーバ機構15のウエハキャリアへ14内へ収容
される(304)。The loading / unloading mechanism 31 and the processing unit control unit 32 perform a series of processing based on the received recipe information, for example, the above-described alignment operation (301) of the wafer mounting table 23, transfer of the semiconductor wafer (302), and a series of processing. (303)
Control. Thus, the processed semiconductor wafer 2 is transported again by the wafer transport mechanism 4 to the loading / unloading mechanism 18 and stored in the wafer carrier 14 of the receiver mechanism 15 (304).
このように、半導体ウエハ2に形成されたID番号に対
応するレシピ情報を予め記憶し、処理時に処理すべき半
導体ウエハ2のID番号を読取り、このID番号に対応した
レシピ情報を読出して、該読出したレシピ情報に基づい
て一連の処理動作を制御するように構成することで、割
込み生産や少ロット生産を行う場合でも、半導体製造ラ
イン側の生産計画の変更やマニュアル操作の必要がな
く、一連の処理を全自動で行うことができ、多品種少量
生産化にも容易に対応することができ、かつ生産効率の
向上が図れる。As described above, the recipe information corresponding to the ID number formed on the semiconductor wafer 2 is stored in advance, the ID number of the semiconductor wafer 2 to be processed at the time of processing is read, and the recipe information corresponding to this ID number is read. By configuring so that a series of processing operations are controlled based on the read recipe information, even if interrupt production or small lot production is performed, there is no need to change the production plan on the semiconductor manufacturing line side or perform manual operations. Can be performed fully automatically, it is possible to easily cope with low-volume, high-mix production, and the production efficiency can be improved.
[発明の効果] 以上説明したように、本発明の半導体製造装置によれ
ば、多品種少量生産化への対応が容易に行え、生産効率
の向上を図ることが可能となる。[Effects of the Invention] As described above, according to the semiconductor manufacturing apparatus of the present invention, it is possible to easily cope with low-volume, high-mix production, and to improve production efficiency.
【図面の簡単な説明】 第1図は本発明を半導体製造装置をレジスト塗布現像装
置に適用した一実施例を示す構成図、第2図は実施例の
制御系の構成を示す図、第3図は実施例の動作を説明す
るためのフローチャート図である。 1……装置本体、2……半導体ウエハ、3……ウエハ保
持機構、4……ウエハ搬送機構、6、7、8、9、10…
…処理機構、11……処理装置ユニット、12、14……ウエ
ハキャリア、13……センダー機構、15……レシーバ機
構、16……搬送腕、18……搬入・搬出機構、19……ID読
取り機構、20……IDリーダ機構、21……プリアライメン
ト機構、22……ID読取り機構制御部、31……搬入・搬出
機構制御部、32……処理装置ユニット制御部、33……主
制御部、34……レシピ記憶部、35……レシピ制御部。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment in which the present invention is applied to a resist coating and developing apparatus using a semiconductor manufacturing apparatus, FIG. 2 is a view showing a control system of the embodiment, FIG. FIG. 5 is a flowchart for explaining the operation of the embodiment. DESCRIPTION OF SYMBOLS 1 ... Device main body, 2 ... Semiconductor wafer, 3 ... Wafer holding mechanism, 4 ... Wafer transfer mechanism, 6, 7, 8, 9, 10 ...
Processing mechanism, 11 Processing unit, 12, 14 Wafer carrier, 13 Sender mechanism, 15 Receiver mechanism, 16 Transfer arm, 18 Loading / unloading mechanism, 19 ID reading Mechanism 20 ID reader mechanism 21 Pre-alignment mechanism 22 ID reading mechanism control section 31 Loading / unloading mechanism control section 32 Processing unit control section 33 Main control section , 34... Recipe storage unit, 35... Recipe control unit.
フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 H01L 21/30 502J Continued on the front page (51) Int.Cl. 6 Identification number Agency reference number FI Technical display location H01L 21/30 502J
Claims (1)
基づいて処理を施す処理機構を複数配置してなる処理装
置ユニットと、 前記被処理物を前記各処理機構中選択された処理機構に
所定の手順で搬入・搬出する搬入・搬出機構とを有する
半導体製造装置において、 前記被処理物の品種を識別する識別機構と、 前記被処理物の品種に対する処理内容情報を予め記憶し
た記憶機構と、 前記識別した品種情報に対応する処理内容情報を前記記
憶機構から呼出す主制御部と、 前記主制御部によって前記記憶機構から呼出された前記
処理内容情報を受け、この処理内容情報に従って前記搬
入・搬出機構を制御し、前記被処理物を前記処理機構に
搬入・搬出する搬入・搬出機構制御部と、 前記主制御部によって前記記憶機構から呼出された前記
処理内容情報を受け、この処理内容情報に従って前記処
理機構を制御し、前記被処理物搬送機構によって搬入さ
れた前記被処理物に処理を施す処理装置ユニット制御部
と を備えたことを特徴とする半導体製造装置。A processing unit for arranging a plurality of processing mechanisms for performing processing on a processing target based on predetermined processing content information; and a processing mechanism selected from the processing mechanisms for the processing target. A semiconductor manufacturing apparatus having a loading / unloading mechanism for loading / unloading the workpiece in a predetermined procedure, an identification mechanism for identifying a type of the workpiece, and a storage mechanism for preliminarily storing processing content information for the type of the workpiece. A main control unit for calling processing content information corresponding to the identified type information from the storage mechanism; receiving the processing content information called from the storage mechanism by the main control unit; A loading / unloading mechanism control unit for controlling the unloading mechanism and loading / unloading the processing object into / from the processing mechanism; and the processing called from the storage mechanism by the main control unit. And a processing unit control section for controlling the processing mechanism in accordance with the processing content information and processing the workpiece carried in by the workpiece transport mechanism. Manufacturing equipment.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63320281A JP2627796B2 (en) | 1988-12-19 | 1988-12-19 | Semiconductor manufacturing equipment |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63320281A JP2627796B2 (en) | 1988-12-19 | 1988-12-19 | Semiconductor manufacturing equipment |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH02164017A JPH02164017A (en) | 1990-06-25 |
JP2627796B2 true JP2627796B2 (en) | 1997-07-09 |
Family
ID=18119752
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63320281A Expired - Lifetime JP2627796B2 (en) | 1988-12-19 | 1988-12-19 | Semiconductor manufacturing equipment |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2627796B2 (en) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06105737B2 (en) * | 1990-12-14 | 1994-12-21 | 日鉄セミコンダクター株式会社 | Wafer lot number automatic reader |
US5927512A (en) | 1997-01-17 | 1999-07-27 | Micron Technology, Inc. | Method for sorting integrated circuit devices |
US6100486A (en) | 1998-08-13 | 2000-08-08 | Micron Technology, Inc. | Method for sorting integrated circuit devices |
US5844803A (en) | 1997-02-17 | 1998-12-01 | Micron Technology, Inc. | Method of sorting a group of integrated circuit devices for those devices requiring special testing |
US5915231A (en) | 1997-02-26 | 1999-06-22 | Micron Technology, Inc. | Method in an integrated circuit (IC) manufacturing process for identifying and redirecting IC's mis-processed during their manufacture |
US5856923A (en) | 1997-03-24 | 1999-01-05 | Micron Technology, Inc. | Method for continuous, non lot-based integrated circuit manufacturing |
US7120513B1 (en) | 1997-06-06 | 2006-10-10 | Micron Technology, Inc. | Method for using data regarding manufacturing procedures integrated circuits (ICS) have undergone, such as repairs, to select procedures the ICS will undergo, such as additional repairs |
US5907492A (en) | 1997-06-06 | 1999-05-25 | Micron Technology, Inc. | Method for using data regarding manufacturing procedures integrated circuits (IC's) have undergone, such as repairs, to select procedures the IC's will undergo, such as additional repairs |
US6049624A (en) | 1998-02-20 | 2000-04-11 | Micron Technology, Inc. | Non-lot based method for assembling integrated circuit devices |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2541544B2 (en) * | 1987-04-14 | 1996-10-09 | 株式会社日立製作所 | Semiconductor manufacturing equipment |
-
1988
- 1988-12-19 JP JP63320281A patent/JP2627796B2/en not_active Expired - Lifetime
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Publication number | Publication date |
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JPH02164017A (en) | 1990-06-25 |
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