JP2626527B2 - Digital video signal processing method and processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing method for a digital video signal recording / reproducing apparatus using high-efficiency encoding when inputting / outputting a digital signal in a state of high-efficiency encoding.

[0002]

2. Description of the Related Art In recent years, recording and reproducing equipment using digital recording has been put into practical use in place of conventional analog recording as consumer image equipment has been improved in image quality and digitized. However, for example, a 4: 2: 2 component signal has a very high transmission rate of 216 Mbps, so that long-time recording cannot be realized if recording is performed as it is. Therefore, in order to obtain sufficient recording time for consumer use, it is necessary to efficiently reduce the amount of information of an image to such an extent that an allowable image quality can be obtained by a high-efficiency encoding technique. The following describes a digital recording VT as a recording / reproducing apparatus for a digital video signal using high efficiency coding
The configuration and operation will be described by taking R (hereinafter, referred to as a digital VTR) as an example.

FIG. 16 is a block diagram showing a configuration of a conventional digital VTR using high efficiency coding. FIG.
In 6, reference numeral 1 denotes an input terminal of a video signal, 2 denotes an A / D converter for converting an analog signal into a digital signal, 3 denotes a high efficiency coding circuit, 4 denotes an error correction coding circuit, 5 denotes a modulation circuit, and a recording amplifier. , A recording amplifier 6, and a magnetic tape 7. 8 is a head amplifier, 9 is a reproduction processing circuit for detecting and demodulating a reproduction signal, 10 is an error correction decoding circuit for correcting errors in the reproduction signal based on an error correction parity added at the time of recording, and 11 is error correction. An error correction circuit for correcting an error that could not be corrected by the decoder; 12, a high-efficiency decoding circuit for decoding high-efficiency coded data into original data; 13, an analog signal for decoding the decoded data; D / A converter for converting to 1
Reference numeral 4 denotes an output terminal for a reproduced video signal. The operation will be described below.

At the time of recording, a video signal input from a terminal 1 is converted into a digital signal by an A / D converter 2 and is encoded by a high-efficiency encoding circuit 3 to be compressed to a predetermined data amount. Next, a parity for error correction is added by the error correction coding circuit 4, a synchronization signal and identification information (ID) are added to form a recording block (hereinafter referred to as a synchronization block), and the recording processing circuit 5 , And amplify it by the recording amplifier 6 and record it on the tape. FIG. 17 is a diagram showing the configuration of a synchronous block, where 100 is a synchronous signal for detecting a synchronous block from a reproduced signal, 101 is a track number, a synchronous block number, and the like for correctly writing the reproduced synchronous block to a memory. , ID is data obtained by encoding a video signal with high efficiency, and 103 is an error correction parity (Inner parity) added in units of synchronous blocks. The synchronous block configured as described above is arranged on the track and recorded on the tape.

At the time of reproduction, a reproduced signal is amplified by a head amplifier 8 and a reproduction processing circuit 9 detects and demodulates a synchronous block. Then, an error correction decoding circuit 10 corrects an error correction signal added at the time of recording. Error correction is performed based on the parity. Here, if a large dropout occurs due to, for example, a scratch on the tape, the error exceeds the correction capability, so that it is impossible to correct the error.
When such an uncorrectable error occurs, the error correction circuit 11 performs correction so that the influence of the error is visually suppressed as little as possible. The modified data is sent to the high-efficiency decoding circuit 1
2, the data is decoded into original data, converted into an analog signal by the D / A converter 13, and output from the output terminal 14 as a video signal.

In digital recording, data strings of 0 and 1 are recorded.
And 1 are erroneously detected. Here, if the error rate is equal to or less than a predetermined value, the error can be corrected by the error correction technique. Therefore, by setting the correction capability appropriately for the error rate of the reproduced data, completely correct data can be obtained. It is possible to play. Therefore, for analog recording in which distortion increases and deterioration accumulates due to repeated recording and reproduction, dubbing (connecting multiple devices and inputting and reproducing signals output and output from one device to the other device) Is a major feature of digital recording. In particular, in the case of dubbing in a digital signal state without going through analog processing (digital dubbing), it is possible to further suppress signal deterioration.

FIG. 18 is a diagram showing a method of digital dubbing between two digital VTRs, wherein 200 is a digital VTR on the reproducing side, 201 is a digital VTR on the recording side, 202 and 203 are digital interface circuits, and 204 Is digital dubbing data to be transmitted. First, the output signal of the high-efficiency decoding circuit 10 is input from the digital VTR 200 to the digital interface circuit 202, formatted into a transmission format, and output to the outside as digital dubbing data 204. Next, in the digital VTR 200,
The input digital dubbing data 204 is converted back to a digital video signal format by the digital interface circuit 203, high-efficiency encoding is performed again by the high-efficiency encoding circuit 3, and a series of recording processes are performed to obtain data on the tape. Record

[0008]

However, the conventional configuration described above has the following problems.

As a method for encoding a video signal with high efficiency,
Orthogonal transform coding is widely used in terms of compression efficiency. The orthogonal transformation is a method of collecting a plurality of pixels into blocks, and converting the blocks into a frequency domain in block units. When orthogonal transformation is performed on a video signal, energy tends to be concentrated on low frequency components, so that data can be efficiently compressed by performing encoding according to the energy distribution. Here, since the processes of the orthogonal transform and the inverse transform are actually performed with a finite word length, arithmetic errors accumulate and the distortion increases by repeating the transform and the inverse transform.
In addition, when filter processing such as thinning and interpolation is performed, distortion is similarly increased by repeating the filter processing. Therefore, despite the fact that digital recording has less deterioration due to dubbing than analog recording, distortion increases each time digital dubbing is performed, and the image quality after dubbing several times is higher than the original image quality. The deterioration may be so large that it can be visually recognized.

In view of the above-mentioned problems of the prior art, the present invention suppresses an increase in deterioration due to digital dubbing and correctly reproduces data after dubbing in a digital video signal recording / reproducing apparatus using high efficiency coding. It is an object of the present invention to provide a method of processing a digital video signal which can be performed.

[0011]

SUMMARY OF THE INVENTION The present invention relates to a processing method for generating a recording block by blocking a digital video signal which has been coded with high efficiency and performing recording and reproduction. Digital video information, wherein decoding information indicating whether or not data of the recording block in which the error correction has been performed maintains continuity with another recording block is added to the recording block. method of processing signals, and high-efficiency encoded de
Create recording block by blocking digital video signal
In the processing device for performing recording and reproduction, the recording block
When a lock is erroneously corrected during playback,
The data of the recording block performed is replaced with another recording block.
Decryption information indicating whether or not continuity with the
It should have at least means for adding to the recording block.
And a digital video signal processing device.

[0012]

[0013]

[0014]

According to the digital signal processing method of the present invention, a digital video signal using high efficiency coding is recorded and reproduced.
At this time, an error correction process is performed at the time of reproduction, an error correction process is performed on a recording block having an uncorrectable error, and error correction information indicating that the recording block having the error correction has been corrected is multiplexed. Also, by modifying some of the recording blocks, there is a possibility that the continuity of highly efficient encoded data may be lost. Are multiplexed together and output. In addition, the present invention
A digital signal processor for storing data of the recording block;
Whether continuity with other recording blocks is maintained
Means for adding decoding information shown to the recording block
High efficiency marks that have lost continuity due to
Recognize encoded data and continuously connect discontinuous information
Data from dubbing by preventing
Deterioration can be prevented.

[0015]

[0016]

[0017]

Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a block diagram showing the configuration of a digital VTR for realizing a digital video signal processing method according to an embodiment of the first invention. In FIG.
Reference numeral 300 denotes a reproduction-side digital VTR; 301, an error correction decoding circuit; 302, a flag indicating the presence of an error in a synchronous block unit; 303, an error correction memory having a capacity of one page; and 304, a correction memory. 303, a memory control circuit for supplying address and control signals; 305, a high-efficiency decoding circuit; 306, a digital interface circuit for performing digital dubbing in a state of high-efficiency encoding; 307, digital dubbing data to be output; 308 is a digital VTR on the recording side, and 309 is a digital interface circuit for digital dubbing.

Before describing the operation of the present embodiment, a high-efficiency encoding method in the present embodiment will be described. FIG.
FIG. 4 is a block diagram showing a configuration of a high-efficiency encoding unit at the time of recording, where 400 is a memory for blocking, 401 is an orthogonal transformation operation circuit that performs orthogonal transformation, 402 is a quantization circuit, 403 is a variable length encoding circuit, Reference numeral 404 denotes a memory for inserting variable-length encoded data into a synchronization block.

First, digitized input signals are sequentially written to the memory 400 and read out in block units. Here, in order to perform the high-efficiency encoding in units of a predetermined number of blocks, data is read from the memory 400 in units of a predetermined number of blocks (compressed block units), and a code in which the data amount becomes constant in compressed block units. Perform the conversion.
In the memory 400, the screen is divided into five regions, and four blocks of luminance signals and two blocks of color difference signals (RY:
By reading out one block (BY: one block), a compressed block composed of 30 blocks is formed.
Here, the number of horizontal pixels of the chrominance signal is half of the luminance signal, and the number of vertical pixels of the chrominance signal is reduced to 信号 of the luminance signal by thinning out in the line direction. Therefore, four blocks of luminance signals and one block of each of two types of color difference signals have the same position and area on the screen, and are collectively referred to as a macroblock. That is, one compressed block is composed of five macro blocks.

Next, an orthogonal transform operation is performed on each block by an orthogonal transform operation circuit 401, quantized by a quantization circuit 402, and then variable-length encoded by a variable-length encoding circuit 403. The quantization is controlled so that the variable-length coded data is always a fixed amount in compressed block units.
The data is written to the memory 404 in units of compressed blocks. FIG.
FIG. 4 is a diagram showing an order in which coefficients after orthogonal transformation in a case where one block is 8 pixels × 8 lines are subjected to variable-length coding,
The shaded portion 500 is a DC component, and 501 is an AC component. As shown in FIG. 3, zigzag encoding is performed in order from the low-order component of the AC component corresponding to the low-frequency component with the DC component at the head. The memory 404 divides the variable-length coded data into five synchronous blocks, inserts the data, and outputs the divided data.

FIG. 4 is a diagram showing a method of inserting variable-length coded data into five synchronization blocks. Data 600, 601 and
602, 603, and 604 are replaced by 605, 606, and 60, respectively.
7, 608 and 609 are inserted into the corresponding synchronization blocks. Here, since the information amount of each macroblock is different, there are cases where the data amount of one macroblock exceeds or is less than the data amount that can be inserted into the corresponding synchronization block. Therefore, the data (hatched portion) overflowing from the corresponding synchronous block in the data of each macro block is inserted into the surplus area of each synchronous block. By configuring the synchronization block as described above,
One synchronous block corresponds to data of one macro block, and if one synchronous block can be reproduced, the corresponding macro block can be reproduced. In addition, since data that overflows from one synchronous block and is inserted into another synchronous block corresponds to a high-frequency component of each block, even if such data is lost, no particularly significant deterioration in image quality occurs.

A reproduction process for reproducing data recorded after performing the above-described high-efficiency encoding process will be described with reference to FIG. The error correction decoding circuit 301 corrects a correctable error based on the error correction parity added at the time of recording. The flag 302 is a flag indicating the presence of an error in a synchronous block unit, and is set to “1” when there is an uncorrectable error in the synchronous block, and is set to “0” when there is no error. Next, the output of the error correction decoding circuit 301 and the flag 302 are input to the correction memory 303, and error correction processing is performed. The error correction process performs an operation of using the correction memory 303 to replace an error synchronous block with a corresponding synchronous block one page before. Such a modification operation is realized by writing only correct synchronization blocks to the modification memory 303 and prohibiting writing to the modification memory 303 of an erroneous synchronization block. The flag 302 is used for writing to the modification memory 303.
Is controlled by the memory control circuit 304 in accordance with the result of the detection. Therefore, the modified synchronization block is output from the modification memory 303.

Here, the retouching memory 303 multiplexes retouching information and information (decoding information) for high-efficiency decoding with respect to each retouched synchronous block. FIG. 5 is a diagram showing the configuration of a synchronous block in which these pieces of information are multiplexed.
00 is information indicating a quantization method, 701 is modification information, 70
2 is decoding information, and 703 is highly efficient encoded data. The modification information 701 is represented by 2 bits, and the decoding information 702 is represented by 1 bit, and is defined as shown in (Table 1).

[0025]

[Table 1]

Hereinafter, the information multiplexed in each synchronous block will be specifically described. The modification information 701 is a flag for indicating whether or not the synchronous block has been modified. The flag is set to “00” when the synchronous block has not been modified, and is set to other than “00” when the synchronous block has been modified. Here, by allocating two bits to the modification information, a detailed modification method as shown in (Table 1) can be represented. Next, when there is data overflowing from another synchronous block in the synchronous block, the decoding information 702 indicates whether or not the data can be used for decoding. Becomes possible. The decoding information 702 is set as follows according to the modification pattern of the synchronization block constituting one compression block. (1) When a part of synchronous blocks is modified For example, when one synchronous block is erroneous in one compressed block, the erroneous synchronous block is replaced with a corresponding synchronous block one page before. Here, there is a possibility that data of another macro block in which another synchronous block overflows in the error synchronous block. Since such data is lost due to the modification and cannot be used for decoding, the decoding information is set to "1". (2) When all five synchronous blocks are modified When all the five synchronous blocks constituting the compressed block are erroneous due to a burst error or the like, the five synchronous blocks are replaced with the corresponding synchronous blocks one page before. in this case,
The decoding information is set to "0" for the five synchronization blocks. The high-efficiency decoding circuit 305 can decode all data of each synchronous block.

FIG. 6 (a) shows a block 5 constituting a compression block.
FIG. 6 is a diagram showing additional information of each synchronous block when only one of the synchronous blocks is modified, and the configuration of the synchronous block is the same as that shown in FIG. First, the modified information 701 is set to “01” and the decoded information 702 is set to “1” for the modified synchronous block 800. For the other synchronous blocks 801 to 804, the modification information 701 is set to “00” and the decoding information 702 is set.
Is set to “0”. When the high-efficiency decoding circuit 305 detects that the decoding information 702 of the synchronization block 800 is "1", it decodes only the data of the macroblock corresponding to each synchronization block and overflows from other synchronization blocks. Do not decrypt data.

FIG. 6 (b) shows the structure of the compressed block 5
FIG. 13 is a diagram illustrating additional information of each synchronous block when all the synchronous blocks are modified.
For 809, the modification information 701 is set to "01" and the decryption information 702 is set to "0".

As described above, the data of each synchronous block which is multiplexed with the additional information and output from the modification memory 303 is:
The video signal is decoded into the original video signal by the high-efficiency decoding circuit 305 and is output to the digital interface circuit 306 at the same time. The digital interface circuit 306 formats the data in the highly efficient encoded state into a format for transmission, and then outputs it as digital dubbing data 307 to the outside. At this time, the above-mentioned modification information 701 and decoding information 702 are output in a state where they are multiplexed in each synchronous block. On the other hand, the recording digital VTR 3 to which the digital dubbing data 307 is input is used.
In step 08, after the digital interface circuit 309 solves the transmission format, the error correction encoding circuit 4
Add parity for error correction. Subsequently, the recording processing circuit 5 performs a recording process to record data on the tape. Therefore, when the dubbed data is reproduced next, it is possible to correctly decode the data of each synchronous block based on the decoding information 702.

As described above, according to this embodiment, decoding information is multiplexed to each synchronous block in which error correction processing has been performed and error correction has been performed in a highly efficient coded state. The data of each synchronous block can be correctly decoded by the efficiency decoding circuit. Further, at the time of digital dubbing in the high-efficiency encoding state, the corrected data is always dubbed and recorded, so that erroneous data is not recorded on the tape. further,
Even when the dubbed data is reproduced again, it is possible to correctly decode the data of each synchronous block based on the decoding information.

FIG. 7 is a block diagram showing a configuration of a digital VTR for realizing a digital video signal processing method according to one embodiment of the second invention. 7, reference numeral 900 denotes a reproduction-side digital VTR; 901, an error correction decoding circuit; 902, a high-efficiency decoding circuit; 903, an error flag in units of macroblocks; and 904, an error correction with a capacity of one page. And a memory control circuit 905 for supplying an address and a control signal to the retouching memory 904.

In the above-described embodiment of the first invention, the modification information and the decoding information are defined as additional information for performing the modification in the state of the highly efficient encoding. However, the error correction processing is not limited to being performed in the high-efficiency encoding state, and may be performed after decoding the high-efficiency encoded data. Therefore, in this embodiment, after the high-efficiency decoding, the error correction processing is performed using the correction memory 904 having a capacity of one page. Since an error flag is necessary for performing error correction in the correction memory 904, the error flag and the above-described decoded information are multiplexed for each synchronous block. FIG. 8 is a diagram showing a configuration of a synchronous block in which these pieces of information are multiplexed, and 1000 is an error flag. Each of the error flag 1000 and the decoding information 702 is represented by one bit, and is defined as shown in (Table 2). The setting method of the decryption information 702 is the same as that described above.

[0033]

[Table 2]

The error flag 1000 is a flag for indicating whether or not an error exists in the synchronous block. The error flag 1000 is set to “0” when no error exists, and is set to “1” when an error exists. Is done. Therefore, when the correction function in the high efficiency coding state is not provided as in the present embodiment, the error flag 1000
Is set to “1”. For a recording block in which an error exists, data overflowing from another synchronous block cannot be used for decoding, so that the decoding information 702 is also set to “1”. FIG. 9A is a diagram showing additional information of each synchronous block when an error is present in one of the five synchronous blocks constituting the compressed block. First, for the synchronous block 1100 in which an error exists, the error flag 1000 is set to “1”, and the decoding information 702 is set to “1”.
Set to. Further, other synchronization blocks 1101 to 110
For No. 4, the error flag 1000 is set to “0” and the decoding information 702 is set to “0”. FIG. 9B is a diagram showing additional information of each synchronous block in a case where an error exists in all five synchronous blocks constituting the compressed block.
0 is set to “1”, and the decryption information 702 is set to “1”.

The above additional information is sent to an error correction decoding circuit 90.
1 is set in accordance with the error correction processing result. The data of each synchronous block output from the error correction decoding circuit 901 after the additional information is multiplexed is decoded by the high efficiency decoding circuit 902 into the original video signal. The high-efficiency decoding circuit 902 determines an erroneous macroblock based on the multiplexed error flag 1000 and supplies an error flag 903 for each macroblock to the memory control circuit 905. The memory control circuit 905 controls writing of data to the retouching memory 904 in accordance with the error flag 903, writes only correct macroblocks to the retouching memory 904, and prohibits writing of error macroblocks to the retouching memory 904. .

Further, an error flag 10 is set for each synchronous block.
The data in the high-efficiency encoding state in which 00 and the decoding information 702 are multiplexed is formatted into a transmission format by the digital interface circuit 306, and then output to the outside as digital dubbing data 307. The processing of the recording digital VTR 308 is the same as that described in the first embodiment of the present invention. Therefore, when the dubbed data is reproduced next, the error flag 100
It is possible to modify the synchronization block in which 0 is set to "1" and to correctly decode the data of each synchronization block based on the decoding information 702.

As described above, according to the present embodiment, the error correction function in the high efficiency coding state is achieved by multiplexing the error flag and the decoding information with respect to each of the synchronous blocks subjected to the error correction processing. , And can cope with a case where error correction is performed after high-efficiency decoding. Also, at the time of digital dubbing in the high efficiency coding state, an error flag is multiplexed and recorded on an error synchronous block, so that
When the dubbed data is reproduced next time, error correction can be performed with reference to the error flag. In addition,
When error correction is performed in the highly efficient encoding state, correction information cannot be set, but the error flag is always set to “0”.
Thus, it is possible to set the decoding information according to the modification method.

FIG. 10 is a diagram showing a configuration of a synchronous block in which additional information is multiplexed in the digital signal processing method according to the first embodiment of the third invention. In FIG. 10, 1200 is 1-bit additional information commonly used for the decoded information and the error flag. The modification information 701 and the additional information 1200 are each defined as shown in (Table 3), and the setting of the additional information 1200 is switched according to the modification information 701. Hereinafter, a method of setting the additional information 1200 will be described.

First, when the modification information 701 is "00",
The additional information 1200 is used as an error flag. The modification information 701 is set to “00” when no error modification has been performed, and the state of the synchronous block at this time includes a case where no error exists in the synchronous block and a case where an error exists in the synchronous block. It can be classified into two cases, that is, the case where it has not been modified. Therefore, the error flags are set for each of these two cases as shown in (Table 3).

[0040]

[Table 3]

Next, when the modification information 701 is other than "00", the additional information 1200 is used as decoding information. The modification information 701 is set to a value other than “00” when an error modification process has been performed on a recording block. After the modification, there is no error, so it is meaningless to define an error flag. Conversely, data that overflows from other synchronous blocks cannot be decoded due to modification, so decoding information is defined as shown in Table 3 instead of the error flag.

FIG. 11 is a block diagram showing the configuration of a digital VTR for realizing a digital video signal processing method according to the first embodiment of the third invention. FIG.
, 1300 is a digital VTR on the reproduction side, 13
Reference numeral 01 denotes a correction memory for error correction having a capacity of one page, reference numeral 1302 denotes a memory control circuit for supplying addresses and control signals of the correction memory 1301, and reference numeral 1303 denotes a high-efficiency decoding circuit.

The data and the flag 302 that have been corrected by the error correction decoding circuit 301 are stored in the modification memory 130.
1. The error correction processing is performed by being input to each of the memory control circuits 1302. Here, the retouching memory 1301 multiplexes the retouching information 701 and the decoding information 1200 with respect to the retouched synchronous block. In addition, the modification information 701 and the error flag 1200 for the synchronous block that has not been modified.
Multiplex.

FIG. 12A is a diagram showing additional information of each synchronous block when only one synchronous block is modified. For the modified synchronous block 1400, modification information 701 is set to "01", The decryption information 1200 is set to "1"
Set to. For other synchronization blocks 1401 to 1404, the modification information 701 is set to “00” and the error flag 1200 is set.
Is set to “0”. FIG. 12B is a diagram showing additional information of each synchronous block when all the five synchronous blocks constituting the compressed block have been modified, and the modification information 701 is set to "0" for the synchronous blocks 1405 to 1409.
The decryption information 702 is set to "0".

As described above, the data of each synchronization block output from the modification memory 1301 after the additional information is multiplexed is decoded into the original video signal by the high-efficiency decoding circuit 305 and output. It is input to the interface circuit 306. The digital interface circuit 306 formats the data in the highly efficient encoded state into a format for transmission, and then outputs it as digital dubbing data 307 to the outside. At this time, the modified information 701 and the error flag 1200 for the modified synchronous block, and the modified information 701 and the decoded information 1200 for the unmodified synchronous block are output in a state multiplexed in each synchronous block. Recording side digital VT
The processing of R308 is the same as that described in the first and second embodiments, and when the dubbed data is reproduced next, the data of each synchronous block is correctly decoded based on the decoding information 702. It is possible to

As described above, according to this embodiment, by selecting an error flag and decoding information according to the presence or absence of error correction and multiplexing the same as additional information in each synchronous block, the amount of data to be multiplexed does not increase and It is possible to cope with both cases in which error correction is performed in a state of high efficiency coding and cases in which error correction is not performed. Further, at the time of digital dubbing in the high efficiency encoding state, an error flag or decoding information is always dubbed and recorded. Therefore,
When reproducing the dubbed data again, there is no problem that the erroneous data is decoded and output as it is.

FIG. 13 is a diagram showing a configuration of a synchronous block in which modification information and additional information are multiplexed in the digital signal processing method according to the second embodiment of the third invention. In FIG. 13, reference numeral 1400 denotes STATUS information in which the modification information and the additional information are represented by a 4-bit code. The detailed contents of the STATUS information are defined as shown in (Table 4). Here, in (Table 3), the modification information is represented by 2 bits and the additional information is represented by 1 bit.
In Table 4, both the modification information and the additional information are represented by 4 bits.

[0048]

[Table 4]

FIG. 14 is a block diagram showing a configuration of a digital video signal processing method according to the second embodiment of the third invention. In FIG. 14, 1500 is a digital VTR on the reproduction side, 1501 is a correction memory having a capacity of one page for error correction, and 1502 is a correction memory 1501.
A memory control circuit for supplying an address and a control signal to the memory 1503, a delay memory 1504 for delaying data of five synchronization blocks, a STATUS information setting circuit 1504, and a STATUS information 1505 set by the STATUS information setting circuit 1504 , 1506 is STATUS
An information multiplexing circuit 1507 is a high-efficiency decoding circuit.

The data and flag 302 that have been corrected by the error correction decoding circuit 301 are stored in the modification memory 150.
1. Each is input to the memory control circuit 1502, and error correction processing is performed. Next, the data read from the modification memory 1501 is written to the delay memory 1503 in units of five synchronous blocks constituting a compression block. STA
The TUS information setting circuit 1504 sets the flags 302 for the five synchronous blocks written in the delay memory 1503.
Is detected, and 4-bit STATUS information 1505 is set. Then, the STATUS information multiplexing circuit 1506 multiplexes the STATUS information 1505 at the head of each synchronous block read from the delay memory 1503.

FIG. 15A shows STATUS information set in each synchronous block when only one of the five synchronous blocks constituting the compression block is modified in the present embodiment. It is. First, the STATUS information is set to “1010” for the modified synchronization block 1600. Another synchronous block 1
STATUS for 601 to synchronization block 1604
The information is set to “0000”. FIG. 15B shows the STATU of each synchronous block when all five synchronous blocks constituting the compressed block in this embodiment are modified.
FIG. 10 is a diagram showing S information, and STATUS information is set to “001” for the synchronization blocks 1605 to 1609.
Set to "0".

As described above, the data of each synchronous block in which the STATUS information is multiplexed is supplied to the high-efficiency decoding circuit 15.
At 07, the video signal is decoded into the original video signal based on the STATUS information and output, and at the same time, is input to the digital interface circuit 306. The digital interface circuit 306 formats the data in the highly efficient encoded state into a format for transmission, and then outputs it as digital dubbing data 307 to the outside. At this time, the STATUS information is output in a state where it is multiplexed in each synchronization block.

As described above, according to the present embodiment, more information on the synchronous block can be represented by coding the modification information, the information on decoding, and the error flag together as 4-bit STATUS information. Is possible.

In the three embodiments described above, one macroblock corresponds to one synchronization block. However, a plurality of macroblocks and a plurality of synchronization blocks can be associated. It is.

[0055]

As described above, according to the present invention, in a digital signal recording / reproducing apparatus using high efficiency coding, it is possible to suppress an increase in deterioration due to digital dubbing in a high efficiency coding state. And it becomes possible to correctly reproduce the data after dubbing.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a digital VTR for implementing a digital video signal processing method according to an embodiment of the present invention;

FIG. 2 is a block diagram illustrating a configuration of a high-efficiency encoding unit during recording.

FIG. 3 is an explanatory diagram showing an order in which coefficients after orthogonal transformation are subjected to variable-length coding;

FIG. 4 is an explanatory diagram showing a method of inserting variable-length encoded data into five synchronization blocks.

FIG. 5 is an explanatory diagram showing a configuration of a synchronous block in which modification information and decoded information are multiplexed according to the first invention;

FIG. 6 is an explanatory diagram showing a setting method of modification information and decoding information when a synchronous block is modified according to the first invention;

FIG. 7 is a block diagram showing a configuration of a digital VTR for realizing a digital signal processing method according to an embodiment of the second invention;

FIG. 8 is an explanatory diagram showing a configuration of a synchronous block in which an error flag and decoded information are multiplexed according to the second invention.

FIG. 9 is an explanatory diagram showing a method for setting an error flag and decoding information when an error exists in a synchronous block according to the second invention;

FIG. 10 shows modification information of the first embodiment according to the third invention,
Explanatory drawing showing the configuration of a synchronous block in which error flags or decoding information is multiplexed

FIG. 11 is a digital VTR for realizing the digital video signal processing method of the first embodiment according to the third invention.
Block diagram showing the configuration of

FIG. 12 is an explanatory diagram showing a method of setting modification information, an error flag, or decoding information when a synchronous block is modified in the first embodiment according to the third invention;

FIG. 13 is a STATU of the second embodiment according to the third invention.
Explanatory diagram showing the configuration of a synchronous block in which S information is multiplexed

FIG. 14 shows a digital VTR for realizing a digital video signal processing method according to a second embodiment of the present invention.
Block diagram showing the configuration of

FIG. 15 is an explanatory diagram showing a method of setting STATUS information when a synchronous block is modified in the second embodiment according to the third invention;

FIG. 16 shows a conventional digital VT using high efficiency coding.
Block diagram showing the configuration of R

FIG. 17 is an explanatory diagram showing a configuration of a synchronization block.

FIG. 18 is a block diagram showing a method of digital dubbing between two digital VTRs.

[Explanation of symbols]

301, 901 Error correction decoding circuit 302 Error flag 303, 1301, 1501 Modified memory in high efficiency coding state 904 Modified memory after high efficiency decoding 305, 902, 1507 High efficiency decoding circuit 306, 309 Digital interface circuit 307 Digital dubbing data 701 Modification information 702 Decoding information 703 High-efficiency encoded data 1000 Error flag 1200 Additional information 1400 STATUS information 1504 STATUS information setting circuit 1505 STATUS information multiplexing circuit

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical display location H04N 7/24 H04N 7/13 A

Claims (5)

(57) [Claims] 1. A digital video signal which has been encoded with high efficiency.
Generates recording blocks by dividing into blocks, and performs recording and playback.
In the processing method, when the recording block is erroneously corrected during reproduction, the
The data of the recording block where the error correction has been performed
Indicates whether or not continuity with the recording block is maintained
Decoding information is added to the recording block.
Digital video signal processing method . 2. A digital video signal which has been encoded with high efficiency.
Generates recording blocks by dividing into blocks, and performs recording and playback.
In the processing method, it is indicated whether or not the recording block has been corrected for error during reproduction.
Error correction information and the record in which the error correction was performed
Block data maintains continuity with other recording blocks
And decryption information indicating whether or not
Digital video signal processing method characterized by addition
Law . 3. A set of data comprising error correction information and decoding information.
3. The digit according to claim 2, wherein
How to process video signals . 4. A digital video signal which has been encoded with high efficiency.
Generates recording blocks by dividing into blocks, and performs recording and playback.
In the processing device, when the recording block is error-corrected during reproduction, the
The data of the recording block where the error correction has been performed
Indicates whether or not continuity with the recording block is maintained
At least means for adding decryption information to the recording block
Digital video signal processing device characterized by having
Place . 5. A digital video signal which has been encoded with high efficiency.
Generates recording blocks by dividing into blocks, and performs recording and playback.
The processing device indicates whether the recording block has been error-corrected during reproduction.
Error correction information and the record in which the error correction was performed
Block data maintains continuity with other recording blocks
And decryption information indicating whether or not
Characterized by having at least means for adding
Digital video signal processing device .