JP2626045B2 - Semiconductor integrated circuit device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device capable of realizing a high output withstand voltage and a high output current in a normal complementary MOS integrated circuit manufacturing process. General I such as micro processor unit and MCU (micro controller unit)
5V (V _CC ) power supply used in C and high voltage (V
_DD ), a semiconductor integrated circuit device requiring a high current.

[Conventional technology]

FIG. 3 shows a semiconductor integrated circuit device conventionally used when a high output withstand voltage and a high output current are required while reducing power consumption and the output voltage is to be changed.
This is a semiconductor integrated circuit device configured by a so-called Bi-CMOS using a bipolar transistor as an output transistor as a MOS transistor.

In this figure, (1) is an input terminal, and a complementary MO
Connected to the gate of the S transistor. (2)
Is a multi-stage complementary MOS composed of a P-channel MOS transistor (3) and an N-channel MOS transistor (4).
Transistors (5) and (6) are the final stage P
They are a channel MOS transistor and an N channel MOS transistor. (7) is an output voltage changing power supply. (13
b) is a bipolar transistor that responds to the complementary MOS transistor in the final stage, and the emitter is at GND potential (17).
The collector is connected to the output terminal (14). (15)
Is a current limiting resistor. (16) is a light emitting element diode (LED), the anode of which is a power supply for output voltage change (7)
On the (+) side, the cathode is connected to a current limiting resistor (15).

Next, the operation of the semiconductor integrated circuit will be described. Since the complementary MOS transistor (2) of the plurality of stages has a complementary MOS transistor structure, a high output current cannot be obtained. For this reason, a bipolar transistor (13b) is used as the output transistor, and a high output current is obtained by the output voltage changing power supply (7). The operation is such that when the outputs of the complementary MOS transistors (2) in a plurality of stages are at "H", the bipolar transistor (13b) generates a voltage sufficient to turn on between the base and the emitter and turns on. As a result, the output current flows from the output voltage changing power supply (7), and the LED (16) is turned on. On the other hand, when the outputs of the complementary MOS transistors (2) in a plurality of stages are "L", the bipolar transistor (13b) is turned off.
However, the LED (16) does not light.

[Problems to be solved by the invention]

The conventional semiconductor integrated circuit device has a structure as shown in FIG.
-There is a problem that the CMOS structure has a complicated structure and a high production cost.

However, a high output current cannot be expected from a plurality of stages of complementary MOS transistors (2) in a normal CMOS process, and if the withstand voltage is increased, the current gain decreases and an output current cannot be obtained.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems. A high output current can be obtained by a normal CMOS process.

・ Can drive circuits with high output current and high output withstand voltage at various input levels.

It is another object of the present invention to provide a semiconductor integrated circuit device.

[Means for solving the problem]

A semiconductor integrated circuit device according to the present invention is connected between a first power supply potential node to which a first power supply potential higher than a ground potential is applied and a first intermediate output node, and has a gate electrode connected to an input terminal. Connected and the back gate electrode is
P-channel MOS transistor connected to a second power supply potential node to which a second power supply potential higher than the power supply potential is applied, and a gate electrode connected between the first intermediate output node and the ground potential node Is connected to the input terminal and the back gate electrode is connected to the ground potential node.
An input circuit having a channel MOS transistor; a level conversion circuit for converting the level of an output appearing at the first intermediate output node to output to a second intermediate output node; a source electrode and a back gate connected to a second power supply potential node P-channel MOS transistor to which an electrode is connected, and this P-channel M
A complementary N-channel MOS transistor is connected between the drain electrode of the OS transistor and the ground potential node, has a gate electrode connected to the gate electrode of the P-channel MOS transistor, and has a back gate electrode connected to the ground potential node. Control in which a plurality of type MOS transistors are cascaded, an input of a first-stage complementary MOS transistor is connected to a second intermediate output node, and an output of a last-stage complementary MOS transistor is connected to a third intermediate output node A circuit, a vertical npn transistor having a collector electrode connected to the second power supply potential node, an emitter electrode connected to the output terminal, and a base electrode connected to the third intermediate output node; and an output terminal connected to the ground potential And an output circuit having an N-channel MOS transistor connected to the node.

[Operation] In the present invention, a P-channel constituting an input circuit is provided.
Since the back gate bias is applied to the MOS transistor at the second power supply potential, the threshold voltage of the input circuit driven by the first power supply potential can be set low by configuring the N-channel MOS transistor. Vertical type that constitutes the circuit
An npn transistor can be formed in a manufacturing process of P and N channel MOS transistors constituting an input circuit and a control circuit, and is constituted by a plurality of cascade-connected complementary MOS transistors controlling the vertical npn transistor. Since the back-channel bias is applied to the P-channel MOS transistor constituting the complementary MOS transistor in the control circuit to be applied at the second power supply potential, a high breakdown voltage is obtained, that is, the transistor can be driven even at the second power supply potential. A control circuit is obtained, and the output from the input circuit is given to this control circuit via the level conversion circuit.
High output power can be supplied to the output terminal from the n transistor.

〔Example〕

FIG. 1 shows an embodiment of a semiconductor integrated circuit device according to the present invention. In this figure, (1) is an input terminal to which an input signal is input, and (8) is applied with a first power supply potential Vcc (for example, 5 V) from a Vcc power supply (hereinafter, referred to as a first power supply). A source portion (source electrode) is connected to the first power supply potential node (10), a drain portion (drain electrode) is connected to the first intermediate output node, and a gate portion (gate electrode) is connected to the input terminal (1). ) Is connected to the second power supply potential V _DD which is higher than the first power supply potential Vcc.
Power supply for output voltage change (for example, 20V) (7)
(V _DD power, hereinafter referred to as a second power source) P-channel MOS which the second power supply potential node to a bulk portion of the second power supply potential V _DD from is applied (back gate electrode) is connected
It is a transistor.

(9) The source portion (source electrode) is connected to the ground potential node which is set to the ground potential GND (17), and the drain portion (drain electrode) is connected to the first intermediate output node.
Are connected, a gate portion (gate electrode) is connected to the input terminal (1), and a bulk portion (back gate electrode) is connected to the ground potential node. The P-channel MOS transistor and the N-channel MOS transistor constitute an input circuit that outputs a signal based on the signal input to the input terminal (1) to the first intermediate output node.

Since the second power supply potential higher than the first power supply potential is applied as the back gate bias of the P-channel MOS transistor (8), the first power supply potential is applied as the back gate bias of the P-channel MOS transistor. However, the threshold voltage (threshold voltage) of the P-channel MOS transistor (8) is increased, and the threshold voltage (threshold voltage) of the input circuit can be reduced. As a result, as a signal input to the input terminal (1), for example, a CMOS level (generally, an H level is about 4.0 V, an L level is about 0.8 V, and about 2.5 V is required as a threshold voltage of an input circuit) TTL level (generally, the H level is about 2.0 V, the L level is about 0.8 V, and the threshold voltage of the input circuit is about 1.3 V). ) Can be used, and it can correspond to various input levels.

(11) a level conversion circuit for level-converting the output of the first power supply system (Vcc power supply system) to the input of the second power supply system ( _VDD power supply system), which appears at the first intermediate output node The output is level-converted and output to the second intermediate output node.

(2) P-channel MOS transistors (3) and (5) in which a source portion (source electrode) and a bulk portion (back gate electrode) are connected to the second power supply potential node, and the P-channel MOS transistor (3) The gate portion (gate electrode) is connected between the drain portion (drain electrode) of (5) and the ground potential node and the gate portion (gate electrode) of the P-channel MOS transistor (3) (5). N-channel MOS transistors (4) and (6) having a bulk portion (back gate electrode) connected to the ground potential node are connected in cascade in a plurality of stages, and the first stage complementary MOS transistor (3) The input of (4) is connected to the second intermediate output node (corresponding to the output node of the level conversion circuit), and the final stage complementary MOS transistors (5) (6) A control circuit output is connected to the third intermediate output node. These P
Since a back gate bias is applied to the channel MOS transistors (3) and (5) at the second power supply potential, a high withstand voltage can be obtained. Therefore, the control circuit (2) can be driven by the second power supply potential, and as its output, changes the H level to the second power supply potential (more precisely, the second power supply potential) in accordance with the output from the level conversion circuit (11). 2 minus the threshold voltage of the P-channel MOS transistor (5)) and the L level to the ground potential (more precisely, the N-channel MOS to the ground potential).
(The value obtained by adding the threshold voltage of the transistor (6)).

(13a) is the collector part (collector electrode)
Power supply potential node ((+) side of the second power supply (7))
A vertical npn transistor having an emitter portion (emitter electrode) connected to the output terminal (14) and a base electrode connected to the third intermediate output node (corresponding to the output node of the control circuit (2)). is there. This vertical npn transistor has a substrate (n) as shown in the sectional structural view of FIG.
(Type) as a collector portion, a well (p-type) as a base portion, and an n ⁺ diffusion layer formed in the well as an emitter portion. Therefore, it can be formed by the manufacturing process of the P and N channel MOS transistors constituting the input circuit and the control circuit described above. In addition, since the collector portion is connected to the second power supply potential, the substrate constituting the collector portion has the second power supply potential, but a reverse potential is applied to the junction surface forming the PN junction with the substrate. That is, there is no adverse effect on the P and N channel MOS transistors constituting the input circuit and the control circuit.

(12) is connected between the output terminal (14) and the ground potential node and has a gate electrode connected to the control circuit (2).
Is an N-channel MOS transistor connected to the input of the complementary MOS transistors (5) and (6) at the final stage and having a bulk portion (back gate electrode) connected to the ground potential node. The vertical npn transistor (13a) And the output circuit is configured to turn on and off in reverse to the on / off operation of the vertical npn transistor (13a). When the vertical npn transistor (13a) is off, the potential of the output terminal (14) is set to the ground potential and stable. This is used as a pull-down for conversion.

(15) is a current limiting resistor having one end connected to the output terminal (14), and (16) is an LED having an anode connected to the current limiting resistor and a cathode connected to the ground potential node.
It is.

Next, the operation of this embodiment will be described. In the semiconductor integrated circuit device configured as described above, for example,
Assuming that an L-level signal at the TTL level is input to the input terminal 1, an output from an input circuit composed of P and N-channel MOS transistors (8) and (9)
That is, the potential of the first intermediate output node is equal to the first power supply Vc
An H-level signal based on the c-system is output. At this time,
P-channel MOS transistor constituting an input circuit (8)
Since the back gate bias is given by the second power supply V _DD (7), the threshold voltage of the P-channel MOS transistor (8) is high and the threshold voltage of the input circuit is low. For example, a TTL level signal is accurately and accurately distinguished between an L level and an H level and output.

An H-level signal from the input circuit based on the first power supply Vcc system is supplied to a second power supply Vcc by a level conversion circuit (11).
The signal is level-converted to an H-level signal based on the _DD system.
, Ie, the input node of the control circuit (2).

In the control circuit (2), its output node, ie, the third
, Output a signal corresponding to the H-level signal input to the input node, in this example, a level signal. That is, the last-stage P-channel MOS transistor (5) constituting the control circuit (2) turns on, and the N-channel MOS transistor (6) turns off. As a result, the base potential of the second power supply potential is applied from the second power supply potential node to the base electrode of the vertical npn transistor (13a) via the P-channel MOS transistor (5). At this time, the P-channel MOS transistors (3) and (5) constituting the control circuit (2) are driven by the second power supply V _DD (7), and the second power supply V _{DD is used} as the back gate bias.
Since it is provided by (7), a circuit with a high withstand voltage is obtained as the control circuit (2).

The vertical npn transistor (13a) is connected to the second power supply V
_Since the base potential is given via the P-channel MOS transistor (5) by the _DD (7), the base is sufficiently turned on, and a high output current is supplied from the second power supply V _DD (7) to the output terminal (14). The LED (16) is caused to flow through the LED (16) via the limiting resistor (15), and the LED (16) is turned on.

At this time, the N-channel MOS transistor (12)
Is given an L level as a gate potential,
Off.

On the other hand, for example, if an H level signal at the TTL level is input to the input terminal 1, the P and N channel MO
As the output from the input circuit constituted by the S transistors (8) and (9), that is, the potential of the first intermediate output node, an L-level signal based on the first power supply Vcc system is output.

An L-level signal from the input circuit based on the first power supply Vcc system is supplied to the second power supply Vcc by the level conversion circuit (11).
The signal is level-converted into an L-level signal based on the _DD system (both are ground potentials) and input to a second intermediate output node, that is, an input node of the control circuit (2).

In the control circuit (2), its output node, ie, the third
, Outputs a signal corresponding to the L-level signal input to the input node, in this example, an L-level signal. That is, the last-stage P-channel MOS transistor (5) constituting the control circuit (2) is turned off, and the N-channel MOS transistor (6) is turned on. As a result, the base potential of the vertical npn transistor (13a) is set to the potential of the ground potential node via the N-channel MOS transistor (6).

Therefore, the vertical npn transistor (13a) is turned off.
The LED (16) is turned off to cut off the current supply to the LED (16).

At this time, the N-channel MOS transistor (12)
Is given an H level as a gate potential,
On, the potential of the output terminal (14) is set to the potential of the ground potential node, and the potential of the output terminal (14) is stabilized.

In the semiconductor integrated circuit device configured as described above,
Since an output circuit is formed and a vertical npn transistor is used as a transistor for flowing a high output current, the P and N channel MOS transistors (3) to (8) and (12) forming the input circuit and the control circuit are used. It can be formed by a manufacturing process, is easy to manufacture, and connects a collector electrode formed of an N-type substrate to a second power supply potential node with a p-type diffusion layer forming a pn junction with the substrate. A voltage in the opposite direction is always applied between them, and there is no adverse effect on other circuit elements, especially on p-channel MOS transistors.

The P-channel MOS transistor (8) constituting the input circuit is driven by the first power supply Vcc (for example, 5 V) and is supplied with the back gate bias by the second power supply V _DD (7) (for example, 20 V). P-channel MOS
The threshold voltage of the transistor (8) is high, and the threshold voltage of the input circuit can be set low. Even if the signal input to the input terminal (1) is, for example, a TTL level signal, the L level and the H level are reliably and accurately determined. The output can be distinguished from the level.

Since the P-channel MOS transistors (3) and (5) constituting the control circuit (2) are provided with a back gate bias at the second power supply potential, a high withstand voltage is obtained, and the control circuit (2) is connected to the second circuit. It can be driven by the power supply potential. As a result, the control circuit (2) that has received the output from the input circuit operating on the first power supply Vcc system via the level conversion circuit (11),
The power supply operates at the power supply V _DD system, and a high output current can flow from the vertical npn transistor (13a) to the output terminal (14).

In the above embodiment, the vertical npn transistor (13a) is used as the output transistor, but a pnp transistor may be used, and the same effect can be obtained.

〔The invention's effect〕

As described above, the present invention relates to the first power supply potential node to which the first power supply potential higher than the ground potential is applied and the first power supply potential node.
, The gate electrode is connected to the input terminal, and the back gate electrode is connected to a second power supply potential node to which a second power supply potential higher than the first power supply potential is applied. P-channel MOS transistor,
An input circuit having an N-channel MOS transistor connected between the first intermediate output node and the ground potential node, having a gate electrode connected to the input terminal, and a back gate electrode connected to the ground potential node; A level conversion circuit for level-converting the output appearing at the first intermediate output node and outputting the output to the second intermediate output node; and a P-type transistor having a source electrode and a back gate electrode connected to the second power supply potential node.
A channel MOS transistor, connected between the drain electrode of the P-channel MOS transistor and a ground potential node, a gate electrode connected to the gate electrode of the P-channel MOS transistor, and a back gate electrode connected to the ground potential node A complementary MOS transistor having an N-channel MOS transistor is cascaded in a plurality of stages,
A control circuit having an input of the first-stage complementary MOS transistor connected to the second intermediate output node and an output of the last-stage complementary MOS transistor connected to the third intermediate output node;
A vertical npn transistor having a collector electrode connected to the second power supply potential node, an emitter electrode connected to the output terminal, and a base electrode connected to the third intermediate output node; Since an output circuit having an N-channel MOS transistor connected between them is provided, the threshold voltage of the input circuit driven by the first power supply potential can be set low, and the MPU (microprocessor unit) and the MCU ( Micro control unit), etc.
This has the effect of being able to be used together with a commonly used semiconductor integrated circuit device driven by a power supply of 5 V (Vcc), and the vertical npn transistor constituting the output circuit is composed of P and P constituting the input circuit and the control circuit. N channel
It has the effect that it can be formed in the manufacturing process of the MOS transistor, and has a high breakdown voltage as a P-channel MOS transistor constituting a complementary MOS transistor in the control circuit, that is, it can be driven even at the second power supply potential This has an effect that a control circuit can be obtained.

In other words, according to the present invention, even if a vertical npn transistor that can be formed in a manufacturing process of P and N channel MOS transistors is used as a transistor constituting an output circuit for obtaining a high output current, a signal from the first power supply system is used. This has an effect that a semiconductor integrated circuit device which can receive an input signal and output a high output current can be obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of a semiconductor integrated circuit device according to the present invention. FIG. 2 is a sectional structural view of the vertical npn transistor of FIG. Fig. 3 shows a conventional Bi-CM
FIG. 2 is a circuit configuration diagram illustrating a semiconductor integrated circuit device having an OS configuration. In the figure, (2) is a plurality of stages of complementary MOS transistors, (7) is a power supply for output voltage change, (8) is a P-channel MOS transistor having a back gate bias applied to a bulk portion, and (11) is a power supply V _CC. A circuit for level-converting the output of the system to the output of the power supply _VDD system, (13a) is a vertical npn transistor. The same reference numerals in the drawings indicate the same or the same parts.

──────────────────────────────────────────────────続 き Continuation of the front page (51) Int.Cl. ⁶ Identification number Agency reference number FI Technical display location H03K 19/0948 (56) References JP-A-53-87187 (JP, A) JP-A-62 123826 (JP, A) JP-A-63-299161 (JP, A) JP-B-69225 (JP, B2) JP-B-56-7331 (JP, B2) JP-B-60-4619 (JP, B2)

Claims (1)

(57) [Claims] A ground potential node to which a ground potential is applied; a first potential to which a first power supply potential higher than the ground potential is applied;
A power supply potential node; a second power supply potential node to which a second power supply potential higher than the first power supply potential is applied; an input terminal to which an input signal is input; an output terminal to output an output signal; A P-channel MOS transistor connected between a power supply potential node and a first intermediate output node, a gate electrode connected to the input terminal, and a back gate electrode connected to the second power supply potential node; First
An N-channel MOS transistor connected between the intermediate output node and the ground potential node and having a gate electrode connected to the input terminal and a back gate electrode connected to the ground potential node; A level conversion circuit for converting the level of an output appearing at the first intermediate output node to output the output to a second intermediate output node; a P-channel MOS transistor having a source electrode and a back gate electrode connected to the second power supply potential node Connected between the drain electrode of the P-channel MOS transistor and the ground potential node, the gate electrode is connected to the gate electrode of the P-channel MOS transistor, and the back gate electrode is connected to the ground potential node.
A complementary MOS transistor having a channel MOS transistor is connected in cascade at a plurality of stages, an input of the first stage complementary MOS transistor is connected to the second intermediate output node, and an output of the last stage complementary MOS transistor is connected to the third stage. A control circuit connected to the intermediate output node; a vertical line having a collector electrode connected to the second power supply potential node, an emitter electrode connected to the output terminal, and a base electrode connected to the third intermediate output node. Type np
A semiconductor integrated circuit device including an output circuit having an n-transistor and an N-channel MOS transistor connected between the output terminal and the ground potential node.