JP2625482B2 - Multi-screen video display - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-screen moving image display device capable of simultaneously monitoring a large number of moving image planes.

[Conventional technology]

2. Description of the Related Art Conventionally, in a television receiver, a VTR, and the like, various applied functions have been added using a memory. As one example, as disclosed in "Television Technology" May 1986, pp. 19-24, another moving image is set as a sub-screen in a part of a parent screen of a moving image displayed on the entire monitor. Generally, a picture-in-picture function, a function of sampling a video signal of each broadcast channel every few seconds, and displaying these as a still image on a multi-screen are common.

[Problems to be solved by the invention]

However, in the case of the picture-in-picture function,
The displayed moving image is based on a video signal from one tuner and a video signal reproduced from a VTR, and is intended for two signal sources.

Although the above multi-screen display function is intended for a large number of signal sources, these are selected in order by one tuner, and are displayed only as a still image, and are displayed as moving images. Can not be displayed as For this reason, it is only possible to roughly grasp the contents of each channel, and simultaneous viewing of each channel is unexpected.

In the surveillance system, video cameras are installed at various places so that each place can be monitored. Conventionally, a monitor is provided for each video camera, or one monitor is provided. Video cameras are sequentially switched using one monitor. However, in the former case, there is a problem that the whole system becomes large and expensive, and in the latter case, the monitoring is missed.

SUMMARY OF THE INVENTION An object of the present invention is to provide a multi-screen moving image display device which can solve the above problem and can simultaneously display moving image planes using a plurality of asynchronous moving image signals.

[Means for solving the problem]

In order to achieve the above object, the present invention provides a time axis reducing unit that reduces the screen of each of the moving image signals that are asynchronous with each other according to a set reduction ratio, a background signal generating unit, and the video signal and the background signal. Switching means for selecting any one of the following: a synchronizing means for outputting a moving image signal whose image has been reduced from the time axis reducing means in a predetermined phase relationship with an output signal of the switching means; and an output of the switching means. A signal synthesizing means for inserting and synthesizing the signal and the moving picture signal whose screen has been reduced from the time axis reducing means from a signal source different from the output signal.

[Action]

The time axis reducing means reduces the time axis of the moving picture signal for each field or every other field, and the time axis is reduced by the synchronizing means so as to have a predetermined phase relationship with the output signal of the switching means. Output each field. As a result, the position at which the image-reduced moving image signal is fitted to the output signal of the switching means is fixed, and the image-reduced moving image signal is fitted one field at a time for each field of the output signal of the switching means. A plurality of small screens are displayed at the same time as moving images.

When the switching means selects the background signal and when one of the moving picture signals is selected, the reduction ratio is made different, whereby the mode for displaying the screen based on the moving picture signal with the same size and the mode using the moving picture signal are selected. It is possible to select a mode in which one of the screens is taken as a large shot and the other is a small screen.

〔Example〕

 Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a multi-screen moving image display apparatus according to the present invention, wherein reference numerals 1 to 4 are input terminals, 5 is a background signal generation circuit, 6 to 9 are time axis reduction circuits, and 10 to 13. Is a memory, 14 is a switching switch, 15 to 18 are field synchronization circuits, 19 is a reduction ratio control circuit, 20 to 23 are signal synthesis circuits, 24 is an output terminal, 25 to 28 are open / close switches, and 29 is a switch control circuit. is there.

In this embodiment, a case will be described in which screens based on video signals from four signal sources are simultaneously displayed on a monitor.
Here, these video signals are referred to as A, B, C, and D, respectively, a display screen based on the video signal A is denoted by A, and similarly, the video signals B, C, and D are displayed.
Are displayed as B, C, and D, respectively. FIGS. 2A and 2B show examples of multi-screen display of these screens. Fig. 2 (a)
Is an example in which the contents of the four screens A, B, C, and D are to be viewed evenly. These are divided into small screens on the monitor M with respect to the background BS on the monitor M. . FIG. 2 (b) shows one of these screens (eg, screen C).
Is to be focused on, the screen to be focused on is enlarged on the entire monitor M, and the other screens are displayed as small screens. In the case of the display example shown in FIG. 2A, a portion of the monitor M excluding the screens A, B, C, and D is used as a background BS, and the background portion BS is, for example, a suitable solid color such as blue or green. Color screen.

In FIG. 1, the reduction ratio control circuit 19 includes a reduction ratio r for determining the size of each of the screens A, B, C and D so that the multi-screen display shown in FIGS. 2 (a) and 2 (b) can be performed. (<1) is set. In the case of the multi-screen display shown in FIG.
The reduction ratio r is set to about 1/2, and in the case of the multi-screen display shown in FIG. 2B, the reduction ratio r is set to about 1/3 to 1/4.

First, a case where a multi-screen display is performed as shown in FIG. 2A will be described. In this case, the reduction ratio r is set to about 1/2 as described above.

Video signals A, B, C, and D are input to input terminals 1, 2, 3, and 4, respectively. These are supplied to time axis reduction circuits 6, 7, 8, and 9, respectively. The video signals A, B, C, D and the background signal BS output from the background signal generation circuit 5 are both supplied to the switching switch 14. In this case, the switching switch 14 selects and outputs the background signal BS.

The time axis reduction circuit 6 writes and reads the video signal A in the memory 10 under the control of the field synchronization circuit 15. The ratio between the writing speed and the reading speed in the memory 10 is determined by the reduction ratio r set in the reduction ratio control circuit 19, and the size of the screen A in FIG. . That is, assuming that the cycle of the write clock in the memory 10 is T _W and the cycle of the read clock is T _R , Is set to As a result, the vertical and horizontal length of the screen A on the monitor becomes r times the entire monitor. In the case of the display example of FIG. 2A, since r = 1/2, the screen A
Is half the length of the monitor M. The writing clock of the memory 10 is synchronized with the synchronizing signal of the input video signal A, and the reading clock is synchronizing with the synchronizing signal of the output signal of the switching switch 14 (in this case, the background signal BS).

The timing of reading from the memory 10 is controlled by the field synchronization circuit 15 so that the screen A is displayed on the monitor M at the position shown in FIG. Memory 10
Is faster than the writing speed, but the field synchronization circuit 15 also controls the time axis reduction circuit 6 so that the reading position in the memory 10 does not overtake the writing position. To perform such control, the video signal A and the background signal BS output from the switching switch 14 are supplied to the field synchronization circuit 15. Further, the number of horizontal scanning lines per field of the video signal A is also reduced to the reduction ratio r times.

The above is the reduction processing for the video signal A, but the same applies to the video signals B, C, and D. That is, the video signal B
, The time axis reduction circuit 7, the memory 11, and the field synchronization circuit 16 perform reduction processing so that the screen B is displayed in the size and position shown in FIG. Is reduced by the time axis reduction circuit 8, the memory 12, and the field synchronization circuit 17 so that the screen C is displayed at the size and position shown in FIG.
The video signal D is reduced by the time axis reduction circuit 9, the memory 13, and the field synchronization circuit 18 so that the screen D is displayed in the size and position shown in FIG.
The field synchronization circuit 16 receives the video signal B and the background signal BS output from the changeover switch 14, the field synchronization circuit 17 receives the video signal C and the background signal BS, and the field synchronization circuit 18 receives the video signal B and the background signal BS. D and the background signal BS are supplied respectively.

It goes without saying that in the memories 10 to 13, the video signal is reduced and read out one field at a time for each field of the background signal BS.

In this way, the reduced video signals A ', B', C ', D' are output from the time base reduction circuits 6, 7, 8, 9 in synchronization with the background signal BS. These video signals A 'to D' do not include a synchronizing signal or a burst signal, and are composed of video signals. The video signal A 'passes through the opening / closing switch 25, and is synthesized by the signal synthesizing circuit 20 with the background signal BS output from the switching switch 14. The video signal B 'passes through the opening / closing switch 26 and is synthesized by the signal synthesizing circuit 21 with the output signal of the signal synthesizing circuit 20. The video signal C 'passes through the opening / closing switch 27 and is synthesized by the signal synthesizing circuit 22 with the output signal of the signal synthesizing circuit 21. The video signal D 'passes through the opening / closing switch 28 and is synthesized by the signal synthesis circuit 23 with the output signal of the signal synthesis circuit 22.

Here, the switching switch 14 and the opening / closing switches 25 to 28 are controlled by the switch control circuit 29 as follows. That is, the output signal of the switching switch 14 is closed with a predetermined phase relationship so that the screen A by the video signal A 'is displayed in the positional relationship shown in FIG. Extract the minutes. The opening / closing switches 26 to 28 operate in the same manner with respect to the video signals B 'to D'. The switching switch 14 outputs the background signal BS only when all of the open / close switches 25 to 28 are open. Therefore, the background signal BS output from the switching switch 14 is missing during the period when the open / close switches 25 to 28 are closed.

The signal synthesizing circuits 20 to 23 output the video signals A 'to D' from the open / close switches 25 to 28, respectively, during the absence of the background signal BS.
Is inserted and synthesized. The output signal E of the signal synthesizing circuit 23 is supplied to the monitor from the output terminal 24. In each field of the output signal E, the video signals A 'and B' are output for one horizontal scanning period in each first horizontal scanning period. Are time-divisionally combined,
In the latter half horizontal scanning periods, the video signals C 'and D' are synthesized in a time division manner for one horizontal scanning period. Therefore,
By the output signal E, the screens A, B, C, D and the background BS are displayed on the monitor as shown in FIG. 2 (a).

Next, a case where a multi-screen display is performed as shown in FIG. 2 (b) will be described. In this case, the reduction ratio r is set to about 1/3 to 1/4 by the reduction ratio control circuit 19 as described above.
The switch control circuit 29 sets the open / close switch 27 to an open state.

Video signals A to D are input to input terminals 1 to 4, respectively. At this time, the switching switch 14 selects and outputs the video signal C. Accordingly, the video signal C is supplied to the field synchronization circuits 15 to 18 as the output signal of the switching switch 14.

The video signals A, B, C, D are supplied to the reduction ratio control circuit 1 in the same manner as described above.
The reduction processing is performed at the reduction ratio r set to 9, and the read timing of the memories 10 to 13 at this time is controlled by the field synchronization circuits 15 to 18 so that the multi-screen display shown in FIG. The video signal C output from the switching switch 14 is set.

Here, the opening / closing switches 25, 26, and 28 are transmitted from the switching switch 14 so that the screens A, B, and D have the positional relationship as shown in FIG. It is closed for a period of one field of the video signals A ', B', and D 'in a predetermined phase relationship with the video signal C. The switching switch 14 is closed only when all of the open / close switches 25 to 28 are open.

The reduced video signal A 'output from the time axis reduction circuit 6 passes through the opening / closing switch 25, and is synthesized by the signal synthesis circuit 20 with the video signal C output from the switching switch 14 as described above. The reduced video signal B 'output from the time axis reduction circuit 7 passes through the opening / closing switch 26, and is synthesized by the signal synthesis circuit 21 with the output signal of the signal synthesis circuit 20. This output signal passes through the signal synthesis circuit 22 as it is. The reduced video signal D 'output from the time axis reducing circuit 9 passes through the opening / closing switch 28 and is combined with the output signal of the signal combining circuit 22 by the signal combining circuit 23. The output signal of the signal combining circuit 23 is supplied from an output terminal 24 to a monitor. Therefore, the monitor displays a screen as shown in FIG. 2 (b).

In this way, even if the input video signals A, B, C, and D are asynchronous, the video signals A ', B', C ', and D' obtained by reducing them are output from the switching switch 14. Signal, and the monitor scans in synchronization with the synchronizing signal of the output signal of the switching switch 14. Therefore, each screen A, B, C,
D will be displayed correctly.

The display modes shown in FIGS. 2A and 2B can be selected only by controlling the switching switch 14 and the opening / closing switches 25 to 28 and switching the reduction ratio r. The switching switch 14 is also controlled by the switch control circuit 29, and selects the background signal BS when all of the open / close switches 25 to 28 are on / off controlled. However, when the open / close switch 25 is always open, the video signal is selected. A, the video signal B is selected when the open / close switch 26 is always open, and the video signal D is selected when the open / close switch 28 is always open.
Any of B, C, and D can be arbitrarily selected and displayed as a close-up.

In FIG. 1, four signal synthesizing circuits 20 to 23 are provided. However, as shown in FIG. 3, one signal synthesizing circuit 30 outputs the output signals of the switching switch 14 and the time axis reducing circuits 6 to 9. May be combined.

In FIG. 1, the signal synthesizing circuits 20 to 23 are used, and in FIG. 3, the signal synthesizing circuit 30 is used as a switching switch. These signals are controlled by a switch control circuit 29, so that the signal from the switching switch 14 is controlled. The function to be absent and the functions of the open / close switches 25 to 28 may be provided. In this case, the switching switch 14 merely selects the background signal BS and the video signals A to D, and the opening / closing switches 25 to 28 can be omitted.

FIG. 4 is a block diagram showing a specific example of a time axis compression circuit, a memory and a field synchronization circuit in FIGS. 1 and 3, wherein 31 is a write clock generator, and 32 is an A / D.
(Analog / digital) converter, 33 is a write address generator, 34 is a read clock generator, 35 is a read address generator, 36 is a D / A (digital / analog) converter, and 37 is a write subarea selection circuit. , 38 to 41 are sub-areas, 42 is a read sub-area selection circuit, 43 is a small screen field discrimination circuit, 44 is a large screen field discrimination circuit, 45 is an address control circuit, and 46 is an output terminal. Parts corresponding to those in FIG. 3 are denoted by the same reference numerals.

FIG. 4 shows the reduction processing means of the video signal A in FIGS. 1 and 3, but the video signals B, C, D
The same applies to each reduction process.

Before describing this specific example, the reason for providing the field synchronization circuits 15 to 18 will now be described.

As described above, in FIGS. 1 and 2, it is common that there is no synchronous relationship between the input video signals A, B, C, and D, and between them and the background signal BS. For this,
The video signals A ', B', C ', D' are added to the output signal of the switching switch 14.
However, even if they are simply synchronized and displayed as shown in FIGS. 2A and 2B, the following problem occurs. That is, the screen (the background BS in FIG. 2 (a) and the screen C in FIG. 2 (b)) having the entire monitor screen as a display area is a large screen, and the screen fitted into the screen (FIG. 2 (a)) Screens A to D, screens A, B and D in FIG. 2 (b))
Is a small screen, (1) the vertical relationship of the scanning lines is reversed for the small screen.

(2) The picture frame is different between the top and bottom.

And other inconvenient phenomena occur.

The phenomenon (1) is directly attributable to the fact that the video signal employs the interlace method. According to such a video signal, for example, in FIG. 1, an odd field is read from the memory 10 when the output signal of the switching switch 14 is an odd field, and an odd field is read from the memory 10 when the output signal of the switching switch 14 is an even field. When the image is read out, an image having a round outline is correctly displayed on the small screen A of the image representing the round outline, as shown in FIG. 5 (a). Here, the solid diagonal lines represent odd-field scanning lines, and the dashed diagonal lines represent even-field scanning lines.

However, conversely, an even field is read from the memory 10 when the output signal of the switching switch 14 is an odd field, and an odd field is read from the memory 10 when the output signal of the switching switch 14 is an even field. is there.
In such a case, as shown in FIG. 5 (b), the scanning line which should be an odd field (solid oblique line) becomes the scanning line of the even field, and the scanning line which should be the even field (the broken line of the broken line). The oblique lines indicate odd-field scanning lines, and the vertical relationship between two vertically adjacent scanning lines is reversed. As a result, two images with round outlines shifted up and down by two scanning lines are displayed in a superimposed manner, resulting in a double-bubble picture frame, and image quality is significantly degraded.

Although the phenomenon (2) has been described above, for example, in FIG. 1, the reading speed in the memories 10 to 13 is higher than the writing speed, and thus the reading position overtakes the writing position. is there. When this occurs, the video signal one field before remains in the recording area of the memories 10 to 13 after passing, and this is read. For this reason, images of different fields are displayed in the vertical direction on the small screen, and especially when the image changes rapidly, as shown in FIG. A shift will occur.

The field synchronization circuits 15 to 18 are for solving such a problem, and FIG. 4 will be described below.

The video signal A input from the input terminal 1 is supplied to the A / D converter 3
After being converted into a digital video signal in 2, it is supplied to a write sub-area selection circuit 37 of the memory 10. Memory 10 is 4
It has a field storage capacity, which is divided into four areas, that is, sub-areas 28 to 41, and a write sub-area selection circuit 37 and a read sub-area selection circuit 42.
It has. The write sub-area selection circuit 37 selects one of the sub-areas 38 to 41, each having a capacity of one field, according to the write address signal from the write address generator 33, and selects one of the sub-areas of the digital video signal. Write the sample data for each minute.

The write address generator 33 has an address counter. The address counter is reset by a reset pulse based on the vertical synchronizing signal of the video signal A, and the write clock from the write clock generator 31 is used. , And forms, for example, 6-bit data (hereinafter referred to as write address designation data) for sequentially designating the addresses of the sub-areas 38 to 41. In this case, by operating the address counter only for every other horizontal scanning period of the video signal A, it is possible to thin out every other horizontal scanning period. Further, the write address generation circuit 33 is connected to the field synchronization circuit 15.
, For example, 2-bit data (hereinafter referred to as write sub-area designation data) for selecting one of sub-areas 38 to 41 is supplied. Are formed as the lower 6 bits to form the above-mentioned write address signal and supply it to the write sub-area selection circuit 37. Therefore, the write sub-area selection circuit 37 selects one of the sub-areas 38 to 41 by the upper two bits of the write address signal, and furthermore, the sample data of the digital video signal is selected by the lower six bits of the write address signal. Are sequentially written.

At this time, since the address counter of the write address generation circuit 33 is reset in accordance with the vertical synchronizing signal of the video signal, each of the selected sub-areas 38 to 41 receives the digitized video signal by one field. Will be remembered.

The sub-areas 38 and 40 are used for storing odd fields of the video signal A, and the sub-areas 39 and 41 are also used for storing even fields. Also, here, sub-areas 38, 39,
It is assumed that the field synchronization circuit 15 creates write subarea designation data to the write address generator 33 so as to be selected in the order of 40, 41, 38,.... With this,
Assuming that the even field of the video signal A is written in the sub area 41, the next odd field is in the sub area 38, the next even field is in the sub area 39, and the next odd field is in the sub area 40. Will be written.

The operation of the field synchronization circuit 15 for generating such write subarea designation data will be described with reference to FIG.

The small-screen field determination circuit 43 determines an odd or even field from the synchronization signal of the input video signal A, and as shown in FIG.
(High level), and outputs a determination signal that becomes “0” (low level) in the even field. As shown in FIG. 6 (b), the address control circuit 45 forms a four-field period signal of the video signal A whose level is inverted at each rising edge of the determination signal, and this signal and the determination signal (FIG. 6 ( a)) are supplied to the write address generator 33 as write sub-area designation data.

The relationship between the sub-area designation data and the sub-areas 38 to 41 designated thereby is as shown in the following table.

With this setting, the sub-areas 38 to 41 are selected in the order shown in FIG. 6C for the odd and even fields of the video signal A shown in FIG. 6A.

It should be noted that since the small screen field determination circuit 43 is provided with a synchronization separation circuit, a reset pulse of the address counter in the write address generator 33 is formed based on the vertical synchronization signal separated by this. Can be.

The read address generator 35 also has an address counter, and counts the read clock from the read clock generator 34. The cycle of this read clock is the write clock generator
31 is set to r times the reduction ratio of the write clock output. On the other hand, in the case of multi-screen display as shown in FIGS. 2 (a) and 2 (b), a signal indicating the display position of the small screen is formed on the basis of the synchronizing signal of the output signal of the switching switch 14. Looking at this for each field, if FIG. 6D shows the odd and even fields of the output signal of the switching switch 14, the signal representing the display position of the small screen A is the sixth signal.
As shown in FIG. 6 (e), the signal shown in FIG. 6 (d) is represented as a signal of "1" in a predetermined phase and at a reduction ratio r times of one field period. The address counter of the read address generator 35 is reset at the rising edge of the signal shown in FIG. The output of this address counter is data (hereinafter referred to as read address designation data) for sequentially designating the addresses of the sub-areas 38 to 41. The number of bits of this data is equal to the write address designation data in the write address signal, for example, 6 bits.

The read address generator 35 also includes a field synchronization circuit.
For example, 2-bit data (hereinafter referred to as read sub-area designating data) for designating one of the sub-areas 38 to 41 is supplied from 15, and this is set as upper 2 bits and read address designating data is set as lower 6 bits. A bit read address signal is created and supplied to a read sub area selection circuit 42.

The read sub-area selection circuit 42 selects one of the sub-areas 38 to 39 according to the upper two bits of the read address signal, and sequentially designates the address of the selected sub-area according to the lower six bits to sample data. read out.
Here, the address counter of the read address generator 35 is reset at the rising edge of the signal of FIG. 6 (e), the read clock cycle is the reduction ratio r times the read clock cycle, and FIG. Since the "1" period of the signal e) is r times the one-field period of the output signal of the switching switch 14,
The sample data for one field of the selected sub-areas 38 to 41 is read in the period of "1" in FIG. 6 (e).

When reading from the sub-areas 38 to 41, when the output signal of the switching switch 14 is an odd field, any of the odd-field sub-areas 38, 40 is an even field, and when the output signal is an even field, the even-field sub-area 39, 41
Is selected, and when a sub-area to be read and selected next is being written,
Read sub-area designation data is created so that the other sub-area for the same field is selected. Hereinafter, the operation of the field synchronization circuit 15 for this purpose will be described with reference to FIG.

The large-screen field discriminating circuit 44 discriminates the odd / even field from the synchronizing signal of the output signal of the switching switch 14,
As shown in FIG. 6 (d), a decision signal is output which becomes "1" in an odd field and "0" in an even field. The address control circuit 45 inputs this determination signal and changes the level of the signal shown in FIG. 6B by the rising edge of the signal representing the period of the small screen A shown in FIG. A sample and hold is performed to form a signal shown in FIG.

Here, the signal shown in FIG. 6 (b) corresponds to FIG. 6 (c), when "1" indicates that the sub-area 38 or 39 has been selected for writing, and when "0", it indicates. This indicates that the sub area 40 or 41 has been selected for writing. Accordingly, from the level of the signal of FIG. 6 (f) at the rising edge of the signal of FIG.
Can be tentatively determined whether or not there is a possibility of a write state.

The determination signal shown in FIG. 6 (d) and the signal shown in FIG. 6 (f) are supplied to the read address generator 35 as read sub-area designation data, whereby the field of the output signal of the switching switch 14 is reduced. A sub-area for the same field and having no possibility of a write state is selected. The following table shows the relationship between the read sub-area designation data and the sub-areas 38 to 41 selected thereby.

With this setting, the switching switch shown in FIG.
For the odd and even fields of the 14 output signal, FIG.
Are selected in the order shown in FIG.

In this manner, the video signal A is written into the sub-areas 38 to 41 one field at a time, and the data is read from them.

The above operation is a time axis reduction circuit for reducing the video signal B.
7, the memory 11, the field synchronization circuit 16,
The same applies to a similar circuit for reducing the video signals C and D. However, as shown in FIGS. 2 (a) and 2 (b), the display positions of the screens A to D on the monitor M are different, so that the display positions are shown in FIG. 6 (d) according to the video signals A to D. The phase of the signal shown in FIG. 6 (e) representing the position of the small screen with respect to each field of the output signal of the switching switch 14 is different.
It goes without saying that the reset timings of the address counters of the read address generation circuits (corresponding to the reference numeral 35 in FIG. 4) in the time axis reduction circuits 6 to 9 are different. The reset timing of this address counter is the second.
The display timing of the upper left corner of each small screen in FIGS. The sizes of these small screens change when shifting from FIG. 2 (a) to FIG. 2 (b). In this case, even if the display timing of the upper left corner on the small screen A does not change, the small screens B, C, About D changes. However, corresponding to this, the phase of the signal shown in FIG. 6 (e) for each of the small screens B, C, and D also changes, so that the reset timing of the address counter also changes. is there.

As described above, in FIGS. 1 and 3, since the video signals A 'to D' are read from the memories 10 to 13 in the fields that match the odd and even fields of the output signal of the switching switch 14, The phenomenon of 1) does not occur, and in these memories 10 to 13, reading is started in a sub-area where writing is not performed.
Prevents the read position from overtaking the write position,
The phenomenon (2) does not occur.

The large-screen field discriminating circuit 44 shown in FIG.
1 can be commonly used in the field synchronization circuits 15 to 18 in FIG. 1 and FIG.

In FIG. 4, the capacity of the memory 10 is set to 4 fields. However, if the read address allows overtaking of the write address, it may be set to 2 fields.
If even field mismatch is allowed, one field may be used.

By the way, when the reduction ratio r is set to an even number, there is a problem that image distortion occurs on a small screen. This will be described with reference to FIG.

Now, FIG. 7 (a) shows a display screen by the interlaced system, in which a solid line scanning line is an odd field scanning line, and a broken line scanning line is an even field scanning line, and a triangular contour image is displayed. And

Here, assuming that such a screen is reduced by half to make it a small screen, in the odd field, every other scanning line of the mark “○” is extracted and the scanning line of the mark “×” is thinned out. In the even field, every other scan line of the mark ◎ is extracted, and the scan lines of the mark 間 are thinned out. When a small screen reduced to 1/2 is displayed by the video signal whose scanning lines have been thinned out as described above, the outline of the triangle becomes distorted as shown in FIG. 7B. This is because, as is clear from FIG. 7 (a), the extracted scanning line (odd field) indicated by ○ and ◎
The scanning lines (even fields) of the marks are not arranged at equal intervals, and in a small screen, as shown in FIG.
This is because they are arranged at equal intervals.

In order to prevent this, in FIGS. 1 and 3,
What is necessary is to extract the video signals A to D to form a small screen every other field and perform a reduction process, so as to remove every other field. In the reduction process, odd and even fields are created from the extracted fields. FIG. 7 (c) shows a case where the odd field of the screen shown in FIG. 7 (a) is extracted, and the odd and even fields of the small screen are created from this.
Shown in Here, every other circle in FIG.
The scanning line indicated by the mark is an odd-field scanning line, the other scanning line indicated by the cross is an even-field scanning line, and the scanning line indicated by a circle and the scanning line indicated by a cross are the seventh line. Since they are arranged at equal intervals in FIG. 7A, they are arranged at equal intervals even in a 1/2 reduced screen shown in FIG. Does not appear.

In the case of such reduction processing, the specific example of FIG. 4 is as follows.

Now, when only the odd field of the video signal A is extracted and reduced, the small-screen field discriminating circuit 43 determines the odd or even field of the video signal A, and doubles the signal of FIG. 6 (a). The signal of the period of is output. Address control circuit 45
Writes this signal and a signal obtained by dividing the signal by 2 (ie, a signal obtained by dividing the signal shown in FIG. 6A by 2 and a signal obtained by dividing the signal shown by FIG. 6B by 2). It is supplied to the write address generation circuit 33 as a sub area designation signal. In the write address generation circuit 33, for example, based on the determination result of the small screen field determination circuit, the address counter
Is held in the reset state during the even field. As a result, the sequential odd field of the video signal A is
Written in the order of 1,40,39,38.

Similarly, the large screen field discriminating circuit 44 outputs a signal obtained by dividing the signal shown in FIG. 6D by two, and the address control circuit 45 converts the signal shown in FIG. The supplied signal is supplied to the read address generator 35 as a read sub-area designation signal. As a result, each sub area 38
.About.41 are selected for each of two field periods of the odd field and the even field of the output signal of the switching switch 14.
Each of the selected sub-areas 38 to 41 is provided with a switching switch.
When the output signal of 14 is an odd field, reading is performed at every other (eg, odd number) read address specifying data from the read address generator 38, and when the output signal is an even field, the read address specifying data is read. Another one
Reading is performed every other (for example, even number).

The same applies to the case where only the even field of the video signal A is extracted and reduced.

 Next, the setting of the display position of the small screen will be described.

A simple method for setting this display position is to use a monostable multivibrator based on the horizontal and vertical synchronizing signals of the video signal of a large screen (ie, the output signal of the switching switch 14 in FIGS. 1 and 3). The time from these synchronization signals is measured using such as delay means.

By the way, in such delay means, an error in the delay time cannot be avoided, and this error causes a shift in the display position of the small screen. Nevertheless, since the delay amount of the delay means for defining the display position in the horizontal direction is small, even if there is a variation in the delay amount, the ratio is small.
The horizontal displacement of the small screen is hardly noticeable. However, for example, when four screens are displayed as shown in FIG. 2 (a), especially for the lower small screens D and C,
The delay amount of the delay means for defining the display position in the vertical direction is very large, about 230 msec. For this reason, even if the amount of delay varies by about 5%, the absolute amount is 150%.
μsec, so that the vertical position shift extends over two scanning lines for more than two horizontal scanning periods. For example, if 4 screens A~D as shown in FIG. 8 is displayed, it is set so that the upper left corner of the small screen C is displayed on the point P on the scanning lines H _n, the delay means Due to the variation in the amount of delay, it is displayed at the position indicated by the point P ′ on the next scanning line H _{n + 1} ,
The small screen C is displayed shifted by one scanning line in the vertical direction.

If the delay amounts of the delay means for setting the vertical positions of the small screens C and D are different, the positions of these small screens will be shifted in the vertical direction, making the display unsightly. Also,
If this delay is on whether the threshold to include scan lines H _n for displaying the small screen C is or is not included scan lines H _n,
As a result, the display position of the small screen C reciprocates in the vertical direction, and the small screen C is displayed with a loose play in the vertical direction.

Further, when the delay amount of the vertical delay means is at the above-described threshold value, the even field is displayed from the scanning line H _n ′ between the odd-field scanning lines H _n and H _{n + 1.} Is done. Therefore, the odd field, when settled on the display from the scan line H _{n + 1,} the information content of the scanning lines H _n 'will be displayed on the scan line H _{n + 1.} Here, the information content displayed on the scan line H _{n + 1} are those that should be displayed on the scan line H _n on the scan line H _n ', the but connexion, odd,
The information displayed between the scanning lines of the even field is upside down.

FIG. 9 shows a first embodiment configured to solve such a problem.
FIG. 3 is a block diagram showing a specific example of a switch control circuit 29 in the figure, wherein 47 is a synchronization separation circuit, 48 and 49 are monostable multivibrators, 50 is a D-type flip-flop circuit (hereinafter referred to as D-FF), and 51 is A preset circuit, 52 is a counter, 53 is a decoder, 54 is a logic circuit, 55 is a horizontal window circuit, and portions corresponding to those in FIG.

 Hereinafter, the operation of this specific example will be described with reference to FIG.

In the figure, a sync separation circuit 47 is provided in the large screen field discriminating circuit 44 in FIG. 4, from which a horizontal sync signal HS and a vertical sync signal VS of the output signal of the switching switch 14 are output. Monostable multivibrator 48 is triggered by the leading edge of the vertical synchronizing signal VS, and generates a pulse to Q ₁ pulse width T ₁ determined by the time constant of the rise and the monostable multivibrator 48 in this leading edge. The monostable multivibrator 49 is triggered by a horizontal synchronizing signal HS, and rises and is monostable by the horizontal synchronizing signal HS.
A pulse Q ₂ having a pulse width T ₂ determined by 49 specific numbers is generated.
Pulse Q ₁ is a data input D next to D-FF50, falling edge of the pulse Q ₂ is a clock CK of the D-FF50. Was but connexion, from D-FF50, falls in the first falling edge of the pulse Q ₂ within the pulse duration of the pulse Q _1, the first falling edge of the pulse Q ₂ after the falling edge of the pulse Q ₁ stand A falling pulse Q is obtained. That is, the pulse Q is equal to the horizontal synchronization signal HS
Has a pulse width that is an integral multiple of the period of

The pulse Q is supplied to a preset circuit 51, and a preset pulse PS is formed at its falling edge. Counter 52
Are counted by the horizontal synchronizing signal HS from the synchronizing separation circuit 47, and are preset by a preset pulse PS. The count value N of the counter 52 is supplied to the decoder 53, and the vertical window signal S _{V is} provided in a numerical range N _{1 to} N ₂ corresponding to the reduction ratio r set in the reduction ratio control circuit 19 for the count value N
Is output. The vertical window signal S _V defines the vertical direction of the display position of the small screen.

On the other hand, the horizontal window circuit 55 becomes a delay means such as a monostable multivibrator, the output of the horizontal window signal S _H which defines the horizontal direction of the display position of the small screen from the horizontal synchronizing signal HS sync separation circuit 47 outputs I do. This horizontal window signal S _H
And a logical operation by the logic circuit 54 and the vertical window signal S _V from the decoder 53, window signal S that defines the display position of each scan line of the small screen is formed. The window signal S is a control signal for the opening / closing switch 25.

The vertical window signal _SV is a signal shown in FIG. 6 (e) for the small screen A, and is supplied to the address control circuit 45 in FIG. 4 to sample the signal shown in FIG. 6 (b). Hold and read address generator in FIG.
Supplied to 35 to reset the address counter at its leading edge. Further, the horizontal window signal S _H in FIG. 9 operates the address counter of the read address generator 35 in FIG. 4 only the pulse period, the read mode sub area selected for reading sub-area 38-41 And

According to this specific example, the display position in the vertical direction of the small screen is mainly determined by the delay amount of the monostable multivibrator 48, the D-FF 50 in which this is an integral multiple of the period of the horizontal synchronization signal, and the counting of the horizontal synchronization signal by the counter 52. Defined by For this, the rise of the vertical window signal S _V, falling edge is by connexion defined in the horizontal synchronizing signal HS, it caused an unstable state that the frame of the small screen can take one of two scanning lines Without and also a monostable multivibrator
Since the delay amount of 48 can be reduced, the error is also reduced, and the vertical display position of the small screen can be set accurately.
It is also possible to prevent the scanning lines of the odd and even fields from being inverted. Therefore, the small screen can be accurately and stably displayed at the specified position.

Now, in the embodiment described above, FIG.
It is possible to select a mode in which four screens are displayed as small screens with the same size as shown in Fig. 2 and a mode in which one of the four screens is made a large screen and the other is a small screen as shown in Fig. 2 (b). However, if these modes are switched at an arbitrary timing, the entire screen is disturbed at the time of the switching. To prevent this, the switching switch shown in FIGS. 1 and 3 is used.
The timing of the vertical synchronization signal in the 14 output signals may be used. The means for this is shown in FIG. In the figure, reference numeral 56 denotes an input terminal for a mode switching command signal, 57 denotes a timing circuit, 47 denotes a synchronization separation circuit shown in FIG. 9, and 14, 19, and 29 denote switching switches and reduction switches in FIG. A ratio control circuit and a switch control circuit.

In FIG. 11, the switching switch from the sync separation circuit 47
A vertical synchronizing signal of the 14 output signals is output and supplied to the timing circuit 57. When a mode switching command signal for changing from one of the modes to the other is input from the input terminal 56, the timing circuit 57 switches the switching switch 14 and the reduction ratio control circuit 19 at the timing of the first vertical synchronization signal after the input. , And sends a switch control signal to the switch control circuit 29. The timing circuit 57 can be constituted by a D-type flip-flop circuit. In this case, the mode switching command signal has a different level according to the mode, and is supplied to the D-type flip-flop circuit as a data input. The vertical synchronizing signal output from the synchronizing separation circuit 47 becomes the clock of the D-type flip-flop circuit.

〔The invention's effect〕

As described above, according to the present invention, it is possible to simultaneously and stably display moving images based on video signals from a plurality of asynchronous signal sources, and to display these moving images in the same size. It is possible to select a mode in which one of the moving images is enlarged and the other is displayed as a small screen, so that simultaneous viewing (monitoring) of a plurality of screens or one specific focused viewing (monitoring) can be performed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a multi-screen moving image display device according to the present invention, FIGS. 2 (a) and 2 (b) show display examples according to this embodiment, and FIG. FIG. 4 is a block diagram showing another embodiment of the screen moving image display device.
And FIG. 3 is a block diagram showing a specific example of a time axis reduction circuit, a memory and a field synchronization circuit in FIG. 3, and FIG. 5 is a phenomenon caused by reversal of the arrangement of scanning lines of odd and even fields in writing and reading of the memory. FIG. 6 is a diagram showing a phenomenon caused by a read address overtaking a write address, FIG. 6 is an explanatory diagram of the operation of the field synchronization circuit in FIG. 4, and FIG. 7 is a view of a small screen when the reduction ratio is an even number. FIG. 8 is a diagram showing image distortion and a method for preventing the image distortion, FIG. 8 is a diagram for explaining variations in the vertical display position of the small screen, and FIG. 9 is one of the switch control circuits in FIG. 1 for preventing the variations. FIG. 10 is a block diagram showing a specific example, FIG. 10 is an explanatory diagram of the operation, and FIG. 11 is a block diagram showing a specific example of the display mode switching means of FIGS. 2 (a) and 2 (b). 1-4 video signal input terminals, 5 ... background signal generation circuit, 6-9 time axis reduction circuit, 10-13 memory 14
…… Switching switches, 15-18 …… Field synchronization circuits,
19 ... reduction ratio control circuit, 20 to 23 ... signal synthesis circuit, 24 ...
... output terminals, 25 to 28 ... open / close switches, 29 ... switch control circuits, 30 ... signal synthesis circuits.

Claims (2)

(57) [Claims] 1. A time axis reducing means for reducing the screen of an input moving image signal from a plurality of signal sources in accordance with a reduction ratio set for each field, a background signal generating means, the plurality of moving image signals, and Switching means for selecting any one of the background signals; synchronizing means for outputting a moving image signal whose screen has been reduced from the time axis reducing means in a predetermined phase relationship with respect to an output signal of the switching means; A signal synthesizing unit for synthesizing an output signal of the switching unit and a moving image signal whose screen has been reduced by the time axis reducing unit from a signal source different from the output signal, and when the switching unit selects the background signal. And a control means for switching the reduction ratio when selecting one of the input moving image signals, wherein a moving image plane based on the asynchronous moving image signal can be simultaneously displayed. . 2. The time axis reduction means according to claim 1, wherein the time axis reduction ratio is set to an even number, and every other field of the input moving image signal is extracted and the odd and even time is extracted from the field. A multi-screen moving image display device, which forms a field whose axis is reduced and outputs a moving image signal whose screen is reduced by the field.