JP2616976B2 - Active matrix and its manufacturing method - Google Patents
Active matrix and its manufacturing methodInfo
- Publication number
- JP2616976B2 JP2616976B2 JP25205988A JP25205988A JP2616976B2 JP 2616976 B2 JP2616976 B2 JP 2616976B2 JP 25205988 A JP25205988 A JP 25205988A JP 25205988 A JP25205988 A JP 25205988A JP 2616976 B2 JP2616976 B2 JP 2616976B2
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- JP
- Japan
- Prior art keywords
- active matrix
- additional capacitance
- insulating film
- wiring
- pixel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Liquid Crystal (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Thin Film Transistor (AREA)
- Liquid Crystal Display Device Control (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、薄膜トランジスタ(以下、TFTという)等
の非線形素子で駆動するアクティブマトリクスおよびそ
の製作法に関するものである。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix driven by a non-linear element such as a thin film transistor (hereinafter, referred to as TFT) and a method for manufacturing the same.
液晶を表示媒体に用いた液晶ディスプレイ(LCD)
は、CRTディスプレイに較べて軽量・薄型であるととも
に、低消費電力などの特徴を有するため、上記CRTディ
スプレイの代替として研究開発が進められており、一部
実用化され始めている。特に、画素ごとに非線形素子を
設けて駆動するアクティブマトリクス方式は、CRTディ
スプレイの匹敵する高画質の実現が可能である。つぎに
アクティブマトリクス方式のLCDを説明するが、非線形
素子には最も多く用いられているTFTを用いる。Liquid crystal display (LCD) using liquid crystal as display medium
Since they are lighter and thinner than CRT displays and have features such as low power consumption, research and development are being promoted as alternatives to the above CRT displays, and some of them have begun to be put into practical use. In particular, the active matrix method in which a non-linear element is provided for each pixel and driven can realize high image quality comparable to that of a CRT display. Next, an active matrix type LCD will be described, and the most frequently used TFT is used for the non-linear element.
アクティブマトリクス方式を用いたLCDは、TFTと画素
電極とから構成される基本単位(画素)をマトリクス状
に並べ、上記画素周囲にTFT動作を制御する走査線およ
び画素周囲にTFT動作を制御する走査線および画素電極
に表示データを供給するデータ線を、格子状に配置した
アクティブマトリクス基板と、全面に単一電位が供給さ
れる対抗基板との間に、液晶を挟んだ構造をなしてい
る。ここでは画素電極と対向基板とで液晶を挟み表示を
行う部分を液晶表示セル、画素ごとに設けられたTFTを
画素用TFTと呼ぶことにする。第4図にアクティブマト
リクスの等価回路を示す。1は走査線、2はデータ線、
3はTFT、11は液晶表示セルである。In an LCD using an active matrix method, a basic unit (pixel) composed of a TFT and a pixel electrode is arranged in a matrix, and a scanning line for controlling the TFT operation around the pixel and a scanning line for controlling the TFT operation around the pixel. The liquid crystal is sandwiched between an active matrix substrate in which data lines for supplying display data to lines and pixel electrodes are arranged in a grid pattern, and a counter substrate in which a single potential is supplied to the entire surface. Here, a portion where a liquid crystal is sandwiched between a pixel electrode and a counter substrate and a display is performed is referred to as a liquid crystal display cell, and a TFT provided for each pixel is referred to as a pixel TFT. FIG. 4 shows an equivalent circuit of the active matrix. 1 is a scanning line, 2 is a data line,
3 is a TFT, and 11 is a liquid crystal display cell.
アクティブマトリクス方式のLCDでは、液晶表示セル
が作る容量に電荷を充電することにより液晶に電圧を印
加し、液晶配向の変化に伴う透過率変化により表示を行
う。しかし、特定画素の充電時間は、つぎに同一画素に
表示データが書き込まれるまでの間の時間に較べて極め
て短く、充電後、つぎに表示データが書き込まれるまで
の間、TFTをオフ状態にして液晶表示セルの状態を保持
する必要がある。液晶に印加された電圧が規定された保
持時間内で変動すると、表示状態の変化が生じ、コント
ラスト低下等の表示品質上の問題を生じる。特に、フル
カラー化を目指して階調表示を行う場合や、より高精細
な画面を目指し画素サイズを小さく、すなわち液晶表示
セルの容量を小さくした場合にはこの電荷の保持特性が
問題になる。充電した電荷はTFTのリーク電流等により
漏れるため、液晶表示セルの保持特性は、液晶表示セル
の容量とTFTのリーク電流等による電荷のリーク量によ
り決まる。In an active matrix type LCD, a voltage is applied to the liquid crystal by charging a capacitor formed by the liquid crystal display cell with electric charge, and display is performed by a change in transmittance accompanying a change in liquid crystal alignment. However, the charging time of a specific pixel is extremely short compared to the time until the next time display data is written to the same pixel, and after charging, the TFT is turned off until the next display data is written. It is necessary to maintain the state of the liquid crystal display cell. If the voltage applied to the liquid crystal fluctuates within a prescribed holding time, a change in the display state occurs, and a problem in display quality such as a decrease in contrast occurs. In particular, when gradation display is performed to achieve full color, or when the pixel size is reduced to achieve a higher definition screen, that is, when the capacity of the liquid crystal display cell is reduced, this charge retention characteristic becomes a problem. Since the charged electric charge leaks due to the leak current of the TFT or the like, the retention characteristics of the liquid crystal display cell are determined by the capacity of the liquid crystal display cell and the amount of charge leak due to the leak current of the TFT and the like.
上記の問題を解決するために、第5図に示したように
液晶表示セル11と並列に付加容量12を形成し、液晶表示
セルの実効的容量を増大する方法が一般に用いられてい
る。この方法では、電荷のリーク量が一定であれば、液
晶表示セルの容量の増大により液晶に印加される電圧値
の変動を小さくできる利点がある。このような付加容量
を用いた例が文献(例えば白井他「高画質フルカラー液
晶パネル」、電子通信学研究技術報告、Vol.86,No.65,p
p65−69,1986,Y.Oana“A240×320Elements Active Matr
ix LCD with Integrated Gate−Bus Drivers Using P
oly−Si TFTs"SID国際シンポジウム技術論文要約、pp31
2−315、1984等多数ある)に示されている。これらの例
では、第6図に示したように画素電極4と付加容量配線
5が付加容量用絶縁膜6を挟んで付加容量を形成する。
なお、上記付加容量配線5は対向電極と同電位が供給さ
れる。このため、上記付加容量配線5は、走査線1、デ
ータ線2またはその両方との交差が避けられない。In order to solve the above problem, a method of increasing the effective capacitance of the liquid crystal display cell by forming an additional capacitance 12 in parallel with the liquid crystal display cell 11 as shown in FIG. 5 is generally used. This method has the advantage that if the amount of charge leakage is constant, the fluctuation of the voltage value applied to the liquid crystal can be reduced due to an increase in the capacity of the liquid crystal display cell. Examples using such additional capacitors are described in the literature (for example, Shirai et al., “High-quality Full-Color Liquid Crystal Panels”, Research Report on Electronics and Communications, Vol. 86, No. 65, p.
p65-69,1986, Y.Oana “A240 × 320Elements Active Matr
ix LCD with Integrated Gate−Bus Drivers Using P
oly-Si TFTs "SID International Symposium Technical Paper Abstract, pp31
2-315, 1984, etc.). In these examples, as shown in FIG. 6, the pixel electrode 4 and the additional capacitance wiring 5 form an additional capacitance with the additional capacitance insulating film 6 interposed therebetween.
The same potential as that of the counter electrode is supplied to the additional capacitance wiring 5. For this reason, it is inevitable that the additional capacitance line 5 crosses the scanning line 1, the data line 2, or both.
付加容量を形成した場合のアクティブマトリクスの概
念を第7図に示す。第7図(a)は付加容量配線5とデ
ータ線2が交差する場合、第7図(b)は付加容量配線
5に走査線1とデータ線2の両方が交差する場合を示し
ている。第7図では走査線1と付加容量配線5とが交差
する場合は示していないが、考え方としてはデー線2と
交差する(a)の場合と同様である。FIG. 7 shows the concept of an active matrix in the case where an additional capacitor is formed. FIG. 7A shows a case where the additional capacitance wiring 5 and the data line 2 intersect, and FIG. 7B shows a case where both the scanning line 1 and the data line 2 intersect the additional capacitance wiring 5. Although FIG. 7 does not show the case where the scanning line 1 intersects with the additional capacitance line 5, the concept is the same as the case of FIG.
したがって、付加容量を形成したアクティブマトリク
スでは、付加容量配線5とデータ線2または走査線1と
の交差部分に、配線容量が新たに発生することになる。
従来の方法では、付加容量配線とデータ線(または走査
線)の間の電気的絶縁は、付加容量を形成する絶縁膜だ
けによって行われている。したがって、付加容量値を増
すためには絶縁膜の膜厚を薄くせざるを得ず、このた
め、データ線または走査線の配線容量が増大することに
なり、アクティブマトリクスを駆動する周辺回路の負荷
が増すという欠点があった。Therefore, in the active matrix in which the additional capacitance is formed, a wiring capacitance is newly generated at the intersection of the additional capacitance wiring 5 and the data line 2 or the scanning line 1.
In the conventional method, electrical insulation between the additional capacitance wiring and the data line (or the scanning line) is performed only by the insulating film forming the additional capacitance. Therefore, in order to increase the additional capacitance value, the thickness of the insulating film has to be reduced, and therefore the wiring capacitance of the data line or the scanning line is increased, and the load of the peripheral circuit for driving the active matrix is increased. However, there is a drawback that the number increases.
本発明は、データ線または走査線の配線容量を小さく
したアクティブマトリクスの構成と、その簡便な製作法
とを得ることを目的とする。SUMMARY OF THE INVENTION It is an object of the present invention to obtain an active matrix configuration in which the wiring capacitance of a data line or a scanning line is reduced, and a simple manufacturing method thereof.
上記目的は、透明導電膜で構成する付加容量配線とデ
ータ線および走査線の両方または一方との交差部分が、
付加容量形成用絶縁膜およびネガ型感光性樹脂層によ
り、電気的に絶縁することによって達成される。The above object is achieved at the intersection between the additional capacitance wiring formed of a transparent conductive film and the data line and / or the scanning line.
This is achieved by electrically insulating with an insulating film for forming an additional capacitance and a negative photosensitive resin layer.
上記のように付加容量を形成した画素構造では配線容
量の増大が大きな問題になる。上記配線容量を低下させ
るには、付加容量配線とデータ線および走査線との交差
部に、新たな絶縁層を設けることによって配線容量を小
さくすることが考えられ、本発明では、上記データ線ま
たは走査線の配線容量を小さくするために、上記配線交
差部に感光性樹脂層よりなる絶縁層を簡便な方法によっ
て新たに設け、アクティブマトリクス構造を形成したも
のである。In the pixel structure in which the additional capacitance is formed as described above, an increase in wiring capacitance is a major problem. In order to reduce the wiring capacitance, it is conceivable to reduce the wiring capacitance by providing a new insulating layer at the intersection of the additional capacitance wiring and the data line and the scanning line. In order to reduce the wiring capacitance of the scanning line, an insulating layer made of a photosensitive resin layer is newly provided at the wiring intersection by a simple method to form an active matrix structure.
つぎに本発明の実施例を図面とともに説明する。第1
図は本発明によるアクティブマトリクスの一実施例を示
す画素平面図、第2図は上記実施例のA−A線矢視方向
の断面図、第3図(a)〜(e)は上記実施例の製作方
法をそれぞれ説明する図である。第1図に示す実施例の
アクティブマトリクスの画素は第6図と同様に、走査線
1、データ線2、TFT3、画素電極4および付加容量配線
5により構成されている。断面構造としては、第2図に
示すように付加容量配線5と画素電極4との間に、付加
容量構造を形成するための付加容量用絶縁膜6が上記第
6図と同様に存在する。なお、第2図に示す断面図は、
アクティブマトリクスの特徴を判りやすくするため、A
−A′線矢視方向における断面図とA′−A線矢視方向
における断面図とを合成してある。データ線2と付加容
量配線5との交差部分には、上記付加容量用絶縁膜6に
加えて感光性樹脂層7を設け、上記データ線2と付加容
量配線5との間に生じる配線容量を低減している。Next, embodiments of the present invention will be described with reference to the drawings. First
FIG. 2 is a plan view of a pixel showing an embodiment of the active matrix according to the present invention, FIG. 2 is a cross-sectional view of the above embodiment taken along line AA, and FIGS. It is a figure explaining each manufacturing method of. The pixels of the active matrix of the embodiment shown in FIG. 1 are composed of scanning lines 1, data lines 2, TFTs 3, pixel electrodes 4 and additional capacitance lines 5, as in FIG. As a sectional structure, as shown in FIG. 2, an additional capacitance insulating film 6 for forming an additional capacitance structure exists between the additional capacitance wiring 5 and the pixel electrode 4 as in FIG. The sectional view shown in FIG.
To make it easier to understand the characteristics of the active matrix,
The cross-sectional view in the direction of the arrow A-A 'and the cross-sectional view in the direction of the arrow A'-A are combined. At the intersection of the data line 2 and the additional capacitance wiring 5, a photosensitive resin layer 7 is provided in addition to the additional capacitance insulating film 6. Has been reduced.
つぎに、上記構成のアクティブマトリクスの製作法を
第3図により説明する。第3図(a)は透明基板10上に
TFT3、TFTのゲート電極を兼ねる走査線1および層間絶
縁膜8を形成後における画素の断面を示す。上記(a)
までの製作法は、従来からのアクティブマトリクス製作
法が使用できる。ここで透明導電膜、具体的にはITO(I
ndium TIn Oxide)膜をスパッタ法で500Å堆積し、通常
のホト工程により付加容量配線5のレジストパタンを形
成し、上記ITO膜を塩酸および硝酸を含む水溶液で加工
し、付加容量配線5を形成する。付加容量を形成するた
めの付加容量用絶縁膜6、具体的にはSiO2をスパッタリ
ング法等で堆積し、第3図(b)に示す構造を作製す
る。Next, a method of manufacturing the active matrix having the above configuration will be described with reference to FIG. FIG. 3 (a) shows on a transparent substrate 10.
A cross section of a pixel after forming a scanning line 1 also serving as a TFT 3 and a gate electrode of the TFT and an interlayer insulating film 8 is shown. (A) above
Up to this point, a conventional active matrix manufacturing method can be used. Here, the transparent conductive film, specifically, ITO (I
A 500 .ANG.-thick ndium TIn Oxide) film is deposited by a sputtering method, a resist pattern of the additional capacitance wiring 5 is formed by a usual photo process, and the ITO film is processed with an aqueous solution containing hydrochloric acid and nitric acid to form the additional capacitance wiring 5. . An insulating film 6 for additional capacitance, specifically SiO 2 , for forming an additional capacitance is deposited by a sputtering method or the like, and a structure shown in FIG. 3B is manufactured.
つぎに、画素電極4を形成するために、透明導電膜お
よび不透明膜の2層膜、例えば上記ITO膜500ÅとMo膜10
00Åをスパッタリング法で連続堆積を行い、通常のホト
工程により画素電極4のレジストパタンを形成したの
ち、Mo膜をCCl2F2とO2との混合ガスを用いた反応性イオ
ンエッチング法によって加工し、続いてITO膜を上記の
付加容量配線パタン加工時と同様に、塩酸・硝酸系の酸
溶液で加工して第3図(c)に示す構造を作製する。Next, in order to form the pixel electrode 4, a two-layer film of a transparent conductive film and an opaque film, for example, the ITO film 500 # and the Mo film 10 are formed.
After a continuous deposition of 00 ° by a sputtering method, a resist pattern of the pixel electrode 4 is formed by a normal photo process, and then the Mo film is processed by a reactive ion etching method using a mixed gas of CCl 2 F 2 and O 2. Subsequently, the ITO film is processed with a hydrochloric acid / nitric acid-based acid solution in the same manner as in the above-described processing of the additional capacitance wiring pattern to produce the structure shown in FIG. 3 (c).
つぎに、ネガ型感光性樹脂、例えば東レのネガ型感光
性ポリイミドUR−3600を回転塗布法で塗布し、推奨の83
℃でプリベークして感光性樹脂層7を形成した。続いて
第3図(d)に示すように基板10の背面から1000mj/cm2
の紫外光で上記感光性ポリイミドを露光する。その後、
推奨の現像液で未露光部の感光性ポリイミドを除去し、
250℃以上の熱処理を行ってイミド化反応を生じさせ
る。すると、第3図(e)に示すように、不透明部分と
なる走査線1、TFT3および画素電極4上は感光性ポリイ
ミドが未感光になるため、上記感光性ポリイミドは除去
され、それ以外の部分に感光性樹脂層7が形成される。Next, a negative photosensitive resin such as Toray's negative photosensitive polyimide UR-3600 is applied by a spin coating method, and the recommended 83
The photosensitive resin layer 7 was formed by pre-baking at ℃. Subsequently, as shown in FIG. 3 (d), 1000 mj / cm 2
The photosensitive polyimide is exposed to ultraviolet light. afterwards,
Remove the photosensitive polyimide in the unexposed area with the recommended developer,
A heat treatment at 250 ° C. or higher is performed to cause an imidization reaction. Then, as shown in FIG. 3 (e), the photosensitive polyimide is unexposed on the scanning lines 1, TFT3 and pixel electrodes 4 which are opaque parts, so that the photosensitive polyimide is removed and other parts are removed. Then, the photosensitive resin layer 7 is formed.
最後に第2図に示すように、TFT3とデータ線2および
画素電極4とを電気的に接続するため、層間絶縁膜8と
付加容量用絶縁膜6にスリーホールを形成してAl等の金
属膜を堆積し、データ線2の配線パタンを形成する。こ
れらの工程は、通常のアクティブマトリクスに用いられ
る方法が適用できる。さらに、不要な画素電極4上の不
透明膜であるMo膜は、CCl2F2とO2との混合ガスを用いた
反応性イオンエッチング法等により除去すればよい。上
記諸工程によって、本発明のアクティブマトリクスが製
作できる。Finally, as shown in FIG. 2, in order to electrically connect the TFT 3 with the data line 2 and the pixel electrode 4, three holes are formed in the interlayer insulating film 8 and the additional capacitance insulating film 6 to form a metal such as Al. A film is deposited, and a wiring pattern of the data line 2 is formed. In these steps, a method used for a normal active matrix can be applied. Further, the unnecessary Mo film which is an opaque film on the pixel electrode 4 may be removed by a reactive ion etching method using a mixed gas of CCl 2 F 2 and O 2 . Through the above steps, the active matrix of the present invention can be manufactured.
上記方法で製作したアクティブマトリクスにおけるデ
ータ線2との配線容量は、付加容量絶縁膜6をSiO2膜10
00Åとし、感光性ポリイミドの膜厚を3000Åとしたとこ
ろ、付加容量用絶縁膜6だけの場合に較べて配線容量を
約1/6に低減できた。また、感光性ポリイミドの膜厚を6
000Åと厚くしたところ、配線容量を約1/10に低減でき
るという効果があった。The wiring capacitance between the data line 2 and the active matrix manufactured by the above-described method is determined by adding the additional capacitance insulating film 6 to the SiO 2 film 10.
When the film thickness of the photosensitive polyimide was 3000 mm and the film thickness of the photosensitive polyimide was 3000 mm, the wiring capacitance could be reduced to about 1/6 as compared with the case where only the insulating film 6 for additional capacitance was used. In addition, the thickness of the photosensitive polyimide is set to 6
When the thickness was increased to 000 mm, there was an effect that the wiring capacitance could be reduced to about 1/10.
本発明の要点は、データ線と付加容量配線との間に感
光性樹脂の絶縁膜を介在させることにより、上記データ
線の配線容量を大幅に低減することにある。上記付加容
量配線は透明導体で形成されるため、画素電極上に不透
明な材料を一層設け、感光性樹脂を背面から露光するこ
とにより、ホトマスクなしの簡便な方法で、所望のデー
タ線と付加容量配線との間に感光性樹脂の絶縁膜を形成
することにある。したがって、上記感光性樹脂は配線交
差部にだけに存在すればよく、TFTや走査線部分が遮光
性であって、感光性樹脂が形成されなくても、本発明の
目的からいって全く問題はない。The gist of the present invention is to significantly reduce the wiring capacity of the data line by interposing an insulating film of a photosensitive resin between the data line and the additional capacitance wiring. Since the above-mentioned additional capacitance wiring is formed of a transparent conductor, a single layer of opaque material is provided on the pixel electrode, and the photosensitive resin is exposed from the back, so that the desired data line and the additional capacitance can be easily formed without a photomask. An object of the present invention is to form a photosensitive resin insulating film between the wirings. Therefore, the above-mentioned photosensitive resin only needs to be present only at the wiring intersection, and even if the TFT or the scanning line portion is light-shielding and the photosensitive resin is not formed, there is no problem for the purpose of the present invention. Absent.
また、本実施例では付加容量配線がデータ線とだけ交
差する場合についてだけ述べたが、走査線と交差する場
合、またはデータ線と走査線との両方と交差する場合で
あっても、感光性樹脂層を形成したのちに上記データ線
および走査線を形成するように工程を変更すれば、全く
同様に適用できることは明らかである。In this embodiment, only the case where the additional capacitance wiring intersects only with the data line has been described. If the process is changed so that the data lines and the scanning lines are formed after the formation of the resin layer, it is obvious that the same can be applied.
さらに、感光性樹脂にはネガ型感光性ポリイミドを用
いたが、本発明の主旨から特定の感光性樹脂に限定され
るわけではなく、その他のネガ型感光性樹脂、例えばポ
リイソプレン系のレジスト(日本合成ゴム CBRシリー
ズ)やゴム系レジスト(東京応化OMRシリーズ)等が適
用できることは明らかである。Furthermore, although a negative photosensitive polyimide was used as the photosensitive resin, the present invention is not limited to a specific photosensitive resin, and other negative photosensitive resins such as a polyisoprene-based resist ( It is clear that Nippon Synthetic Rubber CBR series) and rubber-based resists (Tokyo Oka OMR series) can be applied.
上記のように本発明によるアクティブマトリクスは、
画素ごとに非線形素子と画素電極とを設け、上記画素電
極の一部を付加容量の一方の電極に用いたアクティブマ
トリクスにおいて、透明導電膜で構成する付加容量配線
とデータ線および走査線の両方または一方との交差部分
が、付加容量形成用絶縁膜およびネガ型感光性樹脂層に
より、電気的に絶縁されているため、配線容量の増大を
考慮する必要なく、付加容量を形成する絶縁膜の膜厚を
任意に設定できる利点がある。さらに、従来のアクティ
ブマトリクスTFTや走査線等の配線が存在するために表
面に凹凸があり、そのため、それら凹凸の上に形成され
る配線はそれらの段差部で断線する確率が高くなり、歩
留りが低下するという欠点があった。しかし、本発明の
アクティブマトリクスではTFTを構成するSiや配線材料
が不透明膜であるため、感光性樹脂層が形成されず、上
記感光性樹脂層の厚さを調整すれば、段差部の平坦化が
できるので歩留りが向上の利点がある。As described above, the active matrix according to the present invention includes:
In an active matrix in which a non-linear element and a pixel electrode are provided for each pixel, and a part of the pixel electrode is used as one electrode of an additional capacitor, an additional capacitor wiring formed of a transparent conductive film and both a data line and a scanning line or Since the intersection with one side is electrically insulated by the insulating film for forming the additional capacitance and the negative photosensitive resin layer, it is not necessary to consider an increase in the wiring capacitance, and the film of the insulating film forming the additional capacitance is not required. There is an advantage that the thickness can be set arbitrarily. In addition, there are irregularities on the surface due to the presence of conventional wiring such as active matrix TFTs and scanning lines.Therefore, the wiring formed on those irregularities has a high probability of breaking at those steps, and the yield is high. There was a drawback of lowering. However, in the active matrix of the present invention, since the Si and the wiring material constituting the TFT are opaque films, the photosensitive resin layer is not formed, and if the thickness of the photosensitive resin layer is adjusted, the step portion is flattened. Therefore, there is an advantage that the yield is improved.
第1図は本発明によるアクティブマトリクスの一実施例
を示す画素平面図、第2図は上記実施例のA−A線矢視
方向の断面図、第3図(a)〜(e)は上記実施例の製
作方法をそれぞれ説明する図、第4図はアクティブマト
リクスの等価回路図、第5図は付加容量を形成した場合
のアクティブマトリクスの等価回路図、第6図は付加容
量を形成した場合の従来例の画素断面図、第7図は付加
容量を形成した場合のアクティブマトリクスの概念図
で、(a)はデータ線と付加容量配線とが交差する場合
を示す図、(b)は走査線とデータ線との両方に付加容
量配線が交差する場合を示す図である。 1……走査線 2……データ線 3……非線形素子 4……画素電極 5……付加容量配線 6……付加容量形成用絶縁膜 7……ネガ型感光性樹脂層FIG. 1 is a plan view of a pixel showing an embodiment of an active matrix according to the present invention, FIG. 2 is a cross-sectional view of the above embodiment taken along the line AA, and FIGS. FIGS. 4A and 4B are diagrams illustrating a manufacturing method of the embodiment, FIG. 4 is an equivalent circuit diagram of an active matrix, FIG. 5 is an equivalent circuit diagram of an active matrix when an additional capacitor is formed, and FIG. FIG. 7 is a conceptual diagram of an active matrix when an additional capacitance is formed. FIG. 7A is a diagram showing a case where a data line and an additional capacitance line intersect, and FIG. FIG. 10 is a diagram illustrating a case where an additional capacitance line intersects both a line and a data line. DESCRIPTION OF SYMBOLS 1 ... Scanning line 2 ... Data line 3 ... Non-linear element 4 ... Pixel electrode 5 ... Additional capacitance wiring 6 ... Insulating film for additional capacitance formation 7 ... Negative photosensitive resin layer
───────────────────────────────────────────────────── フロントページの続き (72)発明者 萩原 昇 東京都千代田区内幸町1丁目1番6号 日本電信電話株式会社内 (56)参考文献 特開 平1−283519(JP,A) 特開 昭60−230118(JP,A) ──────────────────────────────────────────────────続 き Continuation of front page (72) Inventor Noboru Hagiwara Nippon Telegraph and Telephone Corporation, 1-6-1, Uchisaiwaicho, Chiyoda-ku, Tokyo (56) References JP-A-1-283519 (JP, A) JP-A Sho 60−230118 (JP, A)
Claims (2)
け、上記画素電極の一部を付加容量の一方の電極に用い
たアクティブマトリクスにおいて、透明導電膜で構成す
る付加容量配線とデータ線および走査線の両方または一
方との交差部分が、付加容量形成用絶縁膜およびネガ型
感光性樹脂層により、電気的に絶縁されていることを特
徴とするアクティブマトリクス。In an active matrix in which a non-linear element and a pixel electrode are provided for each pixel, and a part of the pixel electrode is used as one electrode of an additional capacitor, an additional capacitor wiring formed of a transparent conductive film, a data line and An active matrix, wherein an intersection of both or one of the scanning lines is electrically insulated by an additional capacitance forming insulating film and a negative photosensitive resin layer.
け、上記画素電極の一部を付加容量の一方の電極に用い
たアクティブマトリクスの製作法において、透明基板の
主表面上に透明導電膜により付加容量配線を形成したの
ち、付加容量形成用絶縁膜を堆積し、続いて透明導電膜
と不透明導電膜との2層膜で画素電極を形成し、ネガ型
感光性樹脂を塗布して基板の背面から露光を行い、上記
不透明導電膜等の遮光部分以外の領域上に上記ネガ型感
光性樹脂層を形成し、上記領域にネガ型感光性樹脂層と
上記付加容量形成用絶縁膜からなる絶縁膜を形成して、
上記絶縁膜上にデータ線または走査線、あるいはその両
方を形成する工程を含むことを特徴とするアクティブマ
トリクスの製作法。2. A method of manufacturing an active matrix in which a non-linear element and a pixel electrode are provided for each pixel, and a part of the pixel electrode is used as one electrode of an additional capacitor, wherein a transparent conductive film is formed on a main surface of a transparent substrate. After forming an additional capacitance line, an insulating film for forming an additional capacitance is deposited, a pixel electrode is formed with a two-layer film of a transparent conductive film and an opaque conductive film, and a negative photosensitive resin is applied to the substrate. Exposure from the back surface of the opaque conductive film and the like, the negative photosensitive resin layer is formed on a region other than the light-shielding portion, and the region includes the negative photosensitive resin layer and the insulating film for forming an additional capacitance. Form an insulating film,
A method for manufacturing an active matrix, comprising a step of forming a data line and / or a scanning line on the insulating film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP25205988A JP2616976B2 (en) | 1988-10-07 | 1988-10-07 | Active matrix and its manufacturing method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP25205988A JP2616976B2 (en) | 1988-10-07 | 1988-10-07 | Active matrix and its manufacturing method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH02100024A JPH02100024A (en) | 1990-04-12 |
JP2616976B2 true JP2616976B2 (en) | 1997-06-04 |
Family
ID=17231991
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP25205988A Expired - Fee Related JP2616976B2 (en) | 1988-10-07 | 1988-10-07 | Active matrix and its manufacturing method |
Country Status (1)
Country | Link |
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JP (1) | JP2616976B2 (en) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2531795Y2 (en) * | 1990-11-28 | 1997-04-09 | 自動車機器株式会社 | Power steering device |
US5414278A (en) * | 1991-07-04 | 1995-05-09 | Mitsushibi Denki Kabushiki Kaisha | Active matrix liquid crystal display device |
US5719065A (en) | 1993-10-01 | 1998-02-17 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device with removable spacers |
US5814529A (en) | 1995-01-17 | 1998-09-29 | Semiconductor Energy Laboratory Co., Ltd. | Method for producing a semiconductor integrated circuit including a thin film transistor and a capacitor |
EP1031873A3 (en) * | 1999-02-23 | 2005-02-23 | Sel Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and fabrication method thereof |
JP3989761B2 (en) | 2002-04-09 | 2007-10-10 | 株式会社半導体エネルギー研究所 | Semiconductor display device |
US7038239B2 (en) | 2002-04-09 | 2006-05-02 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor element and display device using the same |
US7256421B2 (en) | 2002-05-17 | 2007-08-14 | Semiconductor Energy Laboratory, Co., Ltd. | Display device having a structure for preventing the deterioration of a light emitting device |
-
1988
- 1988-10-07 JP JP25205988A patent/JP2616976B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPH02100024A (en) | 1990-04-12 |
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