JP2615727B2 - Control device for error correction circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control device of an error correction circuit applied to, for example, a reproduction circuit of a digital audio disk (a so-called compact disk).

[Conventional technology]

In a digital audio disc, an error correction code called a cross interleaved Reed-Solomon code (CIRC code) is used as an error correction code. This error correction code forms a first error correction code sequence (C2 code) consisting of one word included in each of the PCM data sequences of a plurality of channels in the first arrangement state and a first check word corresponding thereto. Then, the PCM data sequence of the plurality of channels and the first check word sequence are interleaved to delay differently for each channel to form a second arrangement state, and the PCM data of the plurality of channels in the second arrangement state and the first check A second error correction code sequence (C1 code) including one word included in each of the word sequences and a second check word corresponding thereto is formed. On the decoding side, decoding of the C1 code (C1 decoding)
And C2 decoding (C2 decoding) is performed, and C2 decoding is performed using the pointer information obtained by the C1 decoding.

As shown in FIG. 11, in the conventional CIRC code, the C1 code sequence (C1 sequence) is composed of two adjacent frames (one frame: 3).
The C2 code sequence (C2 sequence) is formed by 28 symbols included in a predetermined frame in 108 frames.

During cue and review, track jumps occur continuously, and discontinuity of frames occurs in the reproduced RF signal from the digital audio disk. Since the interleave length of the C1 code is only one frame, in ± 1 frames before and after the discontinuity point, the C1 pointer indicating that there is an error is set only in two frames. On the other hand, in the C2 sequence, since the interleave length is 108 frames, a multiplex error occurs in 108 frames after the discontinuous portion.

In the C2 decoding, if there are three or more errors and the number of C1 pointers is two or more, the C1 pointer is copied and used as a flag indicating whether data is valid or invalid. Therefore, in the case of the multiplex error of the C2 sequence that occurs in the above-described discontinuous portion, the copy operation of the C1 pointer is performed.
The reproduced data processed in this way is output after error interpolation, but a reproduced sound (that is, noise) in which sounds before and after the discontinuous portion are mixed is generated.

Similar noise is generated not only in the queue and the review but also when the memory for deinterleaving overflows.

Conventionally, in order to make the above-mentioned noise at the time of cueing and review less conspicuous, a gain at the time of reproduction is reduced, for example, by -12 dB, or passive measures such as muting are taken.

As a countermeasure against the above problem, Japanese Patent Application Laid-Open No.
Proposals described in the AS Conference '86 proceedings (pages 90 to 93) have been proposed.

In addition, the applicant of the present application not only reproduces audio PCM signals, but also uses [C1 decoding → C2 decoding →
C1 decoding → C2 decoding] and C1 decoding and C2 decoding twice,
In the first C2 decoding, an error correction method for performing quadruple erasure correction using the C1 pointer obtained in the preceding C1 decoding is proposed.

[Problems to be solved by the invention]

However, if the quadruple erasure correction is performed in the C2 decoding, a problem arises in that it is not possible to check for erroneous correction of the C1 decoding at the preceding stage or to overlook an error during the C2 decoding. That is, 4
The heavy erasure correction is performed with respect to a known error position indicated by a pointer obtained by C1 decoding. If the error correction is incorrect in the C1 correction, the erasure correction is also lost.

There are two cases where error correction is wrong in C1 decoding. One of them is a case where erroneous correction occurs due to multiple correction in C1 decoding. The second is a case where an error is included in the C2 sequence even if the C1 correction itself corrects the error. The latter case occurs when the above-described frame discontinuity occurs.

Accordingly, an object of the present invention is to provide a control device for an error correction circuit that can prevent erroneous erasure correction when performing erasure correction using the C1 pointer in C2 decoding.

[Means for solving the problem]

According to the present invention, a plurality of symbols in a first arrangement state are encoded with a first error correction code capable of m-level error correction and erasure correction of an n-level error, and the plurality of symbols and the first symbol are encoded. The arrangement of the first check symbols of the error correction code is rearranged to a second arrangement state, and the plurality of symbols and the first arrangement in the second arrangement state are arranged.
In the control device for an error correction circuit configured to decode a check symbol of which has been encoded with a second error correction code capable of k-fold error correction, the decoding process is in the second arrangement state. For a plurality of symbols, a second error correction code performs error correction of up to a predetermined number of error symbols equal to or less than k, and sets an error pointer for at least a predetermined number of error symbols. A second step of converting the second arrangement state to the first arrangement state; and setting a plurality of symbols in the first arrangement state by the first error correction code in the first step. A third step of performing erasure correction of error symbols up to n indicated by the indicated error pointer, and changing the first arrangement state to the second arrangement. A fourth step of converting to a state, and, for a plurality of symbols in the second arrangement state, performing error correction of a predetermined number of error symbols equal to or less than k using a second error correction code, and A fifth step of setting an error pointer for more error symbols, a sixth step of converting a second arrangement state to a first arrangement state, and a plurality of symbols in the first arrangement state And a seventh step of performing error correction of a predetermined number of error symbols equal to or less than m by using the first error correction code with reference to the error pointer set in the fifth step. Means for prohibiting the erasure correction processing in the third step for a predetermined period of time equal to or longer than the interleave length of the first error correction code when the discontinuity occurs. By providing a control device of an error correction circuit according to claim.

[Action]

When frame discontinuity occurs, only two frames of the C1 code sequence are interleaved, so that only two frames of the C1 sequence in the discontinuous portion are detected as errors. Multiple errors have occurred in the C2 sequence including discontinuous parts. In this case, if the erasure correction is performed by trusting the C1 pointer, the erasure correction is incorrect. In the present invention,
Since erasure correction is prohibited for a predetermined period when frame discontinuity occurs, the erroneous erasure correction described above can be prevented.

〔Example〕

Hereinafter, an embodiment of the present invention will be described. This description is made in the following order.

a. Digital audio disk playback circuit b. Synchronous signal detection and protection circuit c. Error correction circuit a. Digital audio disk playback circuit FIG. 1 shows a digital audio disk playback circuit to which the present invention can be applied. This is an example. In FIG. 1, reference numeral 1 denotes a digital audio disc.
An RF signal reproduced from the digital audio disk 1 by the optical pickup 2 is supplied to an RF amplifier 3.

FIG. 2 shows a frame structure of an RF signal reproduced from a digital audio disk. At the beginning of one frame, a frame synchronization signal of 24 channel bits is located, and then one symbol of a subcode for control and display is located. After this, the audio PCM signal (12 symbols), the parity of the error correction code (4 symbols), the audio PCM signal (12 symbols) and the parity (4 symbols) are sequentially located. One symbol is 14 channel bits. One frame has a length of 588 channel bits as described below.

24 × 14 (audio signal) + 8 × 14 (parity) + 1 ×
14 (sub code) + 24 (frame synchronization signal) + 34 x 3
(Margin bit) = 588 channel bits The output signal of the RF amplifier 3 is supplied to the clock extraction circuit 4 composed of a PLL. The reproduced RF signal and the bit clock from the clock extraction circuit 4 are supplied to a frame synchronization detection and protection circuit 5. The frame synchronization detection and protection circuit 5 detects a frame synchronization signal and protects the detected frame synchronization signal, as described later.

An EFM demodulation circuit 6 is provided at the output of the frame synchronization detection and protection circuit 5. The EFM modulation is a channel coding for converting a one-symbol 8-bit pattern into a preferable 14-bit pattern (in a sense that a DC component can be reduced and a bit clock can be easily extracted). The reproduction data in which one symbol is returned to 8 bits by the EFM demodulation circuit 6 is supplied to the decoding circuit 7.

In the decoding circuit 7, an error correction code (referred to as a cross-interleaved Reed-Solomon code (CIRC code))
Is decoded. A memory 8 in which reproduction data is written for deinterleaving or the like is provided in association with the decoding circuit 7. A signal indicating that the frame synchronization is not locked due to a track jump or the like is supplied from the frame synchronization detection and protection circuit 5 to the decoding circuit 7. The decoding circuit 7 includes a system controller 14
Supplies a track jump command generated during operations such as cueing and review.

The reproduced audio data output from the decoding circuit 7 is supplied to the data interpolation circuit 9. In the data interpolation circuit 9,
The error data that could not be corrected by the decoding circuit 7 is subjected to interpolation such as average value interpolation and previous value hold. The output signal of the data interpolation circuit 9 is supplied to D / A converters 10L and 10R, and the audio PCM signal is returned to an analog signal.
Output signals of these D / A converters 10L and 10R are taken out to output terminals 12L and 12R via low-pass filters 11L and 11R.

A subcode demodulation circuit 13 is provided on the output side of the frame synchronization detection and protection circuit 5. Subcode demodulation circuit 13
Are supplied to the system controller 14. Operation unit related to the system controller 14
15 and a display unit 16 are provided.

Motor for rotating digital audio disk 1
17 is driven at a CLV (constant linear velocity) by a spindle servo circuit 18. In connection with the optical pickup 2, a feed servo circuit 19, a tracking servo circuit 20, and a focus servo circuit 21 are provided.

b. Synchronization signal detection and protection circuit FIG. 3 shows an example of the frame synchronization detection and protection circuit 5. In FIG. 3, 31 and 32 are respectively (mod.588)
The following shows the counter of. The counter 31 counts the clock PLC from the terminal 33, and the counter 32 counts the clock F from the terminal 34.
Count the IC. The clock PLC is a bit clock extracted from the reproduced RF signal by the clock extraction circuit 4. The clock FIC is, for example, a crystal oscillation circuit (not shown)
Is a fixed stable clock formed by The frequency of the clock FIC is equal to the center frequency of the clock PLC 4.
3218 MHz.

The outputs of the counters 31 and 32 are supplied to decoders 35 and 36, respectively. The output of the counter 31 is 588 from the decoder 35.
The interpolation synchronization signal NSYNC is generated every time, and the window signal LMASK which becomes “1” with a width of (± 8 clocks) is generated from the decoder 36 around the timing when the output of the counter 32 becomes 588. . Counters 31 and 32 are AND gates
Reset by the detection synchronization signal MKDSY from 41.

Reference numeral 37 denotes a shift register.
The reproduction RF signal EFM is captured by the clock PLC. The shift register 37 is a 23-bit shift register.
The output signal of 37 is supplied to the frame synchronization detection circuit 40.
The frame synchronization detection circuit 40 detects a frame synchronization signal having a predetermined bit pattern. The reproduction synchronization signal SYNC from the synchronization detection circuit 40 is supplied to the AND gate 41. The window signal MASK from the OR gate 57 is supplied as the other input signal of the AND gate 41.

The detection synchronization signal MKDSY from the AND gate 41 is supplied to the counters 31 and 32 as a reset signal, and is also supplied to the AND gate 42 and the inverter 43. The output signal of the inverter 43 is supplied to the AND gate 44. These AND gates 42 and 44 are supplied with the interpolation synchronization signal NSYNC from the decoder 35. The signal GDSY is extracted from the AND gate 42, and the signal NGSY is extracted from the AND gate 44. The signal GDSY is a signal obtained when the detection synchronization signal MKDSY and the interpolation synchronization signal NSYNC are simultaneously generated. The signal NGSY is generated when the interpolation synchronization signal NSYNC occurs.
This signal is obtained when the detection synchronization signal MKDSY does not occur. Further, an RS flip-flop 45 that is set and reset by these signals GDSY and NGSY is provided, and the signal GFS is extracted from the RS flip-flop 45.

The above-described interpolation synchronization signal NSYNC and detection synchronization signal MKDSY are supplied to an OR gate 46, and a reset (RESET) signal is extracted from an output terminal 47. This reset signal is an output signal that defines the timing corresponding to the frame synchronization signal in the reproduced RF signal. That is, each symbol of the reproduced RF signal is separated based on the reset signal which is the data clock.

The signal GDSY from the AND gate 42 is supplied to the N1 counter 48 as a clock input. Signal NGSY from AND gate 44
Is supplied to the N2 counter 49 as a clock input. The carry output of the N1 counter 48 is used as its own reset input via an OR gate 50, and the RS flip-flop 52
Reset input. As the other input of the OR gate 50, the output signal GDF of the RS flip-flop 52 is supplied.

The carry output of the N2 counter 49 is used as its own reset input via the OR gate 51, and is supplied to the OR gate 53. As the other input of the OR gate 51, a detection synchronization signal MKDSY is supplied. The OR gate 53 has an AND gate
The output signal of 54 and the signal from terminal 55 are supplied. AND
The gate 54 is supplied with the output signal GDF and the signal NGSY of the RS flip-flop 52. The signal from the terminal 55 is a signal that becomes “1” when a tracking error or the like occurs. This signal is used for control to remove forward protection after a track jump.

The output signal of the OR gate 53 becomes SR flip-flops 52 and 56.
Are supplied as respective set inputs. As a reset input of RS flip-flop 56, detection synchronization signal MKDS
Y is supplied. The signal GTOP obtained at the output of the RS flip-flop 56 is supplied to the OR gate 57. This OR gate 57
Is supplied with a window signal LMASK.

The above-mentioned N1 counter 48 is provided for protection (backward protection) for detecting that the signal GDSY has been generated N1 times, that is, that the detection of frame synchronization is locked. on the other hand,
The N2 counter 49 is provided for protection (forward protection) for detecting that the signal NGSY has occurred N2 times, that is, unlocking. As an example, (N1 = 2) and (N2 = 3) are set.

FIG. 4 is a timing chart showing the operation of the embodiment. FIG. 4A shows the reproduction synchronization signal SYNC from the frame synchronization detection circuit 40. FIG. 4B shows the window signal MASK supplied to the AND gate 41. Normally, Fig. 4 J
Is "0", the window signal LMASK from the decoder 36 becomes the window signal MASK. Accordingly, the detection synchronization signal MKDSY shown in FIG. 4C is obtained.

FIG. 4D shows the interpolation synchronization signal NS generated from the decoder 35.
Indicates YNC. Interpolation synchronization signal NS
The YNC contains bit slips or erasures whose period differs from the normal one. The detection synchronization signal MKDS shown in FIG. 4C
A signal GDSY shown in FIG. 4E and a signal NGSY shown in FIG. 4F are formed from Y and the interpolation synchronization signal NSYNC.

The signal GDSY is supplied to the N1 counter 48, and the output of the N1 counter 48 changes as shown in FIG. 4G. Since (N1 = 2) is set, the N1 counter 48 generates a carry output when counting up to 2, and by this carry output,
The N1 counter 48 and the RS flip-flop 52 are reset. Therefore, the output signal GDF of the RS flip-flop 52 is "0" as shown in FIG. Also, if the signal NGSY is N2
The output of the N2 counter 49 is supplied to the
Changes as shown in FIG. Since the N2 counter 49 is reset by the detection synchronization signal MKDSY, no carry output from the N2 counter 49 occurs. Therefore, the signal GTOP from the RS flip-flop 56 is, as shown in FIG.
It is “0”.

The OR gate 46 has the interpolation synchronization signal NSYNC and the detection synchronization signal M
Since KDSY is supplied, the output terminal 47
Are taken out. When both the interpolation synchronization signal NSYNC and the detection synchronization signal MKDSY occur in the reset signal, the interpolation synchronization signal NSYNC and the detection synchronization signal MKDSY are generated.
The period between KDSY is the period of the burst error. However, the period of this burst error is relatively short and can be corrected by the error correction code of the digital audio disk.

FIG. 5 is a timing chart showing the operation when an error occurs in the reproduction synchronization signal at the time of a track jump or the like. As shown in FIG. 5A, the reproduction synchronizing signal has disappeared or an incorrect reproduction synchronizing signal (marked with x) has occurred. When the signal GTOP (Fig. 5J) is "0", the decoder
In FIG. 36 to FIG. 5B, a window signal LMASK having a width of (± 8 clocks) is generated. Accordingly, a detection synchronization signal MKDSY shown in FIG. 5C is obtained. This detection synchronization signal M
Since the counter 31 is reset by KDSY, the interpolation synchronization signal NSYNC shown in FIG. 5D is generated. Therefore, even when the reproduction synchronizing signal disappears, the interpolation synchronizing signal NSYNC is obtained, and a reset signal is obtained at the output terminal 47 as shown in FIG. 5K.

FIGS. 5E and 5F show signals GDSY and NGSY, respectively. These signals GDSY and NGSY are counted by the N1 counter 48 and the N2 counter 49, and their outputs change as shown in FIGS. 5G and 5H. When three signals NGSY are counted, a carry output is generated from the N2 counter 49, and the RS flip-flops 52 and 56 are set. Therefore, as shown in FIGS. 5I and 5J, the signal GDF and the signal GTOP become "1". The RS flip-flop 56 detects the detection synchronization signal MK
Since the signal G is reset by DSY, the signal G shown in FIG.
TOP occurs. Further, the RS flip-flop 56 is set by the signal NGSY generated during the period when the signal GDF is “1”.

When the N1 counter 48 counts two signals GDSY,
A carry output is generated from the N1 counter 48, and the RS flip-flop 52 is reset. Accordingly, the signal GDF falls as shown in FIG. 5I.

The reset signal shown in FIG. A burst error occurs while the signal GTOP is "1". The period of this error can be shortened.

As is clear from the above description of the operation, the N1 counter 48
Performs a backward protection operation to detect that the frame synchronization detection operation has returned to normal. The N2 counter 49 performs a forward protection operation for detecting that a frame synchronization detection operation is incorrect. By the protection of both, it is possible to quickly detect that the detection operation of the frame synchronization has become abnormal and that the detection operation has returned to normal.

c. Error Correction Circuit An error correction circuit provided in the decoding circuit 7 and to which the present invention can be applied will be described with reference to FIG.
FIG. 6 is a diagram showing the order of decoding as a block diagram.

The playback signal from the digital audio disc is EF
It is supplied from the M demodulation circuit 6. 32 symbols in one frame are supplied to the delay processing stage, only the even symbols are delayed by one frame, and the delay given by the delay circuit on the encoder side is canceled. 32 symbols from delay processing stage 61 are C1
The C1 decoder 62 supplies the supplied (32, 28) Reed-Solomon code to the decoder 62. In the C1 decoder 62, C1
Up to two error symbols in the sequence are corrected. C1
When three or more errors are detected in the decoder 62, it is determined that all symbols in the C1 sequence have an error.
The C1 pointer is set.

The data corrected by the C1 decoder 62 and the C1 pointer are processed in a deinterleave processing stage 63. The deinterleave processing stage 63 performs a process of restoring the interleaving performed on the encoder side, and performs a deinterleave processing stage.
The output of 63 is provided to C2 decoder 64. The C1 pointer of each symbol generated by the C1 decoder 62 undergoes the same deinterleaving processing as the data in the deinterleaving processing stage 63. The delay processing and deinterleaving can be performed by address control when reading data from the RAM. The C1 pointer is written into a part of the memory area of the RAM, and receives the same address control as that of the data. Using the C1 pointer, the C2 decoder 64 corrects up to two symbol errors and performs erasure correction of triple errors and quadruple errors.

Data from the C2 decoder 64 is provided to an interleaving stage 65. The interleave processing stage 65 returns the data arrangement to the same arrangement as at the time of reproduction. The output data of the interleave processing stage 65 is supplied to the delay processing stage 66, and one frame (32 symbols) of data is obtained from the delay processing stage 66. Actually, since the data corrected by the C1 decoder 62 and the C2 decoder 64 is stored in the RAM, the processing of the interleave processing stage 65 and the delay processing stage 66 is controlled by controlling the read address of this data. I can do it.

A second decoding process is performed from the interleave processing stage 65. The second decoding process is the same as the decoding of a Reed-Solomon code in a known digital audio disc reproducing circuit.

The data of 32 symbols from the delay processing stage 66 is converted to the C1 decoder 67.
Supplied to The C1 decoder 67 decodes the (32,28) Reed-Solomon code and corrects up to a double error. The C1 decoder 67 sets the C1 pointer not only when there are three or more errors but also when a double error is corrected.

Output data from the C1 decoder 67 is supplied to a deinterleave processing stage 68, where the data is deinterleaved. Data of 28 symbols from the deinterleaving stage 68
The signal is supplied to the C2 decoder 69, where the (28, 24) Reed-Solomon code is decoded. The C2 decoder 69 corrects up to a double error with reference to the number and state of the C1 pointer. The output data from the C2 decoder 69 is supplied to a descramble processing stage 70, and a process reverse to the scramble process performed on the encoder side is performed.

As described above, triple and quadruple erasure correction is performed in the C2 decoder 64 using the C1 pointer generated by the C1 decoder 62, so that the number of error symbols that can be corrected increases, and the error correction capability is improved. Can be planned. By performing C1 decoding and C2 decoding again, it is possible to reduce the risk of erroneous correction.

FIG. 7 is a flowchart showing the operation of the C1 decoder 62. In the case of a one-symbol error and a two-symbol error, error correction is performed. The C1 pointer is set when a two-symbol error is corrected and when an error is three or more symbols. Even if a two-symbol error is corrected, the reason why the C1 pointer is set is that the probability of erroneous C1 correction is high. To correct the erasure correction in the next-stage C2 decoding, the C1 pointer is set. C1 pointer is required. When there is no error and when one symbol error is corrected, it is determined whether the C1 pointer is forcibly set.

If the C1 pointer is forcibly set, the C1 pointer is set; otherwise, the C1 pointer is cleared. Whether the C1 pointer is forcibly set is determined according to the flowchart shown in FIG. As shown in FIG. 8, after the track jump command is input from the microcomputer, the signal GTOP becomes "1".
, The C1 pointer is forcibly set. Alternatively, when the signal RAOF indicating that the RAM has overflowed becomes "1", the C1 pointer is forcibly set. C1
A forced set of pointers is made for the next 128 frames when frames become discontinuous. Where 128
The frame is a value obtained according to the following equation.

74 + 28 + 16 = 118 ≒ 128 (frames) 74: Mixed period of data before and after the discontinuity determined by the interleave relationship 28: ± 28 frame jitter margin 16: Number of forward protection of frame synchronization (described above) Example of the value of N2 which was set to 3 in the frame synchronization and protection circuit of the above) As described above, when the frame becomes discontinuous due to a track jump or the like, C is forcibly applied for a period of 128 frames.
By setting the one pointer, the correction by the C2 decoder 64 becomes impossible, and the sound before and after the discontinuity is mixed with each other is prevented.

FIG. 9 is a flowchart showing the decoding operation of the C2 decoder 64. FIG. 9 shows a decoding process after it is determined that there is no error, one symbol error, two symbol errors, three symbol errors, four symbol errors, and five or more symbol errors. Further, the processing of the pointer is omitted.

When there is no error, in the case of one symbol error and in the case of two symbol error, error correction is performed. In the case of a 3-symbol error and a 4-symbol error, it is determined whether or not erasure correction is prohibited.
Unless prohibited, triple erasure correction and 4
Heavy erasure correction is performed. If erasure correction is prohibited or if there are more than 5 symbols,
No erasure correction.

The erasure correction is prohibited when frame discontinuity occurs. This discontinuity occurs when the signal GTOP is set to “1”.
Or the signal RAOF becomes “1”. The erasure correction is prohibited for a period of 180 frames from the detection of the discontinuity of the frame. The period of 180 frames is determined by the following condition.

108 + 56 + 16 = 180 (frames) 108: Interleave length 56: At the time of jitter margin of ± 28 frames 16: Number of forward protection of frame synchronization (example of N2 value which was set to 3 in the frame synchronization and protection circuit described above) As described above , Forcibly set the C1 pointer for a period of 128 frames, and in C2 decoding,
FIG. 10 shows an example of an error correction control circuit for inhibiting erasure correction over the period of a frame.

In FIG. 10, a signal GTOP from the frame synchronization detection and protection circuit 5 is supplied to an input terminal indicated by reference numeral 71. As described above, this signal GTOP includes a predetermined number of signals NGSY, for example, 16 signals.
This signal becomes "1" after counting. A signal RAOF which becomes "1" when the memory 8 (RAM) overflows is supplied to an input terminal indicated by 72. This signal RAOF compares the output of the write address counter of the memory 8 with the output of the read address counter, and the difference between the two is 28.
(Jitter margin), the signal becomes “1”.
A track jump command (“1”) at the time of cue, review or the like is supplied from the microcomputer to the input terminal indicated by 73. The input terminal indicated by 74 is supplied with a clock of one frame period supplied from the read address generation circuit of the memory 8.

A control signal for forcibly setting the C1 pointer is extracted from an output terminal indicated by reference numeral 75, and a control signal for inhibiting erasure correction is extracted from an output terminal indicated by reference numeral. Output terminal 75 is connected to the output of RS flip-flop 77, and output terminal 76 is connected to the output of D flip-flop 78.

Reference numeral 79 denotes a 7-bit counter. The output of the counter 79 is supplied to the NAND gate 80. From the NAND gate 80, an output signal that falls when the counter 79 counts 128 clocks RFCK is generated. Reference numeral 81 denotes an 8-bit counter. The output of the counter 81 is supplied to a NAND gate 82. From the NAND gate 82, an output signal that falls when the counter 81 counts 180 clocks RFCK is generated. The clock RFCK is output via the falling detection circuit 83.
The signals are supplied to the AND gates 84 and 85, and the output signal of the AND gate 84 is used as the clock input of the counter 79, and the output signal of the AND gate 85 is used as the clock input of the counter 81.

The signal RAOF for detecting the RAM overflow is supplied to the D flip-flop 86 and the OR gate 87. OR gate 87
As the other input signal, a track jump command from the terminal 73 is supplied. The output of the OR gate 87 is used as the set input of the RS flip-flop 88 and is supplied to the OR gate 89. The output signal of the OR gate 89 is supplied to the load terminal of the counter 79. The signal GTOP is supplied as the other input of the OR gate 89.

The RS flip-flop 88 is set by a signal RAOF or a track jump instruction, and its output signal is
Supplied to 0. The output of the AND gate 90 is supplied to the RS flip-flop 77 as a set input. As the other input signal of the AND gate 90, the output signal of the OR gate 91 is supplied. The OR gate 91 has a signal GTOP and a D flip-flop.
86 output signals are provided. Therefore, the RS flip-flop 88 is controlled by the signal RAOF or the track jump command.
When the signal GTOP or the signal RAOF (the output of the D flip-flop 86) is supplied while being set, the RS flip-flop 77 is set, and the forced setting of the C1 pointer is started.

When the counter 79 detects 128 frame periods after the forced setting of the C1 pointer is started, the NAND gate 80
Becomes "0", and this fall is detected by the fall detection circuit 92. Fall detection circuit 92
, The RS flip-flops 77 and 88 are reset, and the forced setting operation of the C1 pointer ends.

The signal GTOP and the signal RAOF are supplied to an OR gate 93, and the output of the OR gate 93 is supplied to a load terminal of the counter 81. When the output of the OR gate 93 is supplied to the load terminal, the output of the counter 81 is no longer "1".
The output signal of the NAND gate 82 becomes “1”. Therefore, the control signal taken out from the D flip-flop 78 to the output terminal 76 becomes "1", and the inhibition of the erasure correction is started.

When the counter 81 counts 180 clocks passed through the AND gate 85, the output signal of the NAND gate 82 becomes “0”,
The control signal output to the output terminal 76 is also "0". Accordingly, the operation of prohibiting erasure correction is released.

The control signal for forcibly setting the C1 pointer obtained at the output terminal 75 and the control signal for inhibiting the erasure correction obtained at the output terminal 76 are supplied to the microcomputer for controlling the decoding circuit 7. Is done.

〔The invention's effect〕

According to the present invention, by performing quadruple erasure correction, the error correction capability can be improved. Further, the present invention provides an error correction using the C1 code and an error pointer set (first step), and an erasure correction up to n using the C2 code performed by referring to the error pointer set in the first step (third step). ), Error correction by C1 code (fifth step), error correction by C2 code (seventh step),
Error correction capability can be improved. Further, according to the present invention, when the C1 pointer becomes unreliable due to the discontinuity of the frame, the erasure correction is prohibited, so that erroneous erasure correction can be prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of a digital audio disc reproducing system to which the present invention can be applied;
FIG. 2 is a schematic diagram used to explain the frame configuration of a reproduced signal of a digital audio disk, FIG. 3 is a block diagram of an example of a frame synchronization detection and protection circuit, and FIGS. 4 and 5 are frame synchronization detection and protection. FIG. 6 is a timing chart for explaining the operation of the circuit, FIG. 6 is a block diagram used for describing an error correction circuit to which the present invention can be applied,
7 and 8 are flowcharts used for explaining C1 decoding, FIG. 9 is a flowchart used for explaining C2 decoding, and FIG.
FIG. 10 is a block diagram of a control device of the error correction circuit, and FIG. 11 is a schematic diagram used for explaining a cross interleaved Reed-Solomon code to which the present invention can be applied. Explanation of main symbols in drawings 1: Digital audio disc, 4: Clock extraction circuit, 5: Frame synchronization detection and protection circuit, 62, 67: C1 decoder, 64, 69: C2 decoder, 75: Force C1 pointer Output terminal of control signal to set erroneously, 76: Output terminal of control signal to inhibit erasure correction.

Claims (1)

(57) [Claims] 1. A plurality of symbols in a first arrangement state are encoded with a first error correction code capable of m-level error correction and erasure correction of n-level errors. The first of the first error correction codes
Are rearranged into a second arrangement state, and the second plurality of symbols and the first check symbol in the second arrangement state are k-th error-correctable second arrangements. In the control device of the error correction circuit configured to decode the coded error correction code, the decoding process may be performed on the plurality of symbols in the second arrangement state.
A first step of performing error correction of up to a predetermined number of error symbols equal to or less than k by the second error correction code, and setting an error pointer for at least the number of error symbols exceeding the predetermined number; A second step of converting the second arrangement state to the first arrangement state; and a plurality of symbols in the first arrangement state,
A third step of performing the erasure correction of up to n error symbols indicated by the error pointer set in the first step by the first error correction code, and A fourth step of converting to the second arrangement state; and a plurality of symbols in the second arrangement state,
A fifth step of performing error correction of a predetermined number of error symbols equal to or less than k using the second error correction code, and setting an error pointer for at least the number of error symbols exceeding the predetermined number; A sixth step of converting a second arrangement state to the first arrangement state; and a plurality of symbols in the first arrangement state,
A seventh step of performing error correction of a predetermined number of error symbols equal to or less than m by using the first error correction code and referring to the error pointer set in the fifth step. When the discontinuity occurs, the first
A predetermined period equal to or longer than the interleave length of the error correction code of
A control device for an error correction circuit, further comprising means for inhibiting the erasure correction processing in the third step.