JP2615113B2 - Cache memory - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory and, for example, to a technique effective for use in a directory memory for forming a hit signal.

[Conventional technology]

As a cache memory constituted by a one-chip semiconductor integrated circuit, there is, for example, “Nikkei Microdevice”, April 1987, pages 76 to 90, published by Nikkei McGraw-Hill 1987.

In the cache memory, a dual-port static memory cell is used as a tag memory (directory memory), and a static memory cell is used as a data memory.

[Problems to be solved by the invention]

In the above-described cache memory, a static memory cell including a pair of information storage MOSFETs, an address selection MOSFET, and a total of six resistive elements is used for the memory part, or a basic type thereof is used. The structure has a problem that the number of elements is large and high integration cannot be achieved.

An object of the present invention is to provide a cache memory that achieves high integration.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[Means for solving the problem]

The outline of a typical invention disclosed in the present application will be briefly described as follows. That is,
MOSF for address selection of each information in cache memory
Each data is stored using a dynamic memory cell including an ET and an information storage capacitor.

(Operation)

According to the above-described means, the number of elements required for storage information of a unit can be reduced to two, so that high integration is possible.

〔Example〕

FIG. 1 is a circuit diagram showing an embodiment of a tag (directory) memory and a high-speed comparison circuit in a cache memory according to the present invention. Each circuit element in the figure is formed along with other circuit elements constituting the cache memory on a single semiconductor substrate such as single crystal silicon, although not particularly limited by a known semiconductor integrated circuit manufacturing technique. .

A more specific structure of the integrated circuit is roughly described as follows.

That is, of the surface portion of the semiconductor substrate made of single-crystal P-type silicon and having the N-type well region formed thereon, except for the surface portion which is made the active region, in other words, the semiconductor wiring region, the capacitor formation region, and the N-channel region. A field insulating film having a comparatively thick thickness formed by a known selective oxidation method is formed on portions other than the source, drain, and surface portions of the P-channel MOSFET which are formed as channel forming regions (gate forming regions). The capacitor formation region is not particularly limited, but on the capacitor formation region,
A first polysilicon layer is formed via an insulating film (oxide film) having a relatively small thickness. The first polysilicon layer extends to above the field insulating film. On the surface of the first polysilicon layer, a thin oxide film formed by thermal oxidation of itself is formed. A channel is formed on the surface of the semiconductor substrate in the capacitor formation region by forming an N-type region by ion implantation or by supplying a predetermined voltage. As a result, a capacitor including the first polysilicon layer, the thin insulating film, and the channel region is formed. The first polysilicon layer on the field oxide film is regarded as one type of wiring.

On the channel formation region, a second polysilicon layer for forming a gate electrode via a thin gate oxide film is formed. The second polysilicon layer extends on the field insulating film and the first polysilicon layer. Although not particularly limited, word lines and dummy word lines in a memory array described later are formed of a second polysilicon layer.

Source, drain and semiconductor wiring regions are formed on the surface of the active region which is not covered by the field insulating film, the first and second polysilicon layers by a known impurity introduction technique using them as an impurity introduction mask. .

A relatively thick interlayer insulating film is formed on the surface of the semiconductor substrate including the first and second polysilicon layers, and a conductive layer made of aluminum is formed on the interlayer insulating film. . The conductor layer is electrically coupled to the polysilicon layer and the semiconductor region via a contact hole provided in an insulating film thereunder. A bit line in a memory unit described later is formed of a conductor layer extended on the interlayer insulating film, although not particularly limited.

The surface of the semiconductor substrate including on the interlayer insulating film and the conductor layer,
It is covered with a final passivation film such as a silicon nitride film and a phosphor silicate glass film.

The cache memory compares an address tag input from a microprocessor (not shown) with an address in the memory, and outputs a hit or mishit signal to the microprocessor at high speed.

The address signal in the memory is stored in a memory cell coupled to each of the word lines W0 to Wj extending in the horizontal direction. As the memory cell, a dynamic memory cell including an address selection MOSFET Qm and an information storage capacitor Cs as shown in FIG.

The input / output nodes of the memory cell are connected to a pair of complementary bit lines (data lines or digit lines) B0,0 to Bi, i. These complementary bit lines B0,0-Bi, i amplify the storage information from the memory cells coupled to the selected word line and recover the information charges that are about to be destroyed by the read operation ( A refresh unit is provided. This unit circuit U
Although the specific circuit configuration is not shown, the SA includes a pair of CMOS inverter circuits whose inputs and outputs are cross-connected. A P-channel MO constituting a CMOS inverter circuit in the unit circuit consisting of i + 1 units
The operating voltage is applied to the sources of the SFETs via a P-channel MOSFET Q1 which is connected in common and operates as a power switch.
The sources of the channel MOSFETs are supplied with the ground potential of the circuit via N-channel MOSFETs Q2 which are commonly connected and operate as power switches. MOSFETs Q1 and Q2 above
Gates have sense amplifier timing signals ▲ ▼
When the MOSFETs Q1 and Q2 are turned on, the sense amplifier is activated to perform the amplification operation and the refresh operation as described above.

Further, for the above-mentioned read operation of the memory cell, the following precharge circuit is used for each bit line B0,0-Bi, i.
Is provided. Taking the complementary bit lines B0,0 as an example, the precharge circuit supplies a switch MOSFET Q3 for short-circuiting the complementary bit lines B0,0 and a voltage (Vcc / 2) that is 1/2 of the power supply voltage Vcc to each bit line B0,0. Switch MOSFET
It consists of Q4 and Q5. The same switch MOSFETs as described above are applied to the other exemplary bit lines B1,1 and Bi, i.
Is provided. A precharge signal PC is commonly supplied to the gates of these switch MOSFETs Q3 to Q5.

The switch MOSFET Q3 is turned on when a precharge signal PC generated in a non-operating state is supplied to its gate. Thereby, the high level and the low level of the complementary bit lines B0,0 formed by the amplification operation of the sense amplifier SA formed in the previous operation cycle are short-circuited, and the complementary bit lines B0,0 are set to the precharge voltage of about Vcc / 2. And Although not particularly limited, when the cache memory is in a non-operating state for a relatively long time, the precharge level decreases due to a leak current or the like. Therefore, the half precharge voltage Vcc / 2 is supplied by turning on the switch MOSFETs Q4 and Q5. Although a specific circuit of the voltage generating circuit for forming the half precharge voltage Vcc / 2 is not shown, the voltage generating circuit has a relatively small current supply capability to compensate for the leak current and the like. By adopting such a configuration, an increase in power consumption is suppressed.

Depending on the non-operating state of the tag memory, etc.
Before the SFET Q3 etc. are turned on, the sense amplifier SA
Is deactivated. Thereby, the complementary bit line
B0,0 holds a high level and a low level in a high impedance state. When the tag memory is activated, all of the precharge MOSFETs Q3 to Q5 are turned off before the sense amplifier SA is activated. Thereby, the complementary bit lines B0,0 to B
i and i hold the half precharge level in the high impedance state.

In such a half precharge method, since the high level and the low level of the complementary bit lines B0,0 are simply short-circuited, the power consumption is reduced. Also, in the amplification operation of the sense amplifier SA, the complementary bit lines B0,0 change in a common mode such as a high level and a low level around the precharge level, so that the noise level generated by capacitive coupling can be reduced. Becomes

In the sense amplifier, the power switch MOSFETs Q1 and Q2 that activate it are two switch MOSFETs each.
It consists of. For example, a complementary timing pulse ▲ ▼ 1, which activates a sense amplifier in an operation cycle,
SAC1 is supplied to the gate of one of the switch MOSFETs, and complementary timing pulses {2} and SAC2 generated after the timing pulse {circle around (1)} and SAC1 are supplied to the gate of the other switch MOSFET. By doing so, the operation of the sense amplifier is divided into two stages. When the timing pulse ▲ ▼ 1, SAC1 is generated, that is, in the first stage, the minute read voltage applied between the pair of bit lines from the memory cell by the current limiting action of the switch MOSFET having a relatively small conductance is , Without any unwanted level fluctuation. After the difference between the complementary bit line potentials is increased by the amplification operation of the sense amplifier, the timing pulse
2. When SAC2 is generated, that is, when the second stage is entered, the switch MOSF having a relatively large conductance
ET is turned on. The increase operation of the sense amplifier is accelerated by turning on these MOSFETs. Thus, by performing the amplification operation of the sense amplifier in two stages, it is possible to perform high-speed reading of the stored information in the form of minute electric charges while preventing an undesired level change of the complementary bit line.

The complementary bit line B0,0 is coupled to a common bit line CB, ▼, to which a write signal is transmitted via switch MOSFETs Q6 and Q7 shown as an example. Similar switch MOSFETs are provided for the other illustratively shown complementary bit lines B1,1 and Bi, i.

The selection signals Y0 to Yi are supplied to the gates of the pair of MOSFETs Q6 and Q7, etc., corresponding to the respective complementary bit lines B0, 0 to Bi, i. Therefore, an address signal composed of a plurality of bits serially transmitted to the common bit lines CB, CB is written in 1 + i memory cells corresponding to the selected word line in synchronization with the selection signals Y0 to Yi. is there.

Instead of this configuration, each of the complementary bit lines B0,0 to Bi,
A switch MOSFET for transmitting an address signal A0 to Ai supplied to a comparing unit corresponding to i, which will be described later, may be provided to simultaneously write address signals for one word line. In this case, different address signals are supplied to the address signals A0 to Ai depending on the comparison mode and the write mode.

The address comparing section comprises a unit circuit composed of MOSFETs Q8, Q9 whose gates are coupled to the complementary bit lines B0, B0, and MOSFETs Q10, Q11 connected in series with the MOSFETs Q8, Q9. An address signal A0 to be compared is supplied to a gate of the MOSFET Q10, and a gate of the MOSFET Q11 is
The address signal A0 is supplied after being inverted by the inverter circuit N1. Another illustratively shown complementary bit line B1,
1 and Bi, i are also provided with unit circuits composed of similar MOSFETs, and address signals A1 and Ai are supplied correspondingly.

The drains of the MOSFETs Q8, Q9 and the like constituting the unit circuit are commonly connected to a precharge signal line. The precharge signal line is provided with a precharge MOSFET Q12. The gate of this MOSFET Q12 is supplied with a precharge signal ▼▼. As for the potential of the precharge signal line, a signal Hit is formed through the inverter circuits N4 and N5. That is, the precharge signal line is connected to the serial MO
Constructs the effective wired-OR logic of the SFET.

If the address information stored in the selected word line and the address signals A0 to Ai all match, the MO
Since the SFETs Q8, Q9 and Q10, Q11 are cross-connected, no discharge path is formed. If there is a mismatch in one complementary bit line, both the MOSFETs in the series form are turned on to form a discharge path, so that the precharge signal line is pulled to a low level. Therefore, if the signal Hit is at a high level, it means a hit that all address signals match, and if it is at a low level, it means a miss hit that the address signals do not match.

In this embodiment, the address selecting MOSFET as described above is used.
Since the dynamic memory cell including the Qm and the information storage capacitor Cs is used, much higher integration can be achieved as compared with the case where a static memory cell is used. The address comparison circuit uses complementary bit lines as MOSFETs.
, The comparison can be made immediately after the sense amplifier starts to operate, and high-speed operation is achieved.

FIG. 2 is a schematic block diagram for explaining the flow of data in the cache memory.

Signals formed in the comparison circuit in FIG.
Hit is supplied to an AND gate circuit together with a validity bit, and is output as a hit signal to a microprocessor or the like. Further, the hit signal is supplied to the gate of the MOSFET Q15 constituting the output buffer of the data memory, and makes the output buffer substantially in the operating state. That is, the output signal Dout read from the data memory
Is supplied to the gate of the MOSFET Q14 constituting the output buffer, so that the data is output through the output inverter circuit N6 as valid data only when the MOSFET Q15 in series with it is turned on by the hit signal.

Instead of such a configuration, the output buffer may have a three-state output function. That is, the output may be set to a high impedance state in the case of a mishit.

Note that the word lines of the data memory are in one-to-one correspondence with the same addresses as the word lines of the tag memory, and the data at the address of the tag memory is output. The other configuration of such a cache memory is the same as that of the above document or a similar configuration having the same function.

The operational effects obtained from the above embodiment are as follows. That is, (1) By using a dynamic memory cell for the memory section (tag memory, data memory) of the cache memory, an effect of enabling high integration can be obtained.

(2) As an address comparison unit in the tag memory, a MOSFET having a gate coupled to a complementary bit line and a MOSFET receiving an address signal corresponding thereto are connected in series in a crossing manner,
By combining them with a substantial wired-OR logic, an effect that high-speed address comparison can be performed can be obtained.

Although the invention made by the present inventor has been specifically described based on the embodiment, the present invention is not limited to the embodiment, and various changes can be made without departing from the gist of the invention. Needless to say. For example, an address selection circuit for selecting an address of each memory unit and a circuit for inputting / outputting data include a known bipolar transistor and a CMOS.
A Bi-CMOS circuit composed of a combination with a circuit may be used to increase the speed.

The unit circuit USA of the sense amplifier may be composed of a pair of MOSFETs whose gates and drains are cross-connected. In this case, a power switch is connected to the common source line.
A MOSFET is provided. When such a sense amplifier is used, it is necessary to provide an active restore circuit for restoring the potential of a bit line to be set to a high level according to the amplified output to a high level such as the power supply voltage Vcc. The structure of such a sense amplifier or a known dynamic RAM can be used as it is.

The present invention may be built in a microprocessor, for example, in addition to a cache memory formed of a one-chip semiconductor integrated circuit device.

〔The invention's effect〕

The effect obtained by the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, by using dynamic memory cells for the memory section (tag memory, data memory) of the cache memory, high integration can be achieved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of a tag memory and a high-speed comparison circuit in a cache memory according to the present invention. FIG. 2 is a schematic block diagram for explaining a flow of data in the cache memory. Qm: Address selection MOSFET, Cs: Information storage capacitor, USA: Unit circuit (sense amplifier), Q1 to Q15
MOSFET, N1 to N6: Inverter circuit, G: AND gate circuit

Claims (1)

(57) [Claims] 1. A directory memory comprising: a plurality of complementary bit lines; a plurality of word lines intersecting the plurality of complementary bit lines; an address selection MOSFET and an information storage capacitor, respectively; A plurality of dynamic memory cells provided at predetermined intersections of lines and the complementary bit lines; a precharge circuit for setting the plurality of complementary bit lines to a precharge level; and writing to the dynamic memory cells A pair of common bit lines to which a write address signal to be supplied is supplied; and a plurality of complementary bit lines provided between each of the plurality of complementary bit lines and the pair of common bit lines. A plurality of switches M for selectively applying a write address signal for a common bit line to a corresponding complementary bit line An OSFET and a pair of CMOS inverter circuits whose inputs and outputs are cross-connected are connected to the corresponding complementary bit lines, and read from a plurality of dynamic memory cells selected by word selection. A plurality of sense amplifiers for amplifying the received address signals, a first power switch for applying a power supply voltage to the plurality of sense amplifiers, and a second power switch for applying a ground potential to the plurality of sense amplifiers. The first power switch and the second power switch are each a first MOSFET that is turned on by a first timing pulse for activating the sense amplifier, and a second timing pulse that is generated later than the first timing pulse. A switch circuit comprising a second MOSFET turned on by the A plurality of unit circuits for comparing read address signals read from a plurality of dynamic memory cells each selected by a word line selection and amplified by the sense amplifier with an address signal to be compared; A signal line for obtaining a wired-OR logic of the output signals of the plurality of unit circuits.