JP2611162B2 - Method of forming ohmic electrode - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for forming an ohmic electrode of a semiconductor device, for example, a field effect transistor.

(Prior Art) Conventionally, research and development on ohmic electrodes of semiconductor devices have been promoted and reports have been made (for example, Document I: “Solid-State Electronics”, 18 , 19
75), pp. 541-550 and Reference II: "Electronics Letter
s ", 15 , (24), (1979), pp. 800-801).

As a method of forming an ohmic electrode on a semiconductor layer,
There are an alloying method and a non-alloying (non-alloy) method.

The alloying method is a method in which an ohmic metal electrode pattern is formed on a semiconductor layer and then alloyed with a semiconductor at a high temperature.For example, AuGe is deposited as an ohmic metal on a GaAs semiconductor layer to form an electrode pattern. And then 400
An ohmic electrode is formed by alloying GaAs and AuGe at a high temperature of about ° C.

On the other hand, the non-alloy method is, for example, ion-implanting Si into a GaAs semiconductor layer at a high concentration, and depositing Ti, W or other electrode material on the resulting highly-doped semiconductor layer to form an electrode pattern. The depletion layer is made extremely thin by the method of forming a barrier at the semiconductor-metal interface.
This is a method that utilizes the fact that the carrier passes through the tunnel effect.

(Problems to be solved by the invention) However, in the alloying method, the alloying temperature of about 400 ° C. is compared with the annealing temperature of usually 700 to 800 ° C. for activation after ion implantation is performed on the semiconductor layer. Since the temperature is relatively low, high-temperature processing such as annealing cannot be performed after the alloying processing. Therefore, such high-temperature processing has been avoided in manufacturing a semiconductor device. In addition, in the alloying method, the resistance increases when the temperature deviates from a desired alloying temperature mainly due to a difference in reaction between the semiconductor and the metal for an electrode due to a slight difference in the alloying temperature. Therefore, there is a disadvantage that the reproducibility of the ohmic electrode formation is poor.

In the non-alloy method, since a high-concentration semiconductor layer is formed by ion implantation, there is a disadvantage that the surface state of the semiconductor layer is poor and the resistance value is large. Furthermore, since an electrode is formed on the surface of the semiconductor layer by vapor deposition, an oxide film is formed on the surface of the semiconductor layer, and a barrier is generated due to this, so that the resistance is increased. Since it is difficult to control the magnitude of this resistance, there is a disadvantage that the reproducibility of the ohmic electrode formation is poor.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming an ohmic electrode having excellent heat resistance regardless of the surface condition of an underlayer to be formed with good reproducibility in view of the above-mentioned drawbacks of the conventional method for forming an ohmic electrode. Is to do.

(Means for Solving the Problems) In order to achieve this object, according to the present invention, a step of forming an electrode pattern made of tungsten or an alloy mainly containing tungsten on a semiconductor substrate having an active layer. And growing a semiconductor layer at least partially in contact with the electrode pattern on the active layer, wherein the doping concentration of the semiconductor layer is a concentration at which the contact with the electrode pattern becomes an ohmic contact. It is characterized by doing.

(Operation) FIG. 1 is a sectional view schematically showing a part of a semiconductor device for explaining the principle of the present invention. Note that hatching indicating a cross section is omitted.

According to the present invention, an electrode pattern 2 is formed on a base layer 1 made of a semiconductor. This electrode pattern 2 is 700-8
It is formed of a metal having a high melting point that does not react with the underlayer 1 even at a high temperature of 00 ° C. or higher. This makes it possible to perform high-temperature treatment such as annealing after the formation of the electrode pattern 2. For example, after creating a first group of FETs on a semiconductor substrate, when creating a second group of FETs, even if annealing is performed to form the active layer of this second group of FETs, it is created first. The first group of FETs does not deteriorate.

According to the present invention, after the formation of the electrode pattern 2, the semiconductor layer 3 having a high doping concentration is grown on the base layer 1 so as to be at least partially in contact with the electrode pattern 2. By setting the semiconductor layer 3 to a high doping concentration, the electrode pattern 2 and the semiconductor layer 3 form an ohmic contact. Unlike conventional, electrode pattern 2
Since there is no need to make ohmic contact with the underlayer 1, the contact resistance can be reduced.

Further, according to the present invention, no heat treatment for alloying is required, so that the problem of reproducibility associated with alloying does not occur.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings. In the drawings, the same components are denoted by the same reference numerals. Further, these drawings are only schematically shown to the extent that the configuration of the present invention can be understood.

2 (A) to 2 (D) are process diagrams for explaining one embodiment of the present invention. Here, as an example, a method of forming an ohmic electrode connected to the source / drain of a field effect transistor (FET) will be described.

In this embodiment, a semi-insulating GaAs substrate is used as the underlayer 1.
After the selective ion implantation of, for example, Si is performed in the-part of 1a, the ion implantation region is activated to form an active layer 1b. In this case, the depth of ion implantation and other necessary conditions can be set arbitrarily to the depth and conditions corresponding to the target semiconductor element (FIG. 2A).

Next, a refractory metal layer which does not react with the underlying GaAs even at a high temperature of, for example, about 700 to 800 ° C. or higher is deposited on the underlying layer 1 by vapor deposition or sputtering, and then patterned to form the active layer 1b. An electrode pattern 2 extending over a part and a part of the substrate la is formed (FIG. 2B).
In this case, tungsten (W) is used as the refractory metal,
Alternatively, an alloy containing tungsten as a main component, for example, W-Al,
W-Si and other metals.

Next, a mask 4 used for selectively growing a semiconductor layer for forming an ohmic contact with the electrode pattern 2 is formed (FIG. 2C). The material of the mask 4 is not limited as long as it can be selectively grown. For example, an insulating film such as an oxide film such as SiO ₂ or a nitride film can be used. In this embodiment, the active layer 1b is exposed from the window 5 of the mask 4 and the active layer is exposed to the substrate from the portion of the metal pattern 2 provided on the substrate 1b.
This mask 4 is exposed so that a portion extending on 1a is exposed.
To form

Next, a semiconductor layer 3 having a high doping concentration is selectively grown mainly on the exposed active layer 1b and the electrode pattern 2, and an ohmic contact is formed between the electrode pattern 2 and the semiconductor layer 3 (second). (D). In this case, the material of the semiconductor layer 3 is GaAs, which is the same as the material of the underlayer 1, and for example, Si, Se, Te, S, or any other suitable ion is used as doping ions, and the doping concentration is, for example, about 10 ¹⁹ / cm ^3. Is selected. The semiconductor layer 3 having such a high doping concentration forms an ohmic contact with the electrode pattern 2. In addition, since the semiconductor layer 3 and the active layer 1b have the same conductivity type, an ohmic contact can be obtained between them.

The growth method of the semiconductor layer 3 does not matter, but as an example,
MOCVD can be used. As described above, the FET
An ohmic electrode connected to the source / drain is formed.

In the first embodiment, when the semiconductor layer 3 is grown by the MOCVD method, the electrode pattern 2 is exposed to a hydrogen atmosphere at a high temperature in the reaction tube of the growth apparatus.
The oxide film on the surface of is removed. In this case, it can be expected that the surface state for forming the ohmic contact becomes better.

After forming the ohmic electrode as described above, the FET is completed through desired steps. When the completed FET is operated, the carrier flow is as follows. First, carriers flowing through the active layer 1 b flow to the semiconductor layer 3. Then, the carrier passes through a barrier (barrier) at the semiconductor-metal interface constituted by the semiconductor layer 3 and the electrode pattern 2 by a tunnel effect, and carriers flow to the electrode pattern 2.

The present invention is not limited only to the embodiments described above. For example, in the above-described embodiment, a part of the electrode pattern 2 is provided on the active layer 1b. However, this electrode pattern 2 is provided on the substrate 1a outside the region of the active layer 1b, and these electrodes are passed through the semiconductor layer 3. The pattern 2 may be configured to be electrically connected to the active layer 1b.

Further, in the above-described embodiment, the substrate on which the active layer 1b is formed as the underlayer 1 is described. However, the present invention is not limited to this, and the present invention has been described for a GaAs semiconductor device. However, the present invention is preferably applied to, for example, InP-based or Si-based semiconductor devices.

(Effects of the Invention) As is clear from the above description, according to the present invention, since a metal that is stable even at a high temperature is used for the ohmic electrode, high-temperature treatment such as annealing can be performed after the electrode pattern is formed. There is an advantage. For example, after creating a first group of FETs on a semiconductor substrate, when creating a second group of FETs, even if annealing is performed to form the active layer of this second group of FETs, it is created first. The first group of FETs does not deteriorate.

Further, according to the method of the present invention, since the alloying step is not included, there is an advantage that the problem of reproducibility associated with the conventional alloying method can be solved.

Further, unlike the conventional non-alloy method, a semiconductor layer having a high doping concentration is grown and brought into contact with the electrode pattern, so that there is an advantage that the contact resistance can be reduced.

Because of these effects, the present invention is suitable for application to the formation of ohmic electrodes of various semiconductor devices.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view schematically showing a part of a semiconductor device for explaining the principle of a method for forming an ohmic electrode according to the present invention, and FIGS. 2A to 2D illustrate an embodiment of the present invention. FIG. DESCRIPTION OF SYMBOLS 1 ... Underlayer, 1a ... Substrate 1b ... Active layer 2 ... Electrode pattern (or ohmic electrode) 3 ... High doping concentration semiconductor layer 4 ... Mask, 5 ... Mask window.

Claims (1)

(57) [Claims] A step of forming an electrode pattern made of tungsten or an alloy containing tungsten as a main component on a semiconductor substrate having an active layer; and forming a semiconductor on the active layer at least partially in contact with the electrode pattern. Growing a layer, wherein the doping concentration of the semiconductor layer is a concentration at which contact with the electrode pattern becomes ohmic contact.