JP2610689B2 - Semiconductor integrated circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit having a BiCMOS structure in which an output stage of an inverter circuit is constituted by a bipolar transistor and an input stage is constituted by a CMOSFET. Circuit.

(Prior Art) In recent years, a BiCMOS semiconductor integrated circuit having both the high speed of a bipolar transistor and the low power consumption of a CMOSFET has been widely used.

 FIG. 2 shows a conventional BiCMOS inverter circuit.

In this inverter circuit, the output stage is composed of two npn-type bipolar transistors 5 and 6, and the input stage is provided with two CMOSFETs 21 and 23 for supplying base current to these bipolar transistors 5 and 6, respectively. It is provided. The input stage is provided with two MOSFETs 22 and 24, respectively, for extracting accumulated charges from the bases of the bipolar transistors 5 and 6.

When a high level is input to the input terminal IN, p
The channel MOSFET 21 is turned off and the n-channel MOS
The FET 22 turns on, and the bipolar transistor 5 turns off. Further, the n-channel MOSFET 23 is turned on, the n-channel MOSFET 24 is turned off, and the bipolar transistor 6 is turned on, so that the output terminal OUT is at a low level.

Next, when this input terminal IN changes to LOW level, the MOS
The FET 21 turns on, the MOSFET 22 turns off, and the bipolar transistor 5 turns on. Further, since the MOSFET 23 is turned off and the bipolar transistor 5 is turned on and the MOSFET 24 is also turned on, the bipolar transistor 6 is turned off, so that the output terminal OUT changes to a high level.

In this case, the HIGH level of the output terminal OUT is set to the power supply VC.
The value is obtained by subtracting the base-emitter voltage VBE of the bipolar transistor 5 from C, and the LOW level is the base-emitter voltage VBE of the bipolar transistor 6.

FIG. 3 shows another conventional example of a BiCMOS inverter circuit.

This inverter circuit is provided with a MOSFET 24 provided for extracting the accumulated charge at the base of the bipolar transistor 6.
Is different from the conventional example shown in FIG. 2 in that the gate terminal is connected to the base terminal of the bipolar transistor 5.

In the conventional example shown in FIG. 2, the MOSFET 24 is turned on by the potential of the emitter terminal where the bipolar transistor 5 is turned on, but in the present conventional example, the MOSFET 24 is turned on by the base potential of the bipolar transistor 5. And the same operation as above is performed.

(Problems to be Solved by the Invention) However, in the conventional example shown in FIG. 2, the MOSFET 24 is turned on after the bipolar transistor 5 is turned on, whereby the stored charge of the base is extracted and the bipolar transistor 6 is turned on. Is turned off, a large current flows from the electrode VCC to the ground power supply between the time when the bipolar transistor 5 is turned on and the time when the bipolar transistor 6 is turned off.

Further, in the conventional example shown in FIG. 3, the MOSFET 24 is turned on by the base potential of the bipolar transistor 5, but this base potential is
Is the value obtained by adding the base-emitter voltage VBE to the emitter potential. Then, the emitter potential of the bipolar transistor 5 is set so that the bipolar transistor 6 is completely turned off.
Until the potential becomes low, the MOSFET 24 cannot sufficiently extract the charge stored in the base of the bipolar transistor 6. Therefore, also in this case, after the bipolar transistor 5 is turned on, the bipolar transistor 6 is turned off.
A large current flows from the power supply Vcc to the ground power supply until is completely turned off.

For this reason, in the conventional semiconductor integrated circuits described above, the bipolar transistor 5 in the output stage,
6 has a problem that a large current flows and power consumption increases.

The present invention has been made in view of the above circumstances, and a semiconductor integrated circuit in which useless current does not flow every time an input changes by reliably turning off the other bipolar transistor before turning on one bipolar transistor in the output stage. The purpose is to provide.

(Means for Solving the Problems) The semiconductor integrated circuit according to the present invention includes a first FET which is turned off when a gate input is at a high level and a second FET which is turned on when a gate input is at a high level. The first FET is connected to the power supply side, the second FET is connected to the ground side, these FETs are inserted between the power supply and the ground, and the gates of these FETs are connected to the input terminal together. A first input circuit, a third FET that is turned on when the gate input is at a high level, and a fourth FET that is turned off when the gate input is at a high level, connected in series at each output side, 3 F
With ET on the power supply side and the fourth FET on the ground side, these FETs
Is inserted between the power supply and the ground, and the second input stage circuit in which the gates of these FETs are connected together to the input terminal, one bipolar transistor having a base input between each FET of the first input stage circuit, and The other bipolar transistors having the base input between the FETs of the second input stage circuit are directly connected at their respective output sides, these bipolar transistors are inserted between the power supply and the ground, and the output between these bipolar transistors is output. And an output stage connected to the terminal.
The driving capability of the first FET is set higher than the driving capability of the first FET, and the driving capability of the second FET is set higher than the driving capability of the third FET, thereby achieving the above object. .

(Operation) With the above configuration, each FET of each input stage circuit operates according to the input level of the same input terminal. Also, the FET on the base current extraction side in each input stage circuit
Are set such that the driving capability is higher than that of the FET on the base current supply side in the other input stage circuit.

Therefore, the base current supply side FET in one of the input stage circuits is turned on in response to a change in the input, and the base current extraction in the other input stage circuit is faster than turning on the bipolar transistor in the output stage. Side FET is O
When it becomes N, the base current of the bipolar transistor in the output stage can be extracted and turned off.

For this reason, the two bipolar transistors in the output stage do not turn on at the same time even when the input changes, so that no useless current flows.

(Examples) The present invention will be described below with reference to examples.

FIG. 1 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to one embodiment of the present invention. This embodiment is an inverter circuit using BiCMOS.

In this inverter circuit, the output stage circuit 7 forms a totem pole output by two npn-type bipolar transistors 5 and 6. Therefore, one bipolar transistor 5 has a collector terminal connected to the power supply VCC, and an emitter terminal connected to the collector terminal of the other bipolar transistor 6 together with the output terminal OUT. The emitter terminal of the other bipolar transistor 6 is
Connected to ground power.

The base terminals of these bipolar transistors 5 and 6 are connected to two input stage circuits 8 and 9 each composed of a p-channel MOSFET 1 and an n-channel MOSFET 2 and an n-channel MOSFET 3 and a p-channel MOSFET 4, respectively.
It is connected to the.

That is, the base current is supplied to the bipolar transistor 5 on the power supply VCC side in the output stage circuit 7 by the p-channel MOSFET 1 in the one input stage circuit 8. In addition, this bipolar transistor 5
Is the n-channel MOSFET 2 in the same input stage circuit 8
Thereby, a base current (accumulated charge of the base) is extracted.

The ground-side bipolar transistor 6 in the output stage circuit 7 is supplied with a base current by the n-channel MOSFET 3 in the other input stage circuit 9. The base current of the bipolar transistor 6 is extracted by the p-channel MOSFET 4 in the same input stage circuit 9.

Each of the MOSFETs 1 to in the input stage circuits 8 and 9
4 are connected to the same input terminal IN.

Further, the MOSFET 2 in one input stage circuit 8 is set so that the driving capability is higher than that of the MOSFET 3 in the other input stage circuit 9,
The SFET 4 has a driving capability of the MOSFE in one input stage circuit 8.
It is set to be higher than T1. Note that such setting of the driving capability can be achieved by, for example, changing the size of the element region in the semiconductor device.

 The operation of the inverter circuit having the above configuration will be described.

When a high level is input to the input terminal IN, the MOSFET 1 in the input stage circuit 8 is turned off, the MOSFET 2 is turned on, and the bipolar transistor 5 in the output stage circuit 7 is turned off. Further, the MOSFET 3 in the input stage circuit 9 is turned on, the MOSFET 4 is turned off, and the bipolar transistor 6 in the output stage circuit 7 is turned on, so that the output terminal OUT is at a low level.

Next, when this input terminal IN changes to the LOW level, the MOSFET 1 in the input stage circuit 8 is turned on and the MOSFET 2 is turned off.
And the bipolar transistor 5 of the output stage circuit 7
Turns on. When the MOSFET 3 in the input stage circuit 9 is turned off and the MOSFET 4 is turned on, the bipolar transistor 6 in the output stage circuit 7 is turned off.
UT also changes to HIGH level.

At this time, the MOSFET 4 in the input stage circuit 9 operates at the same input level of the input terminal IN as the MOSFET 1 of the same p-channel in the input stage circuit 8, and has a higher driving capability. Therefore, this MOSFET4
Can quickly extract the base current of the bipolar transistor 6 before the bipolar transistor 5 is turned on, and can surely turn off the bipolar transistor 6.

The MOSFET 2 in the input circuit 8 is also connected to the input stage circuit 9
The same input terminal I as the same n-channel MOSFET 3
It operates according to the input level of N, and its driving capability is set higher than this. Therefore, even when the input terminal IN further changes to the HIGH level, the MOSFET 2 can quickly draw the base current of the bipolar transistor 5 before the bipolar transistor 6 is turned on, and can surely turn off the bipolar transistor 5. .

As a result, in the inverter circuit of the present embodiment, even when the input changes, the two bipolar transistors 5 and 6 of the output stage circuit 7 do not turn on at the same time. Is no longer flowing.

(Effects of the Invention) As is clear from the above description, according to the semiconductor integrated circuit of the present invention, the two bipolar transistors of the output stage drive circuit do not turn on simultaneously when the input changes.

As a result, the present invention has an effect that the power consumption of the semiconductor integrated circuit can be reduced because a useless current does not flow to the output stage when the input changes.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to one embodiment of the present invention, FIG. 2 is a circuit diagram showing a configuration of a conventional semiconductor integrated circuit, and FIG. FIG. 3 is a circuit diagram illustrating a configuration. 1-4, MOSFETs, 5, 6, bipolar transistors, 7, output stage circuits, 8, 9, input stage circuits.

Claims (1)

(57) [Claims] A first FET which is turned off when a gate input is at a high level and a second FET which is turned on when a gate input is at a high level are connected in series at respective output sides, and a first FET is provided. A first input stage circuit in which is connected to the power supply side, the second FET is connected to the ground side, these FETs are inserted between the power supply and the ground, and the gates of these FETs are connected together to the input terminal; The third FET that is turned on when high level
And the fourth which is turned off when the gate input is at a high level
FETs are connected in series at the respective output sides, the third FET is connected to the power supply side, the fourth FET is connected to the ground side, these FETs are inserted between the power supply and ground, and the gates of these FETs are connected to the input terminals. A second input stage circuit connected to both terminals, one bipolar transistor having a base input between each FET of the first input stage circuit and each FET of the second input stage circuit
The other bipolar transistor having a base input between them is connected in series at each output side, these bipolar transistors are inserted between the power supply and the ground, and an output stage connected between these bipolar transistors to the output terminal is connected. A semiconductor integrated circuit comprising: a driving capability of a fourth FET higher than a driving capability of a first FET; and a driving capability of a second FET higher than a driving capability of a third FET.