JP2609714B2 - Asynchronous information line multiplexer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to an asynchronous information concentrator / multiplexer that multiplexes and outputs information asynchronously transmitted from a plurality of input highways by solid-state cells and does not require a centralized contention control circuit. Multiplexing circuits are connected to the output terminals of each input highway, and the multiplexing circuits are connected to the multiplexing highway and the control signal. If there is a cell in only one of the multiplexing highway input to the multiplexing circuit and the input highway in each multiplexing circuit, the cell is sent out to the multiplexing highway on the output side, and the multiplexing is performed. When there are cells on the multiplex highway and the input highway input to the circuit, based on the control signal sent from the previous multiplex circuit,
It is configured to control which of the multiplex highway cell and the input highway cell is transmitted, and to transmit the cell to the output multiplex highway.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an asynchronous information line multiplexer that multiplexes and outputs information asynchronously transmitted from a plurality of input highways by solid-state long cells.

As a technology for realizing broadband ISDN, ATM (Asynchronou Transfer Mode) based on cell multiplex transmission has recently attracted attention as a highly flexible transmission system capable of accommodating various types of information in a unified manner.

However, when multiplexing cells from multiple input highways to the output highway, each cell arrives asynchronously,
Cell contention on the output highway occurs. In order to avoid this, it is necessary to provide a waiting buffer for each input highway. However, this causes an information delay due to the buffer and an information error due to the buffer overflow. Therefore, if the capacity of the buffer is increased, the probability of an information error decreases, but on the contrary, the delay may increase. In order to solve such a problem, it is required to reduce the average residence time of cells in the buffer.

[Prior Art] When cell contention control is performed by a polling method, a line termination circuit (LU) and a multiplexing node (MN) are wired in a star shape as shown in FIG. If this happens, a response delay of polling will occur, which is not practical.

Therefore, conventionally, as shown in FIG. 8, for example, as shown in FIG. 8, a multiplexing unit (MU) for performing small-scale multiplexing is configured in a hierarchical manner between the MN and the LU, and an overall tree-like configuration is formed. The one that is taken is known (IEICE Information Network Research Group IN88-36). Here, each MU is provided with a plurality of buffers, and transmission delays in the middle are absorbed by the buffers in each MU. Then, since there is a problem that the cell delay of the call of the high arrival rate increases due to the call of the low arrival rate, the frequency of reading out the buffer is controlled according to the call arrival rate, and the residence time of the cell in the buffer is shortened. I was trying.

[Problems to be Solved by the Invention] However, the above-described hierarchical configuration requires a plurality of complicated contention control circuits and easily adds a subscriber line with an increase in the number of hierarchies. There were drawbacks that could not be done. The root cause is that the buffer group must be divided and controlled in order to secure the processing speed for performing intensive competition control.

In addition to the polling method, there are an arbiter method, a token method, and the like, and these methods also require intensive and complicated control and management.

SUMMARY OF THE INVENTION An object of the present invention is to provide an asynchronous information line multiplexing apparatus which solves the conventional disadvantages described above, does not require a centralized contention control circuit, and can easily cope with an increase in the number of subscribers. I do.

[Means for Solving the Problems] To achieve the above object, as shown in FIG. 1, an asynchronous information concentrator / multiplexer of the present invention comprises a plurality of asynchronous information concentrators for transmitting information asynchronously by fixed-length cells. An input highway 1 and a plurality of multiplexing circuits 2 connected to the output terminals of the input highways 1 for multiplexing the input asynchronous information, and multiplexing the multiplexing circuits 2 by cascade connection; Multiplexed highway 3 for transmitting the multiplexed information, and a control signal line 4 provided in parallel with the multiplexed highway 3 for transmitting a control signal used for multiplexing control in the multiplexing circuit 2.
And one output highway 5 for transmitting the multiplexed information from the last cascaded multiplex circuit 2a. In each of the multiplex circuits 2, the multiplex highway 3 to be input to the multiplex circuit 2 is provided. When there is a cell on only one of the input highways 1, the cell is sent to the multiplexing highway 3 on the output side, and when there are cells on both the multiplexing highway 3 and the input highway 1 input to the multiplexing circuit 2, the previous cell is output. The multiplexing highway 3 on the output side is controlled based on the control signal transmitted from the multiplexing circuit 2 of the multiplexing highway 3 via the control signal line 4 to determine which of the cell of the multiplexing highway 3 and the cell of the input highway 1 is transmitted. Sent to
At the same time, the control signal used in the multiplexing circuit 2 on the output side is output to the control signal line 4 on the output side.

[Operation] A multiplexing circuit 2 is provided for each output terminal of each input highway 1, and competition control at the time of multiplexing is individually performed by each of these multiplexing circuits 2.

The control is performed in each multiplexing circuit 2 by multiplexing highway 3 and input highway 1 input to the multiplexing circuit 2.
If there is a cell on only one side, the cell is sent to the multiplexing highway 3 on the output side. That is, cells from the input highway 1 are sent out to the multiplexed highway 3 as soon as the multiplexed highway 3 is available. When there are cells on both the multiplexing highway 3 and the input highway 1 input to the multiplexing circuit 2, the cells are sent to the multiplexing highway 3 on the output side based on the control signal transmitted by the control signal line 4. Cell order is controlled.

Example An example will be described with reference to the drawings.

The overall configuration of the embodiment is as shown in FIG. 1 showing the configuration of the present invention. Information is asynchronously transmitted to the input highway 1 by fixed-length cells. A multiplexing circuit 2 for multiplexing and controlling input asynchronous information is connected to each output terminal of the plurality of input highways 1.

A multiplexing highway 3 for transmitting the multiplexed information is cascaded with the multiplexing circuit 2.
A control signal line 4 for transmitting a control signal composed of a pulse of “1” or “0” for controlling the multiplexing operation in the multiplex highway 3. The control signal of "1" or "0" is synchronized with the cell of the multiplex highway 3, and in this embodiment, one pulse of "1" has a length of one cell. Then, one output highway 5 for sending out the multiplexed information is connected to the last multiplexing circuit 2a connected in cascade.

In such a configuration, assuming that the number of input highways 1 is n, the transmission speed thereof is m (b / s), and the transmission speed of the output highway 5 is k, m · n ≧ k to obtain a concentrating function.
Is configured to be.

FIG. 2 shows an example of the internal configuration of each multiplexing circuit 2. In the present embodiment, the first and second first-in first-out registers (FI
FO) 21 and 22 are used. The write control units of the FIFOs 21 and 22 are not shown.

The multiplexing highway 3a and the control signal line 4a input to the multiplexing circuit 2 are connected to the input terminals of a first FIFO (M-FIFO) 21, and the input highway 1 is connected to a second FIFO (I-FIFO) 22. Connected to input terminal. Further, a control circuit 23 for controlling output from each of the FIFOs 21 and 22 is provided. The control circuit 23 can be configured by a CPU, a gate circuit, or the like.

The control circuits 23 and 25 determine whether or not there is information in each of the FIFOs 21 and 22.
Information signal lines (MF, IF) constantly transmitted to 26 and 27 are control lines (M-REN, I-REN) for transmitting a readable signal from the control circuit 23 to each of the FIFOs 21 and 22. Reference numeral 28 denotes an input line (CT-F) for inputting a control signal sent from the control signal line 4a to the multiplexing circuit 2 through the first FIFO 21 to the control circuit 23.

Two selectors 29 and 30 are provided, and an output line passing from the multiplexing highway 3a on the input side through the first FIFO 21 and an output line passing from the input highway 1 through the second FIFO 22 are the first selector. The multiplexing highway 3b on the output side is connected to the input terminal of the selector 29 and the output terminal of the selector 29.

The input terminal of the second selector 30 has a control signal line on the input side.
An output line from 4a through the first FIFO 21 is connected to a signal line that always outputs “1”, and an output terminal of the selector 30 is connected to an output-side control signal line 4b. And
A control circuit 2 is connected to each of the selection signal input terminals of the two selectors 29 and 30.
The control signal from 3 is input to control the operations of the selectors 29 and 30.

FIG. 3 is a time chart illustrating the multiplexing control performed in the apparatus of the embodiment.

First, when there is a cell A on the multiplexed highway 3a on the input side and no cell on the input highway 1, the cell A on the multiplexed highway 3a on the input side is sent to the multiplexed highway 3b on the output side as it is.

Conversely, when the input highway 1 has a cell N and the input side multiplexed highway 3a has no cell, the input highway 1 cell N is sent to the output side multiplexed highway 3b. At the same time, the control signal 101 of “1” is output to the control signal line 4b on the output side.

When there is a cell Z in the multiplex highway 3a on the input side and a cell M in the input highway 1, if the input control signal is "0", the cell Z of the multiplex highway 3a on the input side
However, it is sent as it is to the multiplexing highway 3b on the output side. Then, the cell M waits in the FIFO 22 in the multiplexing circuit 2.

Then, when the control signal 102 of "1" is input, the cell M of the input highway 1 is sent to the multiplexing highway 3b on the output side between the "1" and the next "1". In this embodiment, it is sent out next to the cell C sent from the multiplexing highway 3a on the input side together with the control information 102 of the first "1". At the same time, the input control signal of “1” is canceled and becomes “0”, and the control information 103 is sent together with the multiplexed cell M from the input highway 1.
Becomes "1" and is sent to the multiplexing circuit 2 on the output side.

In this way, in the present embodiment, the cells from each input highway 1 are not multiplexed once between "1" and "1" of the information signal, so that the buffer stays in the low arrival call due to the high arrival call. It is possible to make the transmission acquisition probabilities of the input cells uniform without increasing the time.

In addition, as shown in FIG.
Subsequent to 2, when there is a control signal 104 of the next "1" and a cell D of the input side multiplexing highway 3a, they are delayed by one cell, and the control signal line 4b and the output side multiplexing highway 3b are delayed.
Sent to.

FIG. 5 is a multiplexing control flow for performing the above operation.
s indicates a step.

In s1, the input highway 1 and the multiplexed highway on the input side
It is read whether or not there is a cell in each of the cells 3a, and in s2, it is first determined whether or not there is a cell in the input highway 1. Then, if there is no cell on the input highway 1, in s3, the cell on the input side multiplex highway 3a is sent out to the output side multiplex highway 3b as it is, and the process returns to s1.

When there is a cell in the input highway 1 in s2, the presence or absence of a cell in the input side multiplexing highway 3a is determined in s4.
If there is no cell on the input side multiplexed highway 3a, the cell of the input highway 1 is sent to the output side multiplexed highway 3b at s5, and the control signal synchronized with the cell is set to "1" at s6 and output. Output to the control information line 4b on the
Return to

In s4, when there is a cell in the multiplexed highway 3a on the input side, the control signal is read out in s7, and it is determined whether the control signal is "1" or "0" in s8. When the control signal is "0", the cell from the input highway 1 is made to wait in the second FIFO 22 in s9, and the process proceeds to s3.

When the control signal is "1" in s8, the control signal is set to "0" in s10, and in s11, the multiplexed highway 3 on the input side is set.
Sending out the information signal from the cell of a and the input side is controlled by the first FIF
Wait at O21. However, the cell of the input side multiplexed highway 3a sent together with the control signal "1" is directly sent to the output side multiplexed highway 3b, and then s5
Proceed to.

Note that the operation control of the above embodiment can be performed by a gate circuit. FIG. 6 shows the theoretical formula. The M-RE
The N and I-REN control lines operate at a timing in units of cell length, and when these information lines are enabled, the corresponding FI
FO is read.

[Effects of the Invention] According to the asynchronous information line multiplexer of the present invention, multiplexing circuits are connected to the output terminals of the input highways, respectively, and multiplexing control is performed there. The number of input highways can be freely increased without requiring a circuit. That is, the increase in the number of subscribers can be easily dealt with by cascading the multiplexing circuits. Moreover, according to the present invention, since the configuration in which the multiplexed highway and the control signal line are arranged in parallel is adopted, the speed can be increased.
As a result, the degree of multiplexing to the output highway can be increased, so that a large grouping effect can be expected, and the usage efficiency of the highway can be increased.

In addition, the control signal can be used to equalize the transmission acquisition efficiency of the cells of each input highway, so that the average buffer retention time of each cell can be minimized to minimize the average delay time and the buffer amount. Can be achieved.

[Brief description of the drawings]

1 is a block diagram of the present invention, FIG. 2 is a block diagram of a multiplexing circuit of the embodiment, FIGS. 3 and 4 are time charts showing the operation of the embodiment, and FIG. 5 is a multiplexing circuit of the embodiment. FIG. 6 is a logical diagram of control lines in the embodiment, and FIGS. 7 and 8 are block diagrams of a conventional multiplexing system. In the figure, 1 ... Input highway, 2 ... Multiplexing circuit, 3 ... Multiplexing highway, 4 ... Control signal line, 5 ... Output highway.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yuji Kato 1015 Uedanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Co., Ltd. 56) References JP-A-58-188291 (JP, A) JP-A-61-60197 (JP, A) JP-A-63-74339 (JP, A)

Claims (1)

(57) [Claims] 1. A plurality of input highways (1) for asynchronously transmitting information by fixed-length cells and output terminals of each of the input highways (1), respectively, for multiplexing input asynchronous information. A plurality of multiplexing circuits (2); a multiplexing highway (3) for cascading the multiplexing circuits (2) to transmit multiplexed information; A multiplexed signal is transmitted from a control signal line (4) for transmitting a control signal used for multiplexing control in the multiplexing circuit (2) and the last multiplexed circuit (2a) connected in cascade. One output highway (5) is provided. In each of the multiplexing circuits (2), there is a cell in only one of the multiplexing highway (3) and the input highway (1) input to the multiplexing circuit (2). Sometimes output that cell Multiplexing highway (3)
When there are cells on both the multiplexing highway (3) and the input highway (1) input to the multiplexing circuit (2), the cells are transmitted from the previous multiplexing circuit (2) via the control signal line (4). Based on the control signal that has been sent, it is controlled which of the cell of the multiplexed highway (3) and the cell of the input highway (1) is to be transmitted to the multiplexed highway (3) on the output side, and at the same time, the output Side multiplexing circuit (2)
The asynchronous information concentrator / multiplexer characterized in that the control signal used in is output to the control signal line (4) on the output side.