JP2606442B2 - Test jig for semiconductor equipment - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a jig and a tool used for an electrical characteristic inspection (hereinafter, referred to as a test) after sealing in a semiconductor device.

[Conventional technology]

Conventional test and burn-in methods
A description will be given with reference to FIGS. 10 to 13 using QFPIC (hereinafter referred to as IC) as an example.

FIG. 10 is a perspective view of an assembled conventional IC, in which (1) is an IC, (11) is a sealing resin, (12) is an external electrode, and (13) is a direction display. FIG. 11 is a perspective view showing a tray of a first jig for arranging conventional ICs.
(2) is a tray, (21) is a pocket for each IC (1), and a lot of trays (2) are sent to the test step in a lot configuration.

FIG. 12 is an exploded perspective view showing a part of the test apparatus. In FIG. 12, (3) shows conduction between an external electrode (12) of the IC and a tester (not shown) having a voltage, a current source measurement, and a judgment function. The test socket of the second tool to obtain, (31)
The pocket where the sealing resin part (11) of the IC (1) fits, (3
2) is a pedestal in the pocket that has a cushion function, (3
Reference numeral 3) denotes an electrode 1 in contact with the external electrode (12), (4) denotes a test head of a part of the tester, and (5) denotes a pickup portion for handling the IC (1). FIG. 13 is a perspective view of a burn-in board used for burn-in, in which (6) is a burn-in board of a third jig, (61) is a board main body having a printed wiring electric circuit, (62)
Is a heat-resistant burn-in socket having an electrode for setting the IC (1), (63) is a socket (62) and a substrate body (61)
A set screw (64) is a guide section for mounting the burn-in board (6) in a board storage section of a burn-in device (not shown), and (65) is an extraction electrode for receiving a signal from an electrical connector of the burn-in apparatus.

 Next, the operation will be described.

The IC (1) that has completed the assembling process is put into each pocket (21) of the tray (2), is made up of lots of a plurality of trays (2) for each type, and is sent to a test process before burn-in. The tray (2) having a lot configuration that has come to the test process is set on a handler loader portion of a test device (not shown).

The test apparatus takes out one tray (2) from the set trays (2). From this state, the pickup portion (5) moves right above one pocket (21) of the tray (2) from which it has been taken out, and further descends to come into close contact with the sealing resin (11) of the IC (1). Then, while adsorbing with the vacuum jet
The pick-up part (5) with the IC (1) lifted moves directly above the socket (3) attached to the test head (4). Then, it descends and the sealing resin portion of IC (1) (1
The pedestal (32) of the socket (3) is pushed down and stored in the pocket (31) in 1), and the external electrode (12) and the electrode 1 (33) of the socket (3) are conducted. The electrode 1 (33) is connected via a test head (4) to a voltage, current source and a measurement system. A test start signal is issued with the pickup section (5) holding this, and the operation of the tester is started.

Upon receiving the test start signal, the tester executes a test of each item according to a test program input in advance, and returns a test end signal and a pass / fail classification signal to the handler of the test apparatus after completion.

The handler receiving both signals starts the operation again, and sorts the held IC (1) into the non-defective product storage tray or the defective product storage tray according to the classification signal.

By repeating the above, the pre-burn-in test for the trays in the lot configuration is completed.

After the test, the non-defective storage tray is sent to the next burn-in process. Then, the work of moving the IC (1) from the tray (2) to the burn-in socket (62) of the burn-in board (6) is performed by an apparatus (not shown), and after completion, the board is mounted on a burn-in apparatus (not shown). IC (1) in burn-in board (6) mounted on burn-in device
Is maintained at a high temperature (approximately 70 to 100 ° C.), and is energized to the external electrode (12) via the extraction electrode (65) and the electric wiring of the substrate body (61), and can be stored for about 4 to 24 hours. Done. When the burn-in is completed, the burn-in board (6) is detached from the burn-in device, and the IC (not shown) is used.
An operation of transferring (1) to the tray (2) is performed. The IC (1) on the transferred tray (2) is subjected to a post-burn-in test by the same method and operation as the above-described test before the burn-in.

After the burn-in test, non-defective ICs (1) are packaged and shipped together with trays (2) after quantity control.

[Problems to be solved by the invention]

Conventional IC testing and jigs have been configured as described above, and therefore have the following problems.

: Three kinds of jigs and tools are used.

: There are two steps of inserting and removing ICs from the tray used for transportation between the assembly process and the test process to the burn-in board.

: It is necessary to develop and manufacture a test socket according to the shape of the IC. Further, two types of test sockets, one for test and one for burn-in, must be manufactured for one exterior.

: It is necessary to make a burn-in board independently.

: Because ICs are handled many times, there are many appearance defects such as damage to external electrodes due to mistakes in handling equipment, scratches on resin parts, etc.

: Jig and tool costs are large, and extra processes are not eliminated.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a test jig for a semiconductor device which can reduce the cost of the jig and reduce extra steps.

[Means for solving the problem]

A test jig for a semiconductor device according to the present invention is as follows.

: The use of trays used for transportation between the assembly process and the test process is limited to shipping only.

: No need for test socket and printed wiring electrodes
A tool that also serves as a burn-in board in which the external electrodes of the IC are in direct contact. With this one type of tool,: Receives from the assembly process, performs a pre-burn-in test, performs burn-in, and performs burn-in. Perform later tests.

[Action]

In the test jig for a semiconductor device according to the present invention, in addition to the role of transport between the conventional tray assembly and the test, the electrodes provided by the printed wiring technology have the roles of the electrodes of the conventional test socket and burn-in socket. : Cost for socket development: Burn-in board cost
： IC insertion and removal process cost before and after burn-in ： Of the appearance inspection cost before shipping, the above item is about 100%, the item is current status + α
The term is about -1/2. The term has an original effect of about -60%.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1 is a plan view of a test jig for a semiconductor device according to an embodiment of the present invention, FIG. 2 is an enlarged plan view of a portion A in FIG. 1, and FIG. 3 is a cross section taken along line III-III in FIG. FIG. 4 is a plan view showing a state in which the IC having the structure of the present invention is mounted on the jig and tool shown in FIG. 2, FIG. 5 is a sectional view taken along the line VV in FIG.
FIG. 4 is a plan view showing a state in which a presser 1 for contacting an IC external electrode and a jig tool electrode is attached to FIG. 4, FIG. 7 is a sectional view taken along the line VII-VII of FIG. 6, and FIG. FIG. 6 is a plan view showing a state in which a connection jig for connecting the burn-in pattern wiring on the back surface of the jig and the IC external electrode is mounted, and FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. In the figure,
(7) is a jig / tool having a tray, a test socket, and a burn-in board, and (71) is a reinforcing portion provided on an edge side.
(72) is a pitch hole for conveyance provided in the reinforcement part (71),
(73) is the area where the resin part of the IC to be mounted enters, (74) is
A positioning pin for aligning the center of the external electrode of the IC with the center of the first electrode of the jig (7); (75) a first electrode made by a pattern wiring technique that is directly contacted with the external electrode of the IC;
(76) is electrically connected to the first electrode (75), and the first through-hole (7) is subjected to through-hole processing on the back surface of the jig (7).
7) is a presser 1 for pressing the first electrode (75) and the external electrode of the IC from above.
8) is a second through hole that guides the wiring pattern (79) for burn-in provided on the back surface of the jig (7) to the surface of the jig, (79) is a wiring pattern connected to the extraction electrode (712), ( 710) is the resistance on the wiring pattern (79) circuit, (71)
1) is a jack 2 for connecting the pin plugs at both ends of the connection jig to be connected to connect the second through hole (78) and the first electrode (75) at burn-in, and (712) is a drawer for receiving power from the burn-in device. In order to mount the electrode and (8) on the jig with good positional accuracy, positioning pins (7
4) An embodiment of the structure of the present invention provided with a hole for receiving 4) I
C, (81) is a sealing resin of the IC (8), (82) is an external electrode, (83) is a direction display, (84) is a hole for a positioning pin (74), and (9) is a presser 1. , (91) is an elastic body made of an insulating material, (10) is a spring probe for obtaining a contact with the first through hole (76) during the test, (11) is a connection jig, (111) and (112) are Short pins for connecting the first through hole (76) and the second through hole (78), respectively.

 Next, the operation will be described.

The IC (8) having the hole (84) machined in the resin sealing process is a device (not shown) at the end of the assembling process, in which the hole (84) fits in the positioning pin (74) of the jig (7) in FIG. It is mounted as shown in FIG.

Subsequently, when the presser 1 (9) is attached and a pin plug (not shown) enters the jack 1 (77), the elastic body (91) overlaps the first electrode (75) and the external electrode (82) and presses the contact. I take the. FIG. 6 shows this state. The jig (7) that has been processed as described above is made up of a plurality of lots for each type and sent to a test process before burn-in. The jig (7) having a lot configuration that has come to the test process is set on a handler loader portion of a test device (not shown).
The test apparatus takes one sheet out of the plurality of jigs (7) set and transports it to the test position using the pitch hole (72) of the reinforcing part (71). First IC in jig (7)
When (8) repeats to the test position, the transport stops, and then the spring probe (10) moves to the first through hole (76).
Stop rising to contact This state is indicated by the 7th
FIG.

A test start is issued while holding this, and the operation of the tester is started. Upon receiving the test start signal, the tester executes a test of each item according to a test program input in advance, and returns a test end signal and a pass / fail classification signal to the test device handler after completion.
The handler that received both signals ends the test, lowers the spring probe (10) holding the judge tool NO and ICNO pass / fail classification signals, and moves the jig (7) to the next IC (8) test position. Transport. Then, the above operation is repeated to perform a test. The jig (8), which has completed all the tests of the IC (8) in the jig (7), is transferred to the classification section of the handler section together with the held good / bad classification signal, where the holding tool of the bad IC is held. 1 (9) is withdrawn, and the defective IC (8) is picked up and accommodated in the defective classification location. Then, a connection jig (11) for connecting the first through hole (76) and the second through hole (78) is attached to the non-defective IC. This state is shown in FIG. Bad
The tool (7) from which the IC has been removed is stored in the unloader section of the handler.

By repeating the above, the pre-burn-in test of the jig / tool (7) having the lot configuration is completed. The lot that has completed the pre-burn-in test is then sent to the burn-in process.

The jig (7) is mounted on the burn-in device, and the extraction electrode (712), the wiring pattern (79), the resistor (710), the second through hole (78), and the short pin (111) of the connection jig (11) are provided. (112), through the first through hole (76), the first electrode (75), the external electrodes (82) of the IC (8) are energized and maintained at a high temperature as described in the conventional example. You.

When the burn-in is completed in this way, the jig (7) is detached from the burn-in device, the connection jig (11) is removed, and the burn-in test is sent to the post-burn-in test.

The post-burn-in test is performed in the same manner as the pre-burn-in test described above, and a good IC is stored in the conventional tray (2) (the conventional tray is used for customer shipment). ).

In the present embodiment, a method is described in which a hole (84) is formed in the IC (8) so that the positioning pin (74) can be accommodated. However, the IC remains the same and the sealing resin (11) of the conventional IC (1) is used. May be formed in the area (73) where the resin portion of the IC enters.

〔The invention's effect〕

As described above, according to the present invention: pattern wiring, test and burn-in can be performed with a jig similar to a conventional burn-in board and a relatively inexpensive jig attached to the jig and tool, which is a problem which has conventionally been a problem. No test socket development costs are required.

: The number of times of handling individual ICs is reduced, resulting in a lower appearance defect rate. It is possible to save labor by adopting a sampling process instead of the conventional visual inspection process.

And the like.

[Brief description of the drawings]

1 is a plan view showing a test jig of a semiconductor device according to one embodiment of the present invention, FIG. 2 is an enlarged plan view of a portion A in FIG. 1, and FIG. 3 is a cross section taken along line III-III in FIG. Fig. 4
FIG. 5 is a plan view showing a state in which the IC having the structure of the present invention is mounted on the jig shown in FIG. 5, FIG. 5 is a cross-sectional view taken along the line VV in FIG. 4, and FIG. FIG. 7 is a plan view showing a state where a retainer for contacting the electrode of the tool is attached, FIG. 7 is a cross-sectional view taken along the line VII-VII of FIG. 6, and FIG. FIG. 9 is a plan view showing a state in which a connection jig for connecting IC external electrodes is attached, FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. 8, FIG. Figure 11 shows the first array of conventional ICs.
FIG. 12 is a developed perspective view showing a part of a conventional test apparatus, and FIG. 13 is a perspective view of a burn-in board used for burn-in. In the figure, (7) is a jig, (71) is a reinforcing portion of the jig (7), (72) is a pitch hole, (73) is a range in which the resin portion of the IC enters, (74) is a positioning pin, 75) is the first electrode, (76) is the first through hole, (77) is the jack 1, (78) is the second through hole, (76) is the wiring pattern, (710) is the resistor, (711) ) Is the jack 2, (712) is the extraction electrode, (8) is the IC, (81) is the sealing resin of the IC (8), (82) is the external electrode, (83) is the direction display, and (84) is the hole. , (9) is the holding member 1, (91) is the elastic body of the holding member (9), (10) is a spring probe, (11) is a connection jig,
(111) and (112) indicate short pins of the connection jig (11). In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

(57) [Claims] An electric double-sided wiring is provided on a flat plate made of an insulating material by photoengraving, a first electrode pattern directly in contact with an external electrode of a semiconductor device, a first through-hole electrically connected to the electrode pattern, A second through-hole that is not electrically connected to the first through-hole, has a plurality of wiring patterns that are electrically connected to the second through-hole, and in which electric components can be arranged, And a central portion surrounded by the first electrode has a concave or convex portion on which the semiconductor device is mounted, and the external electrode of the semiconductor device on the first electrode is placed upward. A jig for short-circuiting the first through-hole and the second through-hole, and a second jig for fixing the jig. Have a jack, around Test tools of a semiconductor device, wherein the transport concave and the reinforcing member having a convex portion on.