JP2605781B2 - Automatic diagnostic device for parity circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Table of Contents] Overview Industrial field of application Conventional technology Problems to be solved by the invention Means to solve the problem Action Embodiment Effect of the invention [Overview] Program for diagnosing the function of the parity circuit With regard to an automatic diagnostic device for a parity circuit that can be automatically performed by control, the processing of the program is not interrupted, the parity generator and the parity checker can be tested, and parity error generation control is easy and fast. For the purpose of obtaining, when the processor sends a write command, the processor causes the parity generator of the parity circuit to create an inverted parity check bit and send it to the bus for only one cycle during which the processor accesses the bus. , That the interrupt signal sent by the register to the gate is transmitted to the processor After the execution of the bus access cycle of the processor, the parity generator sends a normal parity check bit. When the processor sends a read command, the parity circuit is transmitted only for one cycle in which the processor accesses the bus. Inverts the parity check bit input to the parity checker and prevents the interrupt signal sent by the register from being transmitted to the processor to the gate. After the processor executes the bus access cycle, the normal parity input to the parity checker is performed. The configuration is such that the inversion of the check bit is prohibited.

[Industrial applications]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic parity circuit diagnostic apparatus that can automatically diagnose the function of a parity circuit under program control.

Generally, a parity circuit is used at the time of signal transmission on a bus or a cable. For example, a parity generation is performed from a transmission side to add a parity bit so that the number of “1” becomes an odd number in byte units. The parity check is performed in units of parity addition including .If the check result is an odd number, it is determined that signal transmission has been performed normally.If the check result is an even number, it is determined that a signal error has occurred during transmission and error processing is performed. Thus, transmission reliability is improved.

By the way, when a failure occurs in the parity circuit itself for improving reliability in this way, even if there is an error in the received data, it cannot be detected, and this may cause a malfunction or runaway of the device on the receiving side. It is necessary to diagnose the parity circuit to confirm its own normality.

For the diagnosis of the parity circuit, it is necessary that the transmission side can intentionally break the parity, and the reception side can confirm in the diagnosis program that the parity error is detected and the subsequent error processing is executed normally. It is indispensable to automate the diagnosis that this diagnostic program is executed by a series of programs together with the diagnostic programs for other circuit functions. It is necessary not to harm the bus to which the input / output device and the memory are connected.

[Conventional technology]

For the diagnosis of the parity circuit, a method of manually forcing one bit of a data line or a parity bit line of a parity addition unit to a logic at which a parity error occurs, and controlling a register value by a control signal are used. Then, there is a method of inverting "1" or "0" of the parity bit line.

[Problems to be solved by the invention]

In the case of manual operation, it is not suitable for automating the diagnosis of the parity circuit, the parity error generation logic is fixed, and when using a register, the control logic is fixed. There are various problems.

In a normal system in which a processor and a target (input / output device or memory) are connected by a bus, a parity error needs to occur only for one cycle of the target bus access. However, if the control signal has a fixed logic, a parity error occurs continuously.If the error processing program after the parity error detection is stored in the memory on the same bus, the same bus is used at the first access of the error processing program. Because of the use, the operation is stopped due to the occurrence of a parity error, and the subsequent error processing program cannot be executed.

In addition, there are some types of errors that cannot be recovered, and it is necessary that these processes be performed with the highest priority. Therefore, a signal notifying the occurrence of an error is normally input to the non-maskable interrupt terminal (NMi terminal) of the processor. Parity errors are also included in this type of error and are input to the NMi terminal. Therefore, if a parity error occurs during diagnosis, there is a disadvantage that the diagnostic program is interrupted by an interrupt signal.

The present invention has been made in view of such a problem, and when automating a diagnosis of a parity circuit by program control, an error processing program and a diagnosis program for executing a diagnosis are not interrupted, and a parity generator and a parity generator are used. When the checker and the shared circuit are configured, it is possible to perform both tests, and if there is a parity circuit between the processor side and the target side connected via the bus,
It is an object of the present invention to enable a test of a parity checker on a processor side even when a target side is not connected to a bus, and to enable easy and high-speed control for generating a parity error.

[Means for solving the problem]

 FIG. 1 is a block diagram showing the principle of the present invention.

The parity circuit 12 is connected to, for example, a data terminal of the processor 1 and performs a parity check on data transferred between the controlled device connected to the bus 17 and the processor 1.

Accordingly, the parity check bit added by the parity generator of the parity circuit 12 to the data sent by the processor 1 is checked together with the data by the parity checker of the parity circuit 19 provided in the controlled device, and whether there is an error in the data or not. If no error is detected and there is an error, this error information is written to the register 13 via the bus 17.

Further, the data sent from the controlled device to the processor 1 is added with a parity check bit by a parity generator of a parity circuit 19 and is checked together with the data by a parity checker of the parity circuit 12. Be included.

When the error information is written, the register 13 sends an interrupt signal to the non-maskable interrupt terminal of the processor 1 via the gate 20.

When testing the parity circuit 12, the processor 1 performs the parity generator test and the parity checker test separately.

When testing the parity generator, the processor 1
Sends a write command to the mode setting means 21. Since the mode setting means 21 is a write command,
An instruction to invert the parity check bit generated by the parity generator of the parity circuit 12 is given to the processor 22, and the processor 1 sends data to the bus 17. Gate 20 is controlled to prevent signals from entering the non-maskable interrupt terminal of processor 1.

After the processor 1 executes this bus access cycle, the mode setting means 21 opens the gate 20 to cause the processor 1 to send an interrupt signal sent from the register 13 to the instruction means 22.
And causes the parity generator of the parity circuit 12 to transmit a normal parity check bit.

When testing the parity checker, the processor 1 sends a read command to the mode setting means 21. Since the mode setting means 21 is a read command, the instruction means 22
Instruction to invert the parity check bit input to the parity checker of the parity circuit 12 and the processor 1 fetches data from the bus 17.
The gate 20 is controlled to prevent the interrupt signal sent from the register 13 from being input to the non-maskable interrupt terminal of the processor 1 during one cycle of accessing the memory.

After the processor 1 executes this bus access cycle, the mode setting means 21 opens the gate 20 to cause the processor 1 to send an interrupt signal sent from the register 13 to the instruction means 22.
After that, a normal parity check bit is input to the parity checker of the parity circuit 12.

The same applies to the case where the parity circuit 12 is connected to the address terminal of the processor 1.

[Action]

With the above configuration, the gate 20 is controlled by the mode setting means 21 so that the parity circuit 12
Prevents the processor 1 from being interrupted by the program due to a non-maskable interrupt signal. The instruction means 22 is a mode setting means.
According to the instruction of 21, in order to prevent the occurrence of a parity error in the operation cycle of the processor 1 after the bus access cycle in which the parity error has occurred, when the diagnosis of the parity circuit is automated by program control, the error processing program and the diagnosis are executed. When the program is not interrupted and the parity generator and the parity checker are configured by a shared circuit, both tests can be performed, and both the processor and the target connected via the bus can be tested. In the case where a parity circuit is provided, even if the target side is not connected to the bus, the test of the parity checker on the processor side can be performed, and the control for generating the parity error can be easily performed at high speed.

〔Example〕

FIG. 2 is a block diagram of a circuit showing one embodiment of the present invention, and FIG. 3 is a time chart for explaining the operation of FIG.

1) Initial setting The microprocessor (MPU) 1 and the registers 5, 8, and 13 are cleared by the reset signal input from the terminal B as shown in * RESET (* indicates valid by logic "0"). ,
It will be in the initial state. That is, the microprocessor 1 receives the reset signal at the RS terminal, and the registers 5, 8, and 13 receive the reset signal at the terminals (not shown).
The outputs of 5, 8, and 13 have logic "0".

2) When parity is intentionally broken and a parity error is detected on the target side. This is performed when the parity checker (PCH) of the parity circuit (PGE / PCH) 19 provided in the memory 18 is connected to the microprocessor side. The parity generator (PGE) of the parity circuit 12 inverts and sends out the parity generate bit to detect a parity error.

The clock from the terminal A is the terminal CL of the microprocessor 1.
The microprocessor 1 sends the address to the address decoder 2 from the ADD terminal in the register setting cycle shown in the MPU operation of FIG. As shown by R * W in FIG. 3, "0" is sent as a write command from the * W terminal to the control circuit 4, the timing control circuit 3, the AND circuit 9, and the bus 17.

The address decoder 2 decodes the address sent from the microprocessor 1 by receiving a signal indicating validity from the AS terminal of the microprocessor 1 and sends "1" to the control circuit 4 as shown in FIG. The control circuit 3 sets "1" as a clock as shown in FIG.
To send to. The control circuit 4 synchronizes with this clock,
As shown in FIG. 3, "0" is sent to the CL terminal of the register 5.

The microprocessor 1 receives D _{1 of the} register 5 from the DATA terminal.
To terminals, in order to inhibit the gate 20 composed of a NAND circuit 6, Q ₁ terminal of the register 5 transmits data for instructing for sending "0", with respect to D ₂ terminal of the register 5, the parity circuit for causing execution of a test, Q ₂ terminal of the register 5 transmits data for instructing for sending "1", the D ₃ terminal of register 5, for performing a parity test data system, register 5 Q ₃ terminal transmits data for instructing for sending "1".

Register 5 is at the falling edge of the signal input to the CL terminal.
Incorporation of an instruction from the microprocessor 1 which is input to the D ₁ to D ₃ terminals, as indicated by the rising edge of the signal to Q _1, Q _2, Q ₃ terminals respectively Figure 3, the Q ₁ terminal sends "0" while the, in the Q _2, Q ₃ terminal sends a "1".

Further, as shown in FIG. 3, the timing control circuit 3 sends the next clock to the control circuit 4 in synchronization with the clock input from the terminal A, and the control circuit 4 synchronizes with this clock and shown in FIG. As described above, “1” is sent to the NAND circuit 7.

Therefore, the NAND circuit 7 sends "0" to the S terminal of the register 8 as shown in FIG. 3, and the NAND circuit 6 irrespective of the output logic of the register 13 as shown in FIG. , "1" is sent to the * NMi terminal of the microprocessor 1. Therefore, the microprocessor 1 is not interrupted by the start of the test of the parity circuit.

Register 8 is set when "0" is input to the S terminal,
As shown in FIG. 3, "1" is applied to the exclusive OR circuit 10 from the Q terminal.
To send to. AND circuit 9 is R * of microprocessor 1
Since "0" is sent from the W terminal, "0" is exclusive ORed
It is sent to the circuit 10. Therefore, the exclusive OR circuit 10 is “1”
Is transmitted to the parity circuit 12, and since the parity circuit 12 is a write command, the output of the exclusive OR circuit 10 is transmitted to the parity generator (PGE). The parity generate bit is inverted and transmitted.

That is, if the parity circuit 12 is a byte-based parity circuit, as shown in FIG. 3, in the bus access cycle of the MPU operation, 8-bit data transmitted from the DATA terminal of the microprocessor 1 is set to "1". A parity check bit having an even number (in the case of an odd parity check) is created and sent to the bus 17 via the buffer 14.

At the same time, the microprocessor 1 accesses the memory 18 for one cycle in the bus access cycle shown in FIG.
An address is transmitted to the T terminal, and data is transmitted from the DATA terminal to the DATA terminal of the memory 18.

Accordingly, the data transmitted by the microprocessor 1 and the parity check bit transmitted through the buffer 14 are checked by the parity checker of the parity circuit 19, and an error is detected as shown in FIG. An error signal is written into the register 13 as shown in FIG.

At this time, the address decoder 2 sets the signal to "0" as shown in FIG. 3 and changes the signal to "1" as shown in FIG. Send out.
Therefore, as shown in FIG.
"0" is sent to the CL terminal.

When the microprocessor 1 sends an address for resetting the register 5 for error detection as shown in the register reset cycle of FIG. 3, the address decoder 2 sets the signal to "0" and then sets the signal to "1". "

The register 8 samples the D terminal at the fall of the signal, and since it is "0", sets the Q terminal to "0" as shown in FIG. The exclusive OR circuit 10 sends “0” to the parity circuit 12 because the AND circuit 9 sends “0”. Therefore, the parity generator of the parity circuit 12 does not perform the process of inverting the parity generate bit in the operation cycle of the processor 1 after the register reset cycle.

In the register reset cycle, the control circuit 4 timing control circuit 3 operates similarly to the case of register set cycle, the register 5 is microprocessor 1 to D ₁ terminal of the register 5 from the DATA terminal, composed of a NAND circuit 6 Register 5 to release the inhibit of the gate 20
Q ₁ terminal sends data for instructing for sending "1",
To D ₂ terminal of the register 5, for instructing the end of the test of the parity circuit, Q ₂ terminal of the register 5 transmits data for instructing for sending "0", the data based on the D ₃ terminal of register 5 Register 5 to indicate the end of the parity test of
Q ₃ pin "0" that sent the data for instructing for sending, as shown in Figure 3, sends a "1" was sent to the NAND circuit 6, the NAND circuit 7 as shown in "0" I do.

Therefore, the NAND circuit 7 keeps sending "1" as shown in FIG. 3, and the register is not reset, and keeps sending "0" from the Q terminal as shown in FIG. or,
The register 13 sends "0" due to the writing of the error signal, and the NAND circuit 6 sends this "0" to the * NMi terminal of the microprocessor 1 as shown in * NMi in FIG. .

The microprocessor 1 receives the non-maskable interrupt, and in the error interrupt processing cycle shown in FIG.
After executing the error interrupt processing routine, "1" is sent as a read command from the R * W terminal in the error register read cycle as shown by R * W in FIG. 3, and the contents of the register 13 are read from the DATA terminal. Since the error signal is written, it is determined that the parity generator of the parity circuit 12 and the parity checker of the parity circuit 19 operate normally.

3) In the case where the parity is intentionally broken and the microprocessor detects a parity error, this is transmitted from the target side, that is, the parity generator of the parity circuit 19 provided in the memory 18 with a normal parity check bit added. Received data,
A normal parity check bit is inverted and input to the parity checker of the parity circuit 12 on the microprocessor side to detect a parity error.

In this case, "1" is sent as a read command from the R * W terminal of the microprocessor 1, but the setting of the registers 5 and 8 is the same as the operation in the register setting cycle in FIG. Then, since "1" is input to the AND circuit 9, in the bus access cycle shown in FIG.
The 16 outputs are sent to the exclusive OR circuit 10.

A normal parity check bit sent from the parity generator of the parity circuit 19 is input to the buffer 16,
The signal is sent to the exclusive OR circuit 10 via the AND circuit 9. As shown in FIG. 3, in the bus access cycle,
Since "1" is sent from the Q terminal of the register 8 to the OR circuit 10, the parity check bit sent from the buffer 16 is inverted and sent to the parity circuit 12, which is a read command. , Exclusive OR circuit 10
Is sent to the parity check bit input side of the parity checker.

Since the normal parity check bit is inverted,
A parity error is detected from the parity checker of the parity circuit 12, and this error signal is detected by the sensor 15 and written into the register 13. After the register reset cycle in FIG. 3, the operation is the same as described above.

If an interrupt is not input to the * NMi terminal of the microprocessor 1 after a certain period of time, it is determined that there is an abnormality in the diagnostic circuit. In this case, if the error signal is not written in the register 13, it is a problem on the memory 18 side, and if it is written, it can be investigated as a problem on the microprocessor 1 side.

The microprocessor 1 reads an error processing program and a diagnostic program from the memory 18, and executes a program execution instruction for instructing the setting of the registers 5 and 8 and the memory 18.
Is read from the internal memory 11.

This is because a parity error occurs in the bus access cycle, so that the program in this portion cannot be read from the memory 18.

Although the above description has been given of the data system, when performing the diagnosis of the address system, the NAND circuit 7, the register 8 and the AN 8 shown in FIG.
D circuit 9 and exclusive OR circuit 10 are separately provided for addresses,
Connect to the parity circuit provided in the address circuit,
Specifies the test address system microprocessor 1 to D ₃ terminal of register 5, NAN output of Q _2, Q ₃ terminal of the register 5
It can be easily realized by sending the data to an address-related NAND circuit corresponding to the D circuit 7.

When the memory 18 is not connected to the bus 17, the microprocessor 1 sends a read command to
Since data of “1” is normally input from a receiver connected to the bus 17 (not shown), whether a bit corresponding to a parity check bit of this data is inverted or not depends on whether a parity error occurs or no parity error occurs. Both tests can be performed. In this case, the internal memory 11
Needless to say, it is necessary to store the error processing program and the diagnostic program in the program.

Although the above description has been made using the memory 18 as a target connected to the bus 17, the same applies to an input / output device instead of the memory 18 .In the case of an input / output device, the internal memory 11 stores an error processing program. It is necessary to store a diagnostic program.

Further, when the memory 18 is further read, if the parity check bit is inverted and no error occurs, it can be determined that there is a problem in the parity generator of the parity circuit 19.

Although register 5 and register 8 are set in the register setting cycle in the MPU operation of FIG.
Is supplied to the registers 5 and 8 respectively.

This means that the setting of registers 5 and 8 and the output conditions are several tens
This is because there is no need to set individual addresses because of the following. Therefore, register setting time can be reduced.

This embodiment shows a data-based parity diagnosis circuit.
For 32-bit data in a bit-wise parity system,
The AND circuit 9, the exclusive OR circuit 10, and the parity circuit 12 are required in units of 8 bits.

When a parity circuit test is performed on an input / output device or a memory connected to each of a plurality of buses, the number of mode setting bits in the register 5 is increased, and a control signal corresponding to each bus is created. The register 8, the NAND circuit 7, the AND circuit 9, the exclusive OR circuit 10, and the parity circuit 12 can also be realized by providing them for each bus.

〔The invention's effect〕

As described above, the present invention can prevent the diagnostic program from being interrupted by the interrupt signal input to the non-maskable interrupt terminal of the processor without the execution of the error processing program being stopped due to the occurrence of the parity error. I can do it.

Further, when the parity generator and the parity checker are configured by a shared circuit, the parity error occurrence control is performed by all registers operating from the processor.
A series of automatic diagnoses is possible, and only the parity checker diagnosis is possible without the target input / output device or memory only on the processor side.

In addition, in the data bits of the parity addition unit, the inversion of the parity generation bits and the parity check bits in all combinations can be controlled. And
The parity generation bit and parity check bit of all bytes of the address or data can be inverted by one control signal, so that each byte test can be completed once each and the diagnosis can be performed reasonably and in a short time. I can do it.

In setting the control register, two types of registers can be set at the same time with one access, and the inversion control register is reset at the end edge of the target bus access cycle, so both the control program and the hardware configuration are easy. It is.

[Brief description of the drawings]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a block diagram of a circuit showing an embodiment of the present invention, and FIG. 3 is a time chart for explaining the operation of FIG. In the figure, 1 is a microprocessor, 2 is an address decoder, 3 is a timing control circuit, 4 is a control circuit, 5, 8, and 13 are registers, 6, and 7 are NAND circuits, 9 is an AND circuit, and 10 is an exclusive OR circuit. Reference numeral 11 is an internal memory, 12 and 19 are parity circuits, 14 and 16 are buffers, 15 is a sensor, 17 is a bus, 18 is a memory, 20 is a gate, 21 is mode setting means, and 22 is instruction means.

Claims (1)

(57) [Claims] 1. A processor, a bus to which a controlled device controlled by the processor is connected, a parity generator connected to the bus, for adding a parity check bit to transmission data from the processor, and an input of the processor. A parity checker for performing error detection by using a parity check bit added to the information; a parity error information transmitted by the parity checker; and a parity error information transmitted from the controlled device. An apparatus comprising: a register for transmitting an interrupt signal; a gate for controlling transmission of the interrupt signal transmitted by the register; transmitting a control signal to the gate; and instructing the parity generator and the parity checker to execute a test. Mode setting means for performing the mode setting A means for instructing the parity generator to invert the parity check bit created by the parity generator or an instruction for inverting the parity check bit checked by the parity checker; In the state, when the processor sends a write command, the parity generator adds an inverted parity check bit to the data for a predetermined period during which the processor sends data, and sends the data. The interrupt signal transmitted by the register is prevented from being transmitted to the processor. After the processor executes the data transmission cycle, the parity generator transmits a normal parity check bit, and the processor transmits a read command. Is a predetermined period during which the processor takes in data. Only inverts the parity check bit input to the parity checker, and the gate prevents transmission of the interrupt signal sent from the register to the processor. After the processor executes the data fetch cycle, the parity checker outputs the parity check bit. In the automatic diagnostic device for a parity circuit, the inversion of an input parity check bit is prohibited.