JP2595736B2 - Semiconductor storage device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a first-in first-out (hereinafter abbreviated as FIFO) type semiconductor memory device.

2. Description of the Related Art In recent years, with the progress of semiconductor process technology, there has been a remarkable use of semiconductor memory devices. In particular, the FIFO type semiconductor memory device has attracted attention in the field of video, and has become indispensable for a Y / C separation circuit for digital signal processing.

Hereinafter, a conventional semiconductor memory device will be described. FIG. 3 shows an example of a conventional semiconductor memory device.

FIFO type semiconductor storage devices used in the video field are often used for 1H delay lines and the like, and this conventional example is an example in which there is a 2H storage capacity for performing arithmetic processing in the vertical direction of the screen. Is a circuit for only one bit. 31 and 32 in FIG.
1H delay path composed of an IFO type semiconductor memory device, 33 is a dynamic unit memory circuit composed of three transistors, 34 is a write address signal line, 35 is a read address signal line, 36 is an address control circuit, 37 is a write data signal line, 38 is a read data signal line, and 39 is an arithmetic circuit.

The operation of the semiconductor memory device configured as described above will be described below.

The input data is written to the unit storage circuit specified by the write address signal line. Further, data is selected and output from the unit storage circuit in the column specified by the read address signal line 35. The unit storage circuit 33 composed of three transistors is composed of N-ch transistors. When the write address signal line 34 or the read address signal line 35 is at a high (“H”) level, respectively, Writing of data from the signal line 37 or transfer of data to the read data signal line 38 is performed.

Each of the delay circuits 31 and 32 has the number of unit storage circuits 33 for 1H lines, and further has an arithmetic circuit 39 for calculating data delayed by each of the delay circuits 31 and 32, and calculates data for three lines on the screen. Thus, it is intended to perform signal processing in the vertical direction of the screen.

However, in the above-mentioned conventional technology, in order to input the input data and the output of each 1H delay circuit to the arithmetic circuit, respectively, when designing a monolithic semiconductor integrated circuit, each 1H delay line is Since it occupies a large area in the design, if wiring for inputting input data and output data of each delay line to the arithmetic circuit is performed, the wiring area increases and the design efficiency of the semiconductor integrated circuit decreases. Was.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problems. A delay circuit using a FIFO type storage circuit having a storage capacity of 2H data is constituted by upper and lower two stages per bit, and a write data signal line and a write data signal line are provided. It is an object of the present invention to provide a semiconductor memory circuit in which a read data selection circuit capable of outputting data of a read data signal line is provided, so that a wiring area of a signal line for inputting to an arithmetic circuit can be almost eliminated.

Means for Solving the Problems In order to achieve this object, a semiconductor memory circuit according to the present invention has a plurality of unit memory circuits arranged on one address signal line, and two rows of unit memory circuits are prepared for one bit. An output data selection circuit is provided for each of the unit memory circuit rows so that data of the write data signal line and the read data signal line can be taken out.

Operation With this configuration, data having a plurality of delay amounts can be extracted from one delay circuit, the design of the arithmetic circuit is easy, and a monolithic semiconductor integrated circuit can be obtained.
The design area of the 2H delay line circuit can be reduced.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a semiconductor memory device according to one embodiment of the present invention. In FIG. 1, 1 is a unit storage circuit, 2 is an address control circuit, 3 is an input data selection circuit,
4 is an output data selection circuit, 5 is a write address signal line, 6 is a read address signal line, 7 is a write data selection circuit, and 8 is an arithmetic circuit.

The operation of this embodiment having the above configuration will be described below. The signal processing circuit of this embodiment is an example in which only one bit of a signal processing circuit in the vertical direction of a screen using a delay circuit performing a FIFO operation often used in the video field is described.

The write address signal line 5 and the read address signal line 6 are alternately set to "H" at a constant period, and the input data is equivalent to 1H per row, and the number of unit storage circuits as a whole (2H).
Is a circuit for obtaining the delayed output data.

At the time of data writing, one of the switches in the input data selection circuit 3 is turned on, and the switch of the write data selection circuit is turned off, so that the write data signal line (10
Input data is transferred to a or 10b), and data is written to any one of the unit storage circuits by the write address signal line 5. At that time, the switch of the write data selection circuit 7 to which input data is not connected (the switch of the input data selection circuit 3 is off) is turned on, and the unit storage device of that row stores the read data. The data is written to itself again, and the refresh operation is performed.

When data is read, the read address signal line 6
To transfer data to the read data signal line (9a or 9b) from the unit storage device 1 designated.

As described above, the write data and the read data of each row of the unit storage circuit are input to the output data selection circuit, and the currently written data and the data delayed by 2H (data before 2H) are output as outputs, and Data delayed by 1H (data before 1H) can be obtained.

Table 1 shows two switches 3a of the input data selection circuit 3.
And 3b on and off, and the data values of each write data signal line and read data signal line (9a, 9b, 10a, 10b).

As described above, according to the present embodiment, three outputs can be simultaneously obtained from the delay circuit having the 2H unit storage circuit, and the output can be connected to the subsequent arithmetic circuit without substantially considering the wiring area.

Further, in FIG. 2, the output of the output data selection circuit 14 is 1
The following is an example. Except for the number of outputs of the output data selection circuit 14 and the number of inputs of the arithmetic circuit 18, the configuration is the same as that of the embodiment shown in FIG. Naturally, the current input data and the 1H and 2H delay signals can be obtained as serial data.

Further, in the present embodiment, an example is shown in which 1-bit data is constituted by two rows of unit storage circuits. However, the effect of the invention is the same even if it is constituted by three or more rows according to the required delay amount. It is.

According to the present invention, a plurality of unit memory circuits are arranged on one address signal line, and two unit memory circuit rows are prepared for one bit, and a write data signal is provided for each of the unit memory circuit rows. By providing an output data selection circuit so that data of the line and the read data signal line can be taken out, data having a plurality of delay amounts can be taken out from one delay circuit. It is possible to obtain the effect that it is almost unnecessary to consider the design area.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a semiconductor memory device according to one embodiment of the present invention, FIG. 2 is a configuration diagram of another embodiment, and FIG. 3 is a configuration diagram of a conventional semiconductor memory device. 1 ... unit storage circuit, 2 ... address control circuit, 3 ...
Input data selection circuit, 4 ... Output data selection circuit, 5 ...
... write address signal line, 6 ... read address signal line, 7 ... write data selection circuit, 8 ... arithmetic circuit, 9a, 9b ... read data signal line, 10a, 10b ... write data signal line.

Claims (1)

(57) [Claims] 1. A storage circuit group in which unit storage circuits capable of writing and reading data are arranged in a matrix, and a plurality of addresses for controlling writing and reading of data to and from the storage circuit group for each column. A signal line, an address control circuit for outputting the plurality of address signal lines, a write data signal line for writing data to the memory circuit group for each row, and a read data signal line for reading data, Further, an input data selection circuit for selecting the distribution of the input data to each row of the storage circuit group, an output signal line of the input data selection circuit and a read data signal line of each row are input, and one of the inputs is provided. A write data selection circuit that outputs the data to the write data signal line, the data of the write data signal line of each row, and the read data signal line. Semiconductor memory device characterized by comprising an output data selection circuit data can be arbitrarily selected.